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Viewing changes to arch/mips/bcm63xx/irq.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
arch/mips/bcm63xx/irq.c
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 * internal IRQs operations: only mask/unmask on PERF irq mask
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 * register.
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 */
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static inline void bcm63xx_internal_irq_mask(unsigned int irq)
 
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static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
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{
 
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        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
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        u32 mask;
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        irq -= IRQ_INTERNAL_BASE;
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        mask = bcm_perf_readl(PERF_IRQMASK_REG);
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        mask &= ~(1 << irq);
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        bcm_perf_writel(mask, PERF_IRQMASK_REG);
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}
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static void bcm63xx_internal_irq_unmask(unsigned int irq)
 
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static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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{
 
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        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
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        u32 mask;
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        irq -= IRQ_INTERNAL_BASE;
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        mask = bcm_perf_readl(PERF_IRQMASK_REG);
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        mask |= (1 << irq);
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        bcm_perf_writel(mask, PERF_IRQMASK_REG);
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}
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static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
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{
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        bcm63xx_internal_irq_unmask(irq);
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        return 0;
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}
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/*
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 * external IRQs operations: mask/unmask and clear on PERF external
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 * irq control register.
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 */
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static void bcm63xx_external_irq_mask(unsigned int irq)
 
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static void bcm63xx_external_irq_mask(struct irq_data *d)
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{
 
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        unsigned int irq = d->irq - IRQ_EXT_BASE;
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        u32 reg;
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        irq -= IRQ_EXT_BASE;
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        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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        reg &= ~EXTIRQ_CFG_MASK(irq);
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        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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}
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static void bcm63xx_external_irq_unmask(unsigned int irq)
 
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static void bcm63xx_external_irq_unmask(struct irq_data *d)
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{
 
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        unsigned int irq = d->irq - IRQ_EXT_BASE;
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        u32 reg;
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        irq -= IRQ_EXT_BASE;
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        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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        reg |= EXTIRQ_CFG_MASK(irq);
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        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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}
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static void bcm63xx_external_irq_clear(unsigned int irq)
 
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static void bcm63xx_external_irq_clear(struct irq_data *d)
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{
 
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        unsigned int irq = d->irq - IRQ_EXT_BASE;
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        u32 reg;
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        irq -= IRQ_EXT_BASE;
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        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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        reg |= EXTIRQ_CFG_CLEAR(irq);
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        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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}
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static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
 
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static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
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{
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        set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
 
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        set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
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        irq_enable_hazard();
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        bcm63xx_external_irq_unmask(irq);
 
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        bcm63xx_external_irq_unmask(d);
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        return 0;
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}
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static void bcm63xx_external_irq_shutdown(unsigned int irq)
 
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static void bcm63xx_external_irq_shutdown(struct irq_data *d)
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{
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        bcm63xx_external_irq_mask(irq);
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        clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
 
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        bcm63xx_external_irq_mask(d);
 
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        clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
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        irq_disable_hazard();
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}
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static int bcm63xx_external_irq_set_type(unsigned int irq,
 
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static int bcm63xx_external_irq_set_type(struct irq_data *d,
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                                         unsigned int flow_type)
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{
 
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        unsigned int irq = d->irq - IRQ_EXT_BASE;
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        u32 reg;
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        struct irq_desc *desc = irq_desc + irq;
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        irq -= IRQ_EXT_BASE;
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        flow_type &= IRQ_TYPE_SENSE_MASK;
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        }
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        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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        if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))  {
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                desc->status |= IRQ_LEVEL;
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                desc->handle_irq = handle_level_irq;
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        } else {
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                desc->handle_irq = handle_edge_irq;
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        }
 
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        irqd_set_trigger_type(d, flow_type);
 
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        if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 
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                __irq_set_handler_locked(d->irq, handle_level_irq);
 
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        else
 
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                __irq_set_handler_locked(d->irq, handle_edge_irq);
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        return 0;
 
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        return IRQ_SET_MASK_OK_NOCOPY;
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}
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static struct irq_chip bcm63xx_internal_irq_chip = {
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        .name           = "bcm63xx_ipic",
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        .startup        = bcm63xx_internal_irq_startup,
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        .shutdown       = bcm63xx_internal_irq_mask,
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        .mask           = bcm63xx_internal_irq_mask,
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        .mask_ack       = bcm63xx_internal_irq_mask,
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        .unmask         = bcm63xx_internal_irq_unmask,
 
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        .irq_mask       = bcm63xx_internal_irq_mask,
 
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        .irq_unmask     = bcm63xx_internal_irq_unmask,
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};
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static struct irq_chip bcm63xx_external_irq_chip = {
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        .name           = "bcm63xx_epic",
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        .startup        = bcm63xx_external_irq_startup,
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        .shutdown       = bcm63xx_external_irq_shutdown,
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        .ack            = bcm63xx_external_irq_clear,
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        .mask           = bcm63xx_external_irq_mask,
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        .unmask         = bcm63xx_external_irq_unmask,
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        .set_type       = bcm63xx_external_irq_set_type,
 
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        .irq_startup    = bcm63xx_external_irq_startup,
 
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        .irq_shutdown   = bcm63xx_external_irq_shutdown,
 
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        .irq_ack        = bcm63xx_external_irq_clear,
 
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        .irq_mask       = bcm63xx_external_irq_mask,
 
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        .irq_unmask     = bcm63xx_external_irq_unmask,
 
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        .irq_set_type   = bcm63xx_external_irq_set_type,
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};
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static struct irqaction cpu_ip2_cascade_action = {
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        mips_cpu_irq_init();
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        for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
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                set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
 
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                irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
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                                         handle_level_irq);
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        for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
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                set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
 
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                irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
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                                         handle_edge_irq);
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        setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);