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#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
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/* This indicates that the processor uses the ISA 2.06 server tlbie
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#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
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/* Enable use of TLB reservation. Processor should support tlbsrx.
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* instruction and MAS0[WQ].
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#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
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#define MMU_FTR_SLB ASM_CONST(0x02000000)
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/* Support 16M large pages
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#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
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/* Supports TLBIEL variant
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#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
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/* Supports tlbies w/o locking
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#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
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/* Large pages can be marked CI
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#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
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/* 1T segments available
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#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
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/* Doesn't support the B bit (1T segment) in SLBIE
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#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
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/* MMU feature bit sets for various CPUs */
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#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
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MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
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#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
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#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
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#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
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#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
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#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
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#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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MMU_FTR_CI_LARGE_PAGE
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#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
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#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
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MMU_FTR_USE_TLBIVAX_BCAST | \
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MMU_FTR_LOCK_BCAST_INVAL | \
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MMU_FTR_USE_TLBRSRV | \
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MMU_FTR_USE_PAIRED_MAS | \
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#ifndef __ASSEMBLY__
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#include <asm/cputable.h>