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* Driver for Micronas drx397xD demodulator
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* Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; If not, see <http://www.gnu.org/licenses/>.
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#define DEBUG /* uncomment if you want debugging output */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/firmware.h>
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#include <linux/slab.h>
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#include <asm/div64.h>
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#include "dvb_frontend.h"
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static const char mod_name[] = "drx397xD";
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#define MAX_CLOCK_DRIFT 200 /* maximal 200 PPM allowed */
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#define _FW_ENTRY(a, b, c) b
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#include "drx397xD_fw.h"
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struct drx397xD_state {
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struct i2c_adapter *i2c;
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struct dvb_frontend frontend;
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struct drx397xD_config config;
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u32 bandwidth_parm; /* internal bandwidth conversions */
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u32 f_osc; /* w90: actual osc frequency [Hz] */
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static const char *blob_name[] = {
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#define _BLOB_ENTRY(a, b) a
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#include "drx397xD_fw.h"
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#define _BLOB_ENTRY(a, b) b
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#include "drx397xD_fw.h"
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const struct firmware *file;
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const u8 *data[ARRAY_SIZE(blob_name)];
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#define _FW_ENTRY(a, b, c) { \
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.lock = __RW_LOCK_UNLOCKED(fw[c].lock), \
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#include "drx397xD_fw.h"
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/* use only with writer lock acquired */
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static void _drx_release_fw(struct drx397xD_state *s, enum fw_ix ix)
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memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
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release_firmware(fw[ix].file);
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static void drx_release_fw(struct drx397xD_state *s)
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enum fw_ix ix = s->chip_rev;
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pr_debug("%s\n", __func__);
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write_lock(&fw[ix].lock);
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if (fw[ix].refcnt == 0)
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_drx_release_fw(s, ix);
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write_unlock(&fw[ix].lock);
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static int drx_load_fw(struct drx397xD_state *s, enum fw_ix ix)
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int i = 0, j, rc = -EINVAL;
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pr_debug("%s\n", __func__);
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if (ix < 0 || ix >= ARRAY_SIZE(fw))
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write_lock(&fw[ix].lock);
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memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
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rc = request_firmware(&fw[ix].file, fw[ix].name, s->i2c->dev.parent);
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printk(KERN_ERR "%s: Firmware \"%s\" not available\n",
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mod_name, fw[ix].name);
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if (!fw[ix].file->data || fw[ix].file->size < 10)
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data = fw[ix].file->data;
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size = fw[ix].file->size;
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if (data[i++] != 2) /* check firmware version */
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case 0x00: /* bytecode */
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case 0x01: /* reset */
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case 0x02: /* sleep */
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case 0xfe: /* name */
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len = strnlen(&data[i], size - i);
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if (i + len + 1 >= size)
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if (data[i + len + 1] != 0)
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for (j = 0; j < ARRAY_SIZE(blob_name); j++) {
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if (strcmp(blob_name[j], &data[i]) == 0) {
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fw[ix].data[j] = &data[i + len + 1];
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pr_debug("Loading %s\n", blob_name[j]);
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case 0xff: /* file terminator */
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printk(KERN_ERR "%s: Firmware is corrupt\n", mod_name);
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_drx_release_fw(s, ix);
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write_unlock(&fw[ix].lock);
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static int write_fw(struct drx397xD_state *s, enum blob_ix ix)
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int len, rc = 0, i = 0;
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struct i2c_msg msg = {
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.addr = s->config.demod_address,
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if (ix < 0 || ix >= ARRAY_SIZE(blob_name)) {
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pr_debug("%s drx_fw_ix_t out of range\n", __func__);
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pr_debug("%s %s\n", __func__, blob_name[ix]);
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read_lock(&fw[s->chip_rev].lock);
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data = fw[s->chip_rev].data[ix];
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case 0: /* bytecode */
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msg.buf = (__u8 *) &data[i];
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if (i2c_transfer(s->i2c, &msg, 1) != 1) {
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read_unlock(&fw[s->chip_rev].lock);
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/* Function is not endian safe, use the RD16 wrapper below */
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static int _read16(struct drx397xD_state *s, __le32 i2c_adr)
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struct i2c_msg msg[2] = {
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.addr = s->config.demod_address,
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.addr = s->config.demod_address,
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*(__le32 *) a = i2c_adr;
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rc = i2c_transfer(s->i2c, msg, 2);
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return le16_to_cpu(v);
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/* Function is not endian safe, use the WR16.. wrappers below */
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static int _write16(struct drx397xD_state *s, __le32 i2c_adr, __le16 val)
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struct i2c_msg msg = {
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.addr = s->config.demod_address,
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*(__le32 *)a = i2c_adr;
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*(__le16 *)&a[4] = val;
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rc = i2c_transfer(s->i2c, &msg, 1);
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#define WR16(ss, adr, val) \
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_write16(ss, I2C_ADR_C0(adr), cpu_to_le16(val))
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#define WR16_E0(ss, adr, val) \
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_write16(ss, I2C_ADR_E0(adr), cpu_to_le16(val))
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#define RD16(ss, adr) \
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_read16(ss, I2C_ADR_C0(adr))
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#define EXIT_RC(cmd) \
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if ((rc = (cmd)) < 0) \
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static int PLL_Set(struct drx397xD_state *s,
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struct dvb_frontend_parameters *fep, int *df_tuner)
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struct dvb_frontend *fe = &s->frontend;
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u32 f_tuner, f = fep->frequency;
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pr_debug("%s\n", __func__);
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if ((f > s->frontend.ops.tuner_ops.info.frequency_max) ||
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(f < s->frontend.ops.tuner_ops.info.frequency_min))
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if (!s->frontend.ops.tuner_ops.set_params ||
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!s->frontend.ops.tuner_ops.get_frequency)
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rc = s->frontend.ops.tuner_ops.set_params(fe, fep);
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rc = s->frontend.ops.tuner_ops.get_frequency(fe, &f_tuner);
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*df_tuner = f_tuner - f;
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pr_debug("%s requested %d [Hz] tuner %d [Hz]\n", __func__, f,
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/* Demodulator helper functions */
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static int SC_WaitForReady(struct drx397xD_state *s)
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pr_debug("%s\n", __func__);
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rc = RD16(s, 0x820043);
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static int SC_SendCommand(struct drx397xD_state *s, int cmd)
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pr_debug("%s\n", __func__);
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WR16(s, 0x820043, cmd);
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rc = RD16(s, 0x820042);
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if ((rc & 0xffff) == 0xffff)
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static int HI_Command(struct drx397xD_state *s, u16 cmd)
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pr_debug("%s\n", __func__);
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rc = WR16(s, 0x420032, cmd);
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rc = RD16(s, 0x420032);
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rc = RD16(s, 0x420031);
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static int HI_CfgCommand(struct drx397xD_state *s)
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pr_debug("%s\n", __func__);
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WR16(s, 0x420033, 0x3973);
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WR16(s, 0x420034, s->config.w50); /* code 4, log 4 */
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WR16(s, 0x420035, s->config.w52); /* code 15, log 9 */
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WR16(s, 0x420036, s->config.demod_address << 1);
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WR16(s, 0x420037, s->config.w56); /* code (set_i2c ?? initX 1 ), log 1 */
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/* WR16(s, 0x420033, 0x3973); */
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if ((s->config.w56 & 8) == 0)
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return HI_Command(s, 3);
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return WR16(s, 0x420032, 0x3);
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static const u8 fastIncrDecLUT_15273[] = {
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0x0e, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x12, 0x13, 0x14,
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0x15, 0x16, 0x17, 0x18, 0x1a, 0x1b, 0x1c, 0x1d, 0x1f
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static const u8 slowIncrDecLUT_15272[] = {
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static int SetCfgIfAgc(struct drx397xD_state *s, struct drx397xD_CfgIfAgc *agc)
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int quot, rem, i, rc = -EINVAL;
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pr_debug("%s\n", __func__);
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if (agc->w04 > 0x3ff)
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EXIT_RC(RD16(s, 0x0c20010));
431
EXIT_RC(WR16(s, 0x0c20010, rc));
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return WR16(s, 0x0c20030, agc->w04 & 0x7ff);
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EXIT_RC(RD16(s, 0x0c20010));
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EXIT_RC(WR16(s, 0x0c20010, rc));
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EXIT_RC(WR16(s, 0x0c20025, (w06 >> 1) & 0x1ff));
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EXIT_RC(WR16(s, 0x0c20031, (w0A - w08) >> 1));
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EXIT_RC(WR16(s, 0x0c20032, ((w0A + w08) >> 1) - 0x1ff));
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EXIT_RC(WR16(s, 0x0c20024, quot));
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i = fastIncrDecLUT_15273[rem / 8];
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EXIT_RC(WR16(s, 0x0c2002d, i));
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EXIT_RC(WR16(s, 0x0c2002e, i));
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i = slowIncrDecLUT_15272[rem / 28];
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EXIT_RC(WR16(s, 0x0c2002b, i));
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rc = WR16(s, 0x0c2002c, i);
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static int SetCfgRfAgc(struct drx397xD_state *s, struct drx397xD_CfgRfAgc *agc)
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pr_debug("%s %d 0x%x 0x%x\n", __func__, agc->d00, w04, w06);
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EXIT_RC(WR16(s, 0x0c20036, w04));
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EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
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EXIT_RC(RD16(s, 0x0c20010));
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EXIT_RC(WR16(s, 0x0c20010, rc));
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EXIT_RC(RD16(s, 0x0c20013));
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EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
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EXIT_RC(RD16(s, 0x0c20010));
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EXIT_RC(WR16(s, 0x0c20010, rc));
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EXIT_RC(WR16(s, 0x0c20051, (w06 >> 4) & 0x3f));
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EXIT_RC(RD16(s, 0x0c20013));
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EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
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EXIT_RC(RD16(s, 0x0c20010));
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EXIT_RC(WR16(s, 0x0c20010, rc));
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EXIT_RC(WR16(s, 0x0c20036, 0));
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EXIT_RC(RD16(s, 0x0c20013));
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rc = WR16(s, 0x0c20013, rc);
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static int GetLockStatus(struct drx397xD_state *s, int *lockstat)
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rc = RD16(s, 0x082004b);
541
if (s->config.d60 != 2)
553
static int CorrectSysClockDeviation(struct drx397xD_state *s)
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pr_debug("%s\n", __func__);
561
if (s->config.d5C == 0) {
562
EXIT_RC(WR16(s, 0x08200e8, 0x010));
563
EXIT_RC(WR16(s, 0x08200e9, 0x113));
567
if (s->config.d5C != 1)
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rc = RD16(s, 0x0820048);
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rc = GetLockStatus(s, &lockstat);
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if ((lockstat & 1) == 0)
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EXIT_RC(WR16(s, 0x0420033, 0x200));
579
EXIT_RC(WR16(s, 0x0420034, 0xc5));
580
EXIT_RC(WR16(s, 0x0420035, 0x10));
581
EXIT_RC(WR16(s, 0x0420036, 0x1));
582
EXIT_RC(WR16(s, 0x0420037, 0xa));
583
EXIT_RC(HI_Command(s, 6));
584
EXIT_RC(RD16(s, 0x0420040));
586
EXIT_RC(RD16(s, 0x0420041));
594
if (!s->bandwidth_parm)
597
/* round & convert to Hz */
598
clk = ((u64) (clk + 0x800000) * s->bandwidth_parm + (1 << 20)) >> 21;
599
clk_limit = s->config.f_osc * MAX_CLOCK_DRIFT / 1000;
601
if (clk - s->config.f_osc * 1000 + clk_limit <= 2 * clk_limit) {
603
pr_debug("%s: osc %d %d [Hz]\n", __func__,
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s->config.f_osc * 1000, clk - s->config.f_osc * 1000);
606
rc = WR16(s, 0x08200e8, 0);
612
static int ConfigureMPEGOutput(struct drx397xD_state *s, int type)
616
pr_debug("%s\n", __func__);
619
if (s->config.w98 == 0) {
626
if (s->config.w9A == 0)
631
EXIT_RC(WR16(s, 0x2150045, 0));
632
EXIT_RC(WR16(s, 0x2150010, si));
633
EXIT_RC(WR16(s, 0x2150011, bp));
634
rc = WR16(s, 0x2150012, (type == 0 ? 0xfff : 0));
640
static int drx_tune(struct drx397xD_state *s,
641
struct dvb_frontend_parameters *fep)
647
u32 edi = 0, ebx = 0, ebp = 0, edx = 0;
648
u16 v20 = 0, v1E = 0, v16 = 0, v14 = 0, v12 = 0, v10 = 0, v0E = 0;
650
int rc, df_tuner = 0;
652
pr_debug("%s %d\n", __func__, s->config.d60);
654
if (s->config.d60 != 2)
656
rc = CorrectSysClockDeviation(s);
661
rc = ConfigureMPEGOutput(s, 0);
666
rc = PLL_Set(s, fep, &df_tuner);
668
printk(KERN_ERR "Error in pll_set\n");
673
a = rc = RD16(s, 0x2150016);
676
b = rc = RD16(s, 0x2150010);
679
c = rc = RD16(s, 0x2150034);
682
d = rc = RD16(s, 0x2150035);
685
rc = WR16(s, 0x2150014, c);
686
rc = WR16(s, 0x2150015, d);
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rc = WR16(s, 0x2150010, 0);
688
rc = WR16(s, 0x2150000, 2);
689
rc = WR16(s, 0x2150036, 0x0fff);
690
rc = WR16(s, 0x2150016, a);
692
rc = WR16(s, 0x2150010, 2);
693
rc = WR16(s, 0x2150007, 0);
694
rc = WR16(s, 0x2150000, 1);
695
rc = WR16(s, 0x2110000, 0);
696
rc = WR16(s, 0x0800000, 0);
697
rc = WR16(s, 0x2800000, 0);
698
rc = WR16(s, 0x2110010, 0x664);
700
rc = write_fw(s, DRXD_ResetECRAM);
701
rc = WR16(s, 0x2110000, 1);
703
rc = write_fw(s, DRXD_InitSC);
707
rc = SetCfgIfAgc(s, &s->config.ifagc);
711
rc = SetCfgRfAgc(s, &s->config.rfagc);
715
if (fep->u.ofdm.transmission_mode != TRANSMISSION_MODE_2K)
717
switch (fep->u.ofdm.transmission_mode) {
718
case TRANSMISSION_MODE_8K:
720
if (s->chip_rev == DRXD_FW_B1)
723
rc = WR16(s, 0x2010010, 0);
732
if (s->chip_rev == DRXD_FW_B1)
735
rc = WR16(s, 0x2010010, 1);
744
switch (fep->u.ofdm.guard_interval) {
745
case GUARD_INTERVAL_1_4:
748
case GUARD_INTERVAL_1_8:
751
case GUARD_INTERVAL_1_16:
754
case GUARD_INTERVAL_1_32:
770
switch (fep->u.ofdm.hierarchy_information) {
773
if (s->chip_rev == DRXD_FW_B1)
775
rc = WR16(s, 0x1c10047, 1);
778
rc = WR16(s, 0x2010012, 1);
793
if (s->chip_rev == DRXD_FW_B1)
795
rc = WR16(s, 0x1c10047, 2);
798
rc = WR16(s, 0x2010012, 2);
813
if (s->chip_rev == DRXD_FW_B1)
815
rc = WR16(s, 0x1c10047, 3);
818
rc = WR16(s, 0x2010012, 3);
833
if (s->chip_rev == DRXD_FW_B1)
835
rc = WR16(s, 0x1c10047, 0);
838
rc = WR16(s, 0x2010012, 0);
841
/* QPSK QAM16 QAM64 */
842
ebx = 0x19f; /* 62 */
843
ebp = 0x1fb; /* 15 */
844
v20 = 0x16a; /* 62 */
845
v1E = 0x195; /* 62 */
846
v16 = 0x1bb; /* 15 */
847
v14 = 0x1ef; /* 15 */
853
switch (fep->u.ofdm.constellation) {
857
if (s->chip_rev == DRXD_FW_B1)
860
rc = WR16(s, 0x1c10046, 0);
863
rc = WR16(s, 0x2010011, 0);
866
rc = WR16(s, 0x201001a, 0x10);
869
rc = WR16(s, 0x201001b, 0);
872
rc = WR16(s, 0x201001c, 0);
875
rc = WR16(s, 0x1c10062, v20);
878
rc = WR16(s, 0x1c1002a, v1C);
881
rc = WR16(s, 0x1c10015, v16);
884
rc = WR16(s, 0x1c10016, v12);
890
if (s->chip_rev == DRXD_FW_B1)
893
rc = WR16(s, 0x1c10046, 1);
896
rc = WR16(s, 0x2010011, 1);
899
rc = WR16(s, 0x201001a, 0x10);
902
rc = WR16(s, 0x201001b, 4);
905
rc = WR16(s, 0x201001c, 0);
908
rc = WR16(s, 0x1c10062, v1E);
911
rc = WR16(s, 0x1c1002a, v1A);
914
rc = WR16(s, 0x1c10015, v14);
917
rc = WR16(s, 0x1c10016, v10);
923
rc = WR16(s, 0x1c10046, 2);
926
rc = WR16(s, 0x2010011, 2);
929
rc = WR16(s, 0x201001a, 0x20);
932
rc = WR16(s, 0x201001b, 8);
935
rc = WR16(s, 0x201001c, 2);
938
rc = WR16(s, 0x1c10062, ebx);
941
rc = WR16(s, 0x1c1002a, v18);
944
rc = WR16(s, 0x1c10015, ebp);
947
rc = WR16(s, 0x1c10016, v0E);
953
if (s->config.s20d24 == 1) {
954
rc = WR16(s, 0x2010013, 0);
956
rc = WR16(s, 0x2010013, 1);
960
switch (fep->u.ofdm.code_rate_HP) {
964
if (s->chip_rev == DRXD_FW_B1)
966
rc = WR16(s, 0x2090011, 0);
970
if (s->chip_rev == DRXD_FW_B1)
972
rc = WR16(s, 0x2090011, 1);
976
if (s->chip_rev == DRXD_FW_B1)
978
rc = WR16(s, 0x2090011, 2);
980
case FEC_5_6: /* 5 */
982
if (s->chip_rev == DRXD_FW_B1)
984
rc = WR16(s, 0x2090011, 3);
986
case FEC_7_8: /* 7 */
988
if (s->chip_rev == DRXD_FW_B1)
990
rc = WR16(s, 0x2090011, 4);
996
switch (fep->u.ofdm.bandwidth) {
1000
case BANDWIDTH_8_MHZ: /* 0 */
1001
case BANDWIDTH_AUTO:
1002
rc = WR16(s, 0x0c2003f, 0x32);
1003
s->bandwidth_parm = ebx = 0x8b8249;
1006
case BANDWIDTH_7_MHZ:
1007
rc = WR16(s, 0x0c2003f, 0x3b);
1008
s->bandwidth_parm = ebx = 0x7a1200;
1011
case BANDWIDTH_6_MHZ:
1012
rc = WR16(s, 0x0c2003f, 0x47);
1013
s->bandwidth_parm = ebx = 0x68a1b6;
1021
rc = WR16(s, 0x08200ec, edx);
1025
rc = RD16(s, 0x0820050);
1028
rc = WR16(s, 0x0820050, rc);
1031
/* Configure bandwidth specific factor */
1032
ebx = div64_u64(((u64) (s->f_osc) << 21) + (ebx >> 1),
1033
(u64)ebx) - 0x800000;
1034
EXIT_RC(WR16(s, 0x0c50010, ebx & 0xffff));
1035
EXIT_RC(WR16(s, 0x0c50011, ebx >> 16));
1037
/* drx397xD oscillator calibration */
1038
ebx = div64_u64(((u64) (s->config.f_if + df_tuner) << 28) +
1039
(s->f_osc >> 1), (u64)s->f_osc);
1042
if (fep->inversion == INVERSION_ON)
1043
ebx = 0x10000000 - ebx;
1045
EXIT_RC(WR16(s, 0x0c30010, ebx & 0xffff));
1046
EXIT_RC(WR16(s, 0x0c30011, ebx >> 16));
1048
EXIT_RC(WR16(s, 0x0800000, 1));
1049
EXIT_RC(RD16(s, 0x0800000));
1052
EXIT_RC(SC_WaitForReady(s));
1053
EXIT_RC(WR16(s, 0x0820042, 0));
1054
EXIT_RC(WR16(s, 0x0820041, v22));
1055
EXIT_RC(WR16(s, 0x0820040, edi));
1056
EXIT_RC(SC_SendCommand(s, 3));
1058
rc = RD16(s, 0x0800000);
1061
WR16(s, 0x0820042, 0);
1062
WR16(s, 0x0820041, 1);
1063
WR16(s, 0x0820040, 1);
1064
SC_SendCommand(s, 1);
1067
rc = WR16(s, 0x2150000, 2);
1068
rc = WR16(s, 0x2150016, a);
1069
rc = WR16(s, 0x2150010, 4);
1070
rc = WR16(s, 0x2150036, 0);
1071
rc = WR16(s, 0x2150000, 1);
1078
/*******************************************************************************
1080
******************************************************************************/
1082
static int drx397x_init(struct dvb_frontend *fe)
1084
struct drx397xD_state *s = fe->demodulator_priv;
1087
pr_debug("%s\n", __func__);
1089
s->config.rfagc.d00 = 2; /* 0x7c */
1090
s->config.rfagc.w04 = 0;
1091
s->config.rfagc.w06 = 0x3ff;
1093
s->config.ifagc.d00 = 0; /* 0x68 */
1094
s->config.ifagc.w04 = 0;
1095
s->config.ifagc.w06 = 140;
1096
s->config.ifagc.w08 = 0;
1097
s->config.ifagc.w0A = 0x3ff;
1098
s->config.ifagc.w0C = 0x388;
1100
/* for signal strenght calculations */
1101
s->config.ss76 = 820;
1102
s->config.ss78 = 2200;
1103
s->config.ss7A = 150;
1109
s->config.f_if = 42800000; /* d14: intermediate frequency [Hz] */
1110
s->config.f_osc = 48000; /* s66 : oscillator frequency [kHz] */
1111
s->config.w92 = 12000;
1113
s->config.w9C = 0x000e;
1114
s->config.w9E = 0x0000;
1116
/* ConfigureMPEGOutput params */
1121
/* get chip revision */
1122
rc = RD16(s, 0x2410019);
1127
printk(KERN_INFO "%s: chip revision A2\n", mod_name);
1128
rc = drx_load_fw(s, DRXD_FW_A2);
1131
rc = (rc >> 12) - 3;
1134
s->flags |= F_SET_0D4h;
1137
s->flags |= F_SET_0D0h;
1143
s->flags |= F_SET_0D4h;
1148
printk(KERN_INFO "%s: chip revision B1.%d\n", mod_name, rc);
1149
rc = drx_load_fw(s, DRXD_FW_B1);
1154
rc = WR16(s, 0x0420033, 0x3973);
1158
rc = HI_Command(s, 2);
1162
if (s->chip_rev == DRXD_FW_A2) {
1163
rc = WR16(s, 0x043012d, 0x47F);
1167
rc = WR16_E0(s, 0x0400000, 0);
1171
if (s->config.w92 > 20000 || s->config.w92 % 4000) {
1172
printk(KERN_ERR "%s: invalid osc frequency\n", mod_name);
1177
rc = WR16(s, 0x2410010, 1);
1180
rc = WR16(s, 0x2410011, 0x15);
1183
rc = WR16(s, 0x2410012, s->config.w92 / 4000);
1187
rc = WR16(s, 0x2410015, 2);
1191
rc = WR16(s, 0x2410017, 0x3973);
1195
s->f_osc = s->config.f_osc * 1000; /* initial estimator */
1199
rc = HI_CfgCommand(s);
1203
rc = write_fw(s, DRXD_InitAtomicRead);
1207
if (s->chip_rev == DRXD_FW_A2) {
1208
rc = WR16(s, 0x2150013, 0);
1213
rc = WR16_E0(s, 0x0400002, 0);
1216
rc = WR16(s, 0x0400002, 0);
1220
if (s->chip_rev == DRXD_FW_A2) {
1221
rc = write_fw(s, DRXD_ResetCEFR);
1225
rc = write_fw(s, DRXD_microcode);
1229
s->config.w9C = 0x0e;
1230
if (s->flags & F_SET_0D0h) {
1232
rc = RD16(s, 0x0c20010);
1234
goto write_DRXD_InitFE_1;
1237
rc = WR16(s, 0x0c20010, rc);
1239
goto write_DRXD_InitFE_1;
1241
rc = RD16(s, 0x0c20011);
1243
goto write_DRXD_InitFE_1;
1246
rc = WR16(s, 0x0c20011, rc);
1248
goto write_DRXD_InitFE_1;
1250
rc = WR16(s, 0x0c20012, 1);
1253
write_DRXD_InitFE_1:
1255
rc = write_fw(s, DRXD_InitFE_1);
1260
if (s->chip_rev == DRXD_FW_B1) {
1261
if (s->flags & F_SET_0D0h)
1264
if (s->flags & F_SET_0D0h)
1268
rc = WR16(s, 0x0C20012, rc);
1272
rc = WR16(s, 0x0C20013, s->config.w9E);
1275
rc = WR16(s, 0x0C20015, s->config.w9C);
1279
rc = write_fw(s, DRXD_InitFE_2);
1282
rc = write_fw(s, DRXD_InitFT);
1285
rc = write_fw(s, DRXD_InitCP);
1288
rc = write_fw(s, DRXD_InitCE);
1291
rc = write_fw(s, DRXD_InitEQ);
1294
rc = write_fw(s, DRXD_InitEC);
1297
rc = write_fw(s, DRXD_InitSC);
1301
rc = SetCfgIfAgc(s, &s->config.ifagc);
1305
rc = SetCfgRfAgc(s, &s->config.rfagc);
1309
rc = ConfigureMPEGOutput(s, 1);
1310
rc = WR16(s, 0x08201fe, 0x0017);
1311
rc = WR16(s, 0x08201ff, 0x0101);
1321
static int drx397x_get_frontend(struct dvb_frontend *fe,
1322
struct dvb_frontend_parameters *params)
1327
static int drx397x_set_frontend(struct dvb_frontend *fe,
1328
struct dvb_frontend_parameters *params)
1330
struct drx397xD_state *s = fe->demodulator_priv;
1332
s->config.s20d24 = 1;
1334
return drx_tune(s, params);
1337
static int drx397x_get_tune_settings(struct dvb_frontend *fe,
1338
struct dvb_frontend_tune_settings
1341
fe_tune_settings->min_delay_ms = 10000;
1342
fe_tune_settings->step_size = 0;
1343
fe_tune_settings->max_drift = 0;
1348
static int drx397x_read_status(struct dvb_frontend *fe, fe_status_t *status)
1350
struct drx397xD_state *s = fe->demodulator_priv;
1353
GetLockStatus(s, &lockstat);
1357
CorrectSysClockDeviation(s);
1358
ConfigureMPEGOutput(s, 1);
1359
*status = FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI;
1362
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
1367
static int drx397x_read_ber(struct dvb_frontend *fe, unsigned int *ber)
1374
static int drx397x_read_snr(struct dvb_frontend *fe, u16 *snr)
1381
static int drx397x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1383
struct drx397xD_state *s = fe->demodulator_priv;
1386
if (s->config.ifagc.d00 == 2) {
1390
rc = RD16(s, 0x0c20035);
1396
/* Signal strength is calculated using the following formula:
1398
* a = 2200 * 150 / (2200 + 150);
1399
* a = a * 3300 / (a + 820);
1400
* b = 2200 * 3300 / (2200 + 820);
1401
* c = (((b-a) * rc) >> 10 + a) << 4;
1402
* strength = ~c & 0xffff;
1404
* The following does the same but with less rounding errors:
1406
*strength = ~(7720 + (rc * 30744 >> 10));
1411
static int drx397x_read_ucblocks(struct dvb_frontend *fe,
1412
unsigned int *ucblocks)
1419
static int drx397x_sleep(struct dvb_frontend *fe)
1424
static void drx397x_release(struct dvb_frontend *fe)
1426
struct drx397xD_state *s = fe->demodulator_priv;
1427
printk(KERN_INFO "%s: release demodulator\n", mod_name);
1435
static struct dvb_frontend_ops drx397x_ops = {
1438
.name = "Micronas DRX397xD DVB-T Frontend",
1440
.frequency_min = 47125000,
1441
.frequency_max = 855250000,
1442
.frequency_stepsize = 166667,
1443
.frequency_tolerance = 0,
1444
.caps = /* 0x0C01B2EAE */
1445
FE_CAN_FEC_1_2 | /* = 0x2, */
1446
FE_CAN_FEC_2_3 | /* = 0x4, */
1447
FE_CAN_FEC_3_4 | /* = 0x8, */
1448
FE_CAN_FEC_5_6 | /* = 0x20, */
1449
FE_CAN_FEC_7_8 | /* = 0x80, */
1450
FE_CAN_FEC_AUTO | /* = 0x200, */
1451
FE_CAN_QPSK | /* = 0x400, */
1452
FE_CAN_QAM_16 | /* = 0x800, */
1453
FE_CAN_QAM_64 | /* = 0x2000, */
1454
FE_CAN_QAM_AUTO | /* = 0x10000, */
1455
FE_CAN_TRANSMISSION_MODE_AUTO | /* = 0x20000, */
1456
FE_CAN_GUARD_INTERVAL_AUTO | /* = 0x80000, */
1457
FE_CAN_HIERARCHY_AUTO | /* = 0x100000, */
1458
FE_CAN_RECOVER | /* = 0x40000000, */
1459
FE_CAN_MUTE_TS /* = 0x80000000 */
1462
.release = drx397x_release,
1463
.init = drx397x_init,
1464
.sleep = drx397x_sleep,
1466
.set_frontend = drx397x_set_frontend,
1467
.get_tune_settings = drx397x_get_tune_settings,
1468
.get_frontend = drx397x_get_frontend,
1470
.read_status = drx397x_read_status,
1471
.read_snr = drx397x_read_snr,
1472
.read_signal_strength = drx397x_read_signal_strength,
1473
.read_ber = drx397x_read_ber,
1474
.read_ucblocks = drx397x_read_ucblocks,
1477
struct dvb_frontend *drx397xD_attach(const struct drx397xD_config *config,
1478
struct i2c_adapter *i2c)
1480
struct drx397xD_state *state;
1482
/* allocate memory for the internal state */
1483
state = kzalloc(sizeof(struct drx397xD_state), GFP_KERNEL);
1487
/* setup the state */
1489
memcpy(&state->config, config, sizeof(struct drx397xD_config));
1491
/* check if the demod is there */
1492
if (RD16(state, 0x2410019) < 0)
1495
/* create dvb_frontend */
1496
memcpy(&state->frontend.ops, &drx397x_ops,
1497
sizeof(struct dvb_frontend_ops));
1498
state->frontend.demodulator_priv = state;
1500
return &state->frontend;
1506
EXPORT_SYMBOL(drx397xD_attach);
1508
MODULE_DESCRIPTION("Micronas DRX397xD DVB-T Frontend");
1509
MODULE_AUTHOR("Henk Vergonet");
1510
MODULE_LICENSE("GPL");