~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise : revision 29

1

/* bnx2x_main.c: Broadcom Everest network driver.

2

*

3

4

*

5

* This program is free software; you can redistribute it and/or modify

6

* it under the terms of the GNU General Public License as published by

49

#include <linux/zlib.h>

50

#include <linux/io.h>

51

#include <linux/stringify.h>

52

#include <linux/vmalloc.h>

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53

54

#define BNX2X_MAIN

54

55

#include "bnx2x.h"

145

146

{ "Broadcom NetXtreme II BCM57712E XGb" }

146

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};

147

148

#ifndef PCI_DEVICE_ID_NX2_57712

149

#define PCI_DEVICE_ID_NX2_57712 0x1662

150

#endif

151

#ifndef PCI_DEVICE_ID_NX2_57712E

152

#define PCI_DEVICE_ID_NX2_57712E 0x1663

153

#endif

154

155

149

static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {

156

150

{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },

157

151

{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },

578

572

struct dmae_command *dmae)

579

573

{

580

574

u32 *wb_comp = bnx2x_sp(bp, wb_comp);

581

int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;

575

int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;

582

576

int rc = 0;

583

577

584

578

DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",

586

580

bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);

587

581

588

582

/* lock the dmae channel */

589

mutex_lock(&bp->dmae_mutex);

583

spin_lock_bh(&bp->dmae_lock);

590

584

591

585

/* reset completion */

592

586

*wb_comp = 0;

617

611

bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);

618

612

619

613

unlock:

620

mutex_unlock(&bp->dmae_mutex);

614

spin_unlock_bh(&bp->dmae_lock);

621

615

return rc;

622

616

}

623

617

1397

1391

}

1398

1392

1399

1393

smp_mb__before_atomic_inc();

1400

atomic_inc(&bp->spq_left);

1394

atomic_inc(&bp->cq_spq_left);

1401

1395

/* push the change in fp->state and towards the memory */

1402

1396

smp_wmb();

1403

1397

2043

2037

return CMNG_FNS_NONE;

2044

2038

}

2045

2039

2046

static void bnx2x_read_mf_cfg(struct bnx2x *bp)

2040

void bnx2x_read_mf_cfg(struct bnx2x *bp)

2047

2041

{

2048

2042

int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);

2049

2043

2130

2124

/* This function is called upon link interrupt */

2131

2125

static void bnx2x_link_attn(struct bnx2x *bp)

2132

2126

{

2133

u32 prev_link_status = bp->link_vars.link_status;

2134

2127

/* Make sure that we are synced with the current statistics */

2135

2128

bnx2x_stats_handle(bp, STATS_EVENT_STOP);

2136

2129

2175

2168

"single function mode without fairness\n");

2176

2169

}

2177

2170

2171

__bnx2x_link_report(bp);

2172

2178

2173

if (IS_MF(bp))

2179

2174

bnx2x_link_sync_notify(bp);

2180

2181

/* indicate link status only if link status actually changed */

2182

if (prev_link_status != bp->link_vars.link_status)

2183

bnx2x_link_report(bp);

2184

2175

}

2185

2176

2186

2177

void bnx2x__link_status_update(struct bnx2x *bp)

2187

2178

{

2188

if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))

2179

if (bp->state != BNX2X_STATE_OPEN)

2189

2180

return;

2190

2181

2191

2182

bnx2x_link_status_update(&bp->link_params, &bp->link_vars);

2195

2186

else

2196

2187

bnx2x_stats_handle(bp, STATS_EVENT_STOP);

2197

2188

2198

/* the link status update could be the result of a DCC event

2199

hence re-read the shmem mf configuration */

2200

bnx2x_read_mf_cfg(bp);

2201

2202

2189

/* indicate link status */

2203

2190

bnx2x_link_report(bp);

2204

2191

}

2236

2223

u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)

2237

2224

{

2238

2225

int mb_idx = BP_FW_MB_IDX(bp);

2239

u32 seq = ++bp->fw_seq;

2226

u32 seq;

2240

2227

u32 rc = 0;

2241

2228

u32 cnt = 1;

2242

2229

u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;

2243

2230

2244

2231

mutex_lock(&bp->fw_mb_mutex);

2232

seq = ++bp->fw_seq;

2245

2233

SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);

2246

2234

SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));

2247

2235

2484

2472

rxq_init->sge_map = fp->rx_sge_mapping;

2485

2473

rxq_init->rcq_map = fp->rx_comp_mapping;

2486

2474

rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;

2487

rxq_init->mtu = bp->dev->mtu;

2488

rxq_init->buf_sz = bp->rx_buf_size;

2475

2476

/* Always use mini-jumbo MTU for FCoE L2 ring */

2477

if (IS_FCOE_FP(fp))

2478

rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;

2479

else

2480

rxq_init->mtu = bp->dev->mtu;

2481

2482

rxq_init->buf_sz = fp->rx_buf_size;

2489

2483

rxq_init->cl_qzone_id = fp->cl_qzone_id;

2490

2484

rxq_init->cl_id = fp->cl_id;

2491

2485

rxq_init->spcl_id = fp->cl_id;

2737

2731

2738

2732

spin_lock_bh(&bp->spq_lock);

2739

2733

2740

if (!atomic_read(&bp->spq_left)) {

2741

BNX2X_ERR("BUG! SPQ ring full!\n");

2742

spin_unlock_bh(&bp->spq_lock);

2743

bnx2x_panic();

2744

return -EBUSY;

2734

if (common) {

2735

if (!atomic_read(&bp->eq_spq_left)) {

2736

BNX2X_ERR("BUG! EQ ring full!\n");

2737

spin_unlock_bh(&bp->spq_lock);

2738

bnx2x_panic();

2739

return -EBUSY;

2740

}

2741

} else if (!atomic_read(&bp->cq_spq_left)) {

2742

BNX2X_ERR("BUG! SPQ ring full!\n");

2743

spin_unlock_bh(&bp->spq_lock);

2744

bnx2x_panic();

2745

return -EBUSY;

2745

2746

}

2746

2747

2748

spe = bnx2x_sp_get_next(bp);

2772

2773

spe->data.update_data_addr.lo = cpu_to_le32(data_lo);

2773

2774

2775

/* stats ramrod has it's own slot on the spq */

2775

if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY)

2776

if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {

2776

2777

/* It's ok if the actual decrement is issued towards the memory

2777

2778

* somewhere between the spin_lock and spin_unlock. Thus no

2778

2779

* more explict memory barrier is needed.

2779

2780

*/

2780

atomic_dec(&bp->spq_left);

2781

if (common)

2782

atomic_dec(&bp->eq_spq_left);

2783

else

2784

atomic_dec(&bp->cq_spq_left);

2785

}

2786

2781

2787

2782

2788

DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,

2783

2789

"SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "

2784

"type(0x%x) left %x\n",

2790

"type(0x%x) left (ETH, COMMON) (%x,%x)\n",

2785

2791

bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),

2786

2792

(u32)(U64_LO(bp->spq_mapping) +

2787

2793

(void *)bp->spq_prod_bd - (void *)bp->spq), command,

2788

HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));

2794

HW_CID(bp, cid), data_hi, data_lo, type,

2795

atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));

2789

2796

2790

2797

bnx2x_sp_prod_update(bp);

2791

2798

spin_unlock_bh(&bp->spq_lock);

3108

3115

if (val & DRV_STATUS_SET_MF_BW)

3109

3116

bnx2x_set_mf_bw(bp);

3110

3117

3111

bnx2x__link_status_update(bp);

3112

3118

if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))

3113

3119

bnx2x_pmf_update(bp);

3114

3120

3121

/* Always call it here: bnx2x_link_report() will

3122

* prevent the link indication duplication.

3123

*/

3124

bnx2x__link_status_update(bp);

3125

3115

3126

if (bp->port.pmf &&

3116

3127

(val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&

3117

3128

bp->dcbx_enabled > 0)

3657

3668

union event_ring_elem *elem)

3658

3669

{

3659

3670

if (!bp->cnic_eth_dev.starting_cid ||

3660

cid < bp->cnic_eth_dev.starting_cid)

3671

(cid < bp->cnic_eth_dev.starting_cid &&

3672

cid != bp->cnic_eth_dev.iscsi_l2_cid))

3661

3673

return 1;

3662

3674

3663

3675

DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);

3690

3702

if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)

3691

3703

hw_cons++;

3692

3704

3693

/* This function may never run in parralel with itself for a

3705

/* This function may never run in parallel with itself for a

3694

3706

* specific bp, thus there is no need in "paired" read memory

3695

3707

* barrier here.

3696

3708

*/

3697

3709

sw_cons = bp->eq_cons;

3698

3710

sw_prod = bp->eq_prod;

3699

3711

3700

DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->spq_left %u\n",

3701

hw_cons, sw_cons, atomic_read(&bp->spq_left));

3712

DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",

3713

hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));

3702

3714

3703

3715

for (; sw_cons != hw_cons;

3704

3716

sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {

3763

3775

case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):

3764

3776

case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):

3765

3777

DP(NETIF_MSG_IFUP, "got set mac ramrod\n");

3766

bp->set_mac_pending = 0;

3778

if (elem->message.data.set_mac_event.echo)

3779

bp->set_mac_pending = 0;

3767

3780

break;

3768

3781

3769

3782

case (EVENT_RING_OPCODE_SET_MAC |

3770

3783

BNX2X_STATE_CLOSING_WAIT4_HALT):

3771

3784

DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");

3772

bp->set_mac_pending = 0;

3785

if (elem->message.data.set_mac_event.echo)

3786

bp->set_mac_pending = 0;

3773

3787

break;

3774

3788

default:

3775

3789

/* unknown event log error and continue */

3781

3795

} /* for */

3782

3796

3783

3797

smp_mb__before_atomic_inc();

3784

atomic_add(spqe_cnt, &bp->spq_left);

3798

atomic_add(spqe_cnt, &bp->eq_spq_left);

3785

3799

3786

3800

bp->eq_cons = sw_cons;

3787

3801

bp->eq_prod = sw_prod;

3890

3904

3891

3905

if (poll) {

3892

3906

struct bnx2x_fastpath *fp = &bp->fp[0];

3893

int rc;

3894

3907

3895

3908

bnx2x_tx_int(fp);

3896

rc = bnx2x_rx_int(fp, 1000);

3909

bnx2x_rx_int(fp, 1000);

3897

3910

}

3898

3911

3899

3912

if (!BP_NOMCP(bp)) {

4048

4061

struct hc_status_block_data_e2 sb_data_e2;

4049

4062

struct hc_status_block_data_e1x sb_data_e1x;

4050

4063

struct hc_status_block_sm *hc_sm_p;

4051

struct hc_index_data *hc_index_p;

4052

4064

int data_size;

4053

4065

u32 *sb_data_p;

4054

4066

4069

4081

sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);

4070

4082

sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);

4071

4083

hc_sm_p = sb_data_e2.common.state_machine;

4072

hc_index_p = sb_data_e2.index_data;

4073

4084

sb_data_p = (u32 *)&sb_data_e2;

4074

4085

data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);

4075

4086

} else {

4083

4094

sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);

4084

4095

sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);

4085

4096

hc_sm_p = sb_data_e1x.common.state_machine;

4086

hc_index_p = sb_data_e1x.index_data;

4087

4097

sb_data_p = (u32 *)&sb_data_e1x;

4088

4098

data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);

4089

4099

}

4208

4218

4209

4219

for_each_eth_queue(bp, i)

4210

4220

bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,

4211

bp->rx_ticks, bp->tx_ticks);

4221

bp->tx_ticks, bp->rx_ticks);

4212

4222

}

4213

4223

4214

4224

static void bnx2x_init_sp_ring(struct bnx2x *bp)

4215

4225

{

4216

4226

spin_lock_init(&bp->spq_lock);

4217

atomic_set(&bp->spq_left, MAX_SPQ_PENDING);

4227

atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);

4218

4228

4219

4229

bp->spq_prod_idx = 0;

4220

4230

bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;

4239

4249

bp->eq_cons = 0;

4240

4250

bp->eq_prod = NUM_EQ_DESC;

4241

4251

bp->eq_cons_sb = BNX2X_EQ_INDEX;

4252

/* we want a warning message before it gets rought... */

4253

atomic_set(&bp->eq_spq_left,

4254

min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);

4242

4255

}

4243

4256

4244

static void bnx2x_init_ind_table(struct bnx2x *bp)

4257

void bnx2x_push_indir_table(struct bnx2x *bp)

4245

4258

{

4246

4259

int func = BP_FUNC(bp);

4247

4260

int i;

4249

4262

if (bp->multi_mode == ETH_RSS_MODE_DISABLED)

4250

4263

return;

4251

4264

4252

DP(NETIF_MSG_IFUP,

4253

"Initializing indirection table multi_mode %d\n", bp->multi_mode);

4254

4265

for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)

4255

4266

REG_WR8(bp, BAR_TSTRORM_INTMEM +

4256

4267

TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,

4257

bp->fp->cl_id + (i % (bp->num_queues -

4258

NONE_ETH_CONTEXT_USE)));

4268

bp->fp->cl_id + bp->rx_indir_table[i]);

4269

}

4270

4271

static void bnx2x_init_ind_table(struct bnx2x *bp)

4272

{

4273

int i;

4274

4275

for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)

4276

bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);

4277

4278

bnx2x_push_indir_table(bp);

4259

4279

}

4260

4280

4261

4281

void bnx2x_set_storm_rx_mode(struct bnx2x *bp)

4430

4450

4431

4451

fp->state = BNX2X_FP_STATE_CLOSED;

4432

4452

4433

fp->index = fp->cid = fp_idx;

4453

fp->cid = fp_idx;

4434

4454

fp->cl_id = BP_L_ID(bp) + fp_idx;

4435

4455

fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;

4436

4456

fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;

4518

4538

if (bp->strm == NULL)

4519

4539

goto gunzip_nomem2;

4520

4540

4521

bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),

4522

GFP_KERNEL);

4541

bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());

4523

4542

if (bp->strm->workspace == NULL)

4524

4543

goto gunzip_nomem3;

4525

4544

4542

4561

4543

4562

static void bnx2x_gunzip_end(struct bnx2x *bp)

4544

4563

{

4545

kfree(bp->strm->workspace);

4546

kfree(bp->strm);

4547

bp->strm = NULL;

4564

if (bp->strm) {

4565

vfree(bp->strm->workspace);

4566

kfree(bp->strm);

4567

bp->strm = NULL;

4568

}

4548

4569

4549

4570

if (bp->gunzip_buf) {

4550

4571

dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,

5065

5086

/* Step 1: set zeroes to all ilt page entries with valid bit on

5066

5087

* Step 2: set the timers first/last ilt entry to point

5067

5088

* to the entire range to prevent ILT range error for 3rd/4th

5068

* vnic (this code assumes existance of the vnic)

5089

* vnic (this code assumes existence of the vnic)

5069

5090

*

5070

5091

* both steps performed by call to bnx2x_ilt_client_init_op()

5071

5092

* with dummy TM client

5851

5872

BP_ABS_FUNC(bp), load_code);

5852

5873

5853

5874

bp->dmae_ready = 0;

5854

mutex_init(&bp->dmae_mutex);

5855

rc = bnx2x_gunzip_init(bp);

5856

if (rc)

5857

return rc;

5875

spin_lock_init(&bp->dmae_lock);

5858

5876

5859

5877

switch (load_code) {

5860

5878

case FW_MSG_CODE_DRV_LOAD_COMMON:

5898

5916

5899

5917

void bnx2x_free_mem(struct bnx2x *bp)

5900

5918

{

5901

5902

#define BNX2X_PCI_FREE(x, y, size) \

5903

do { \

5904

if (x) { \

5905

dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \

5906

x = NULL; \

5907

y = 0; \

5908

} \

5909

} while (0)

5910

5911

#define BNX2X_FREE(x) \

5912

do { \

5913

if (x) { \

5914

kfree((void *)x); \

5915

x = NULL; \

5916

} \

5917

} while (0)

5918

5919

int i;

5919

bnx2x_gunzip_end(bp);

5920

5921

/* fastpath */

5922

/* Common */

5923

for_each_queue(bp, i) {

5924

#ifdef BCM_CNIC

5925

/* FCoE client uses default status block */

5926

if (IS_FCOE_IDX(i)) {

5927

union host_hc_status_block *sb =

5928

&bnx2x_fp(bp, i, status_blk);

5929

memset(sb, 0, sizeof(union host_hc_status_block));

5930

bnx2x_fp(bp, i, status_blk_mapping) = 0;

5931

} else {

5932

#endif

5933

/* status blocks */

5934

if (CHIP_IS_E2(bp))

5935

BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),

5936

bnx2x_fp(bp, i, status_blk_mapping),

5937

sizeof(struct host_hc_status_block_e2));

5938

else

5939

BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),

5940

bnx2x_fp(bp, i, status_blk_mapping),

5941

sizeof(struct host_hc_status_block_e1x));

5942

#ifdef BCM_CNIC

5943

}

5944

#endif

5945

}

5946

/* Rx */

5947

for_each_rx_queue(bp, i) {

5948

5949

/* fastpath rx rings: rx_buf rx_desc rx_comp */

5950

BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));

5951

BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),

5952

bnx2x_fp(bp, i, rx_desc_mapping),

5953

sizeof(struct eth_rx_bd) * NUM_RX_BD);

5954

5955

BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),

5956

bnx2x_fp(bp, i, rx_comp_mapping),

5957

sizeof(struct eth_fast_path_rx_cqe) *

5958

NUM_RCQ_BD);

5959

5960

/* SGE ring */

5961

BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));

5962

BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),

5963

bnx2x_fp(bp, i, rx_sge_mapping),

5964

BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);

5965

}

5966

/* Tx */

5967

for_each_tx_queue(bp, i) {

5968

5969

/* fastpath tx rings: tx_buf tx_desc */

5970

BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));

5971

BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),

5972

bnx2x_fp(bp, i, tx_desc_mapping),

5973

sizeof(union eth_tx_bd_types) * NUM_TX_BD);

5974

}

5922

bnx2x_free_fp_mem(bp);

5975

5923

/* end of fastpath */

5976

5924

5977

5925

BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,

6003

5951

BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,

6004

5952

BCM_PAGE_SIZE * NUM_EQ_PAGES);

6005

5953

6006

#undef BNX2X_PCI_FREE

6007

#undef BNX2X_KFREE

5954

BNX2X_FREE(bp->rx_indir_table);

6008

5955

}

6009

5956

6010

static inline void set_sb_shortcuts(struct bnx2x *bp, int index)

6011

{

6012

union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);

6013

if (CHIP_IS_E2(bp)) {

6014

bnx2x_fp(bp, index, sb_index_values) =

6015

(__le16 *)status_blk.e2_sb->sb.index_values;

6016

bnx2x_fp(bp, index, sb_running_index) =

6017

(__le16 *)status_blk.e2_sb->sb.running_index;

6018

} else {

6019

bnx2x_fp(bp, index, sb_index_values) =

6020

(__le16 *)status_blk.e1x_sb->sb.index_values;

6021

bnx2x_fp(bp, index, sb_running_index) =

6022

(__le16 *)status_blk.e1x_sb->sb.running_index;

6023

}

6024

}

6025

5957

6026

5958

int bnx2x_alloc_mem(struct bnx2x *bp)

6027

5959

{

6028

#define BNX2X_PCI_ALLOC(x, y, size) \

6029

do { \

6030

x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \

6031

if (x == NULL) \

6032

goto alloc_mem_err; \

6033

memset(x, 0, size); \

6034

} while (0)

6035

6036

#define BNX2X_ALLOC(x, size) \

6037

do { \

6038

x = kzalloc(size, GFP_KERNEL); \

6039

if (x == NULL) \

6040

goto alloc_mem_err; \

6041

} while (0)

6042

6043

int i;

6044

6045

/* fastpath */

6046

/* Common */

6047

for_each_queue(bp, i) {

6048

union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);

6049

bnx2x_fp(bp, i, bp) = bp;

6050

/* status blocks */

6051

#ifdef BCM_CNIC

6052

if (!IS_FCOE_IDX(i)) {

6053

#endif

6054

if (CHIP_IS_E2(bp))

6055

BNX2X_PCI_ALLOC(sb->e2_sb,

6056

&bnx2x_fp(bp, i, status_blk_mapping),

6057

sizeof(struct host_hc_status_block_e2));

6058

else

6059

BNX2X_PCI_ALLOC(sb->e1x_sb,

6060

&bnx2x_fp(bp, i, status_blk_mapping),

6061

sizeof(struct host_hc_status_block_e1x));

6062

#ifdef BCM_CNIC

6063

}

6064

#endif

6065

set_sb_shortcuts(bp, i);

6066

}

6067

/* Rx */

6068

for_each_queue(bp, i) {

6069

6070

/* fastpath rx rings: rx_buf rx_desc rx_comp */

6071

BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),

6072

sizeof(struct sw_rx_bd) * NUM_RX_BD);

6073

BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),

6074

&bnx2x_fp(bp, i, rx_desc_mapping),

6075

sizeof(struct eth_rx_bd) * NUM_RX_BD);

6076

6077

BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),

6078

&bnx2x_fp(bp, i, rx_comp_mapping),

6079

sizeof(struct eth_fast_path_rx_cqe) *

6080

NUM_RCQ_BD);

6081

6082

/* SGE ring */

6083

BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),

6084

sizeof(struct sw_rx_page) * NUM_RX_SGE);

6085

BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),

6086

&bnx2x_fp(bp, i, rx_sge_mapping),

6087

BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);

6088

}

6089

/* Tx */

6090

for_each_queue(bp, i) {

6091

6092

/* fastpath tx rings: tx_buf tx_desc */

6093

BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),

6094

sizeof(struct sw_tx_bd) * NUM_TX_BD);

6095

BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),

6096

&bnx2x_fp(bp, i, tx_desc_mapping),

6097

sizeof(union eth_tx_bd_types) * NUM_TX_BD);

6098

}

6099

/* end of fastpath */

5960

if (bnx2x_gunzip_init(bp))

5961

return -ENOMEM;

6100

5962

6101

5963

#ifdef BCM_CNIC

6102

5964

if (CHIP_IS_E2(bp))

6133

5995

/* EQ */

6134

5996

BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,

6135

5997

BCM_PAGE_SIZE * NUM_EQ_PAGES);

5998

5999

BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *

6000

TSTORM_INDIRECTION_TABLE_SIZE);

6001

6002

/* fastpath */

6003

/* need to be done at the end, since it's self adjusting to amount

6004

* of memory available for RSS queues

6005

*/

6006

if (bnx2x_alloc_fp_mem(bp))

6007

goto alloc_mem_err;

6136

6008

return 0;

6137

6009

6138

6010

alloc_mem_err:

6139

6011

bnx2x_free_mem(bp);

6140

6012

return -ENOMEM;

6141

6142

#undef BNX2X_PCI_ALLOC

6143

#undef BNX2X_ALLOC

6144

6013

}

6145

6014

6146

6015

/*

6168

6037

}

6169

6038

6170

6039

/**

6171

* Sets a MAC in a CAM for a few L2 Clients for E1x chips

6040

* bnx2x_set_mac_addr_gen - set a MAC in a CAM for a few L2 Clients for E1x chips

6172

6041

*

6173

* @param bp driver descriptor

6174

* @param set set or clear an entry (1 or 0)

6175

* @param mac pointer to a buffer containing a MAC

6176

* @param cl_bit_vec bit vector of clients to register a MAC for

6177

* @param cam_offset offset in a CAM to use

6178

* @param is_bcast is the set MAC a broadcast address (for E1 only)

6042

* @bp: driver handle

6043

* @set: set or clear an entry (1 or 0)

6044

* @mac: pointer to a buffer containing a MAC

6045

* @cl_bit_vec: bit vector of clients to register a MAC for

6046

* @cam_offset: offset in a CAM to use

6047

* @is_bcast: is the set MAC a broadcast address (for E1 only)

6179

6048

*/

6180

6049

static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,

6181

6050

u32 cl_bit_vec, u8 cam_offset,

6186

6055

int ramrod_flags = WAIT_RAMROD_COMMON;

6187

6056

6188

6057

bp->set_mac_pending = 1;

6189

smp_wmb();

6190

6058

6191

6059

config->hdr.length = 1;

6192

6060

config->hdr.offset = cam_offset;

6193

6061

config->hdr.client_id = 0xff;

6194

config->hdr.reserved1 = 0;

6062

/* Mark the single MAC configuration ramrod as opposed to a

6063

* UC/MC list configuration).

6064

*/

6065

config->hdr.echo = 1;

6195

6066

6196

6067

/* primary MAC */

6197

6068

config->config_table[0].msb_mac_addr =

6223

6094

config->config_table[0].middle_mac_addr,

6224

6095

config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);

6225

6096

6097

mb();

6098

6226

6099

bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,

6227

6100

U64_HI(bnx2x_sp_mapping(bp, mac_config)),

6228

6101

U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);

6287

6160

if (CHIP_IS_E1H(bp))

6288

6161

return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);

6289

6162

else if (CHIP_MODE_IS_4_PORT(bp))

6290

return BP_FUNC(bp) * 32 + rel_offset;

6163

return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);

6291

6164

else

6292

return BP_VN(bp) * 32 + rel_offset;

6165

return E2_FUNC_MAX * rel_offset + BP_VN(bp);

6293

6166

}

6294

6167

6295

6168

/**

6296

6169

* LLH CAM line allocations: currently only iSCSI and ETH macs are

6297

6170

* relevant. In addition, current implementation is tuned for a

6298

6171

* single ETH MAC.

6299

*

6300

* When multiple unicast ETH MACs PF configuration in switch

6301

* independent mode is required (NetQ, multiple netdev MACs,

6302

* etc.), consider better utilisation of 16 per function MAC

6303

* entries in the LLH memory.

6304

6172

*/

6305

6173

enum {

6306

6174

LLH_CAM_ISCSI_ETH_LINE = 0,

6375

6243

bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);

6376

6244

}

6377

6245

}

6378

static void bnx2x_set_e1_mc_list(struct bnx2x *bp, u8 offset)

6246

6247

static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)

6248

{

6249

return CHIP_REV_IS_SLOW(bp) ?

6250

(BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :

6251

(BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));

6252

}

6253

6254

/* set mc list, do not wait as wait implies sleep and

6255

* set_rx_mode can be invoked from non-sleepable context.

6256

*

6257

* Instead we use the same ramrod data buffer each time we need

6258

* to configure a list of addresses, and use the fact that the

6259

* list of MACs is changed in an incremental way and that the

6260

* function is called under the netif_addr_lock. A temporary

6261

* inconsistent CAM configuration (possible in case of a very fast

6262

* sequence of add/del/add on the host side) will shortly be

6263

* restored by the handler of the last ramrod.

6264

*/

6265

static int bnx2x_set_e1_mc_list(struct bnx2x *bp)

6379

6266

{

6380

6267

int i = 0, old;

6381

6268

struct net_device *dev = bp->dev;

6269

u8 offset = bnx2x_e1_cam_mc_offset(bp);

6382

6270

struct netdev_hw_addr *ha;

6383

6271

struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);

6384

6272

dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);

6385

6273

6274

if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)

6275

return -EINVAL;

6276

6386

6277

netdev_for_each_mc_addr(ha, dev) {

6387

6278

/* copy mac */

6388

6279

config_cmd->config_table[i].msb_mac_addr =

6423

6314

}

6424

6315

}

6425

6316

6317

wmb();

6318

6426

6319

config_cmd->hdr.length = i;

6427

6320

config_cmd->hdr.offset = offset;

6428

6321

config_cmd->hdr.client_id = 0xff;

6429

config_cmd->hdr.reserved1 = 0;

6430

6431

bp->set_mac_pending = 1;

6432

smp_wmb();

6433

6434

bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,

6322

/* Mark that this ramrod doesn't use bp->set_mac_pending for

6323

* synchronization.

6324

*/

6325

config_cmd->hdr.echo = 0;

6326

6327

mb();

6328

6329

return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,

6435

6330

U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);

6436

6331

}

6437

static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)

6332

6333

void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)

6438

6334

{

6439

6335

int i;

6440

6336

struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);

6441

6337

dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);

6442

6338

int ramrod_flags = WAIT_RAMROD_COMMON;

6443

6444

bp->set_mac_pending = 1;

6445

smp_wmb();

6446

6447

for (i = 0; i < config_cmd->hdr.length; i++)

6339

u8 offset = bnx2x_e1_cam_mc_offset(bp);

6340

6341

for (i = 0; i < BNX2X_MAX_MULTICAST; i++)

6448

6342

SET_FLAG(config_cmd->config_table[i].flags,

6449

6343

MAC_CONFIGURATION_ENTRY_ACTION_TYPE,

6450

6344

T_ETH_MAC_COMMAND_INVALIDATE);

6451

6345

6346

wmb();

6347

6348

config_cmd->hdr.length = BNX2X_MAX_MULTICAST;

6349

config_cmd->hdr.offset = offset;

6350

config_cmd->hdr.client_id = 0xff;

6351

/* We'll wait for a completion this time... */

6352

config_cmd->hdr.echo = 1;

6353

6354

bp->set_mac_pending = 1;

6355

6356

mb();

6357

6452

6358

bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,

6453

6359

U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);

6454

6360

6458

6364

6459

6365

}

6460

6366

6367

/* Accept one or more multicasts */

6368

static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)

6369

{

6370

struct net_device *dev = bp->dev;

6371

struct netdev_hw_addr *ha;

6372

u32 mc_filter[MC_HASH_SIZE];

6373

u32 crc, bit, regidx;

6374

int i;

6375

6376

memset(mc_filter, 0, 4 * MC_HASH_SIZE);

6377

6378

netdev_for_each_mc_addr(ha, dev) {

6379

DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",

6380

bnx2x_mc_addr(ha));

6381

6382

crc = crc32c_le(0, bnx2x_mc_addr(ha),

6383

ETH_ALEN);

6384

bit = (crc >> 24) & 0xff;

6385

regidx = bit >> 5;

6386

bit &= 0x1f;

6387

mc_filter[regidx] |= (1 << bit);

6388

}

6389

6390

for (i = 0; i < MC_HASH_SIZE; i++)

6391

REG_WR(bp, MC_HASH_OFFSET(bp, i),

6392

mc_filter[i]);

6393

6394

return 0;

6395

}

6396

6397

void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)

6398

{

6399

int i;

6400

6401

for (i = 0; i < MC_HASH_SIZE; i++)

6402

REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);

6403

}

6404

6461

6405

#ifdef BCM_CNIC

6462

6406

/**

6463

* Set iSCSI MAC(s) at the next enties in the CAM after the ETH

6464

* MAC(s). This function will wait until the ramdord completion

6465

* returns.

6466

*

6467

* @param bp driver handle

6468

* @param set set or clear the CAM entry

6469

*

6470

* @return 0 if cussess, -ENODEV if ramrod doesn't return.

6407

* bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).

6408

*

6409

* @bp: driver handle

6410

* @set: set or clear the CAM entry

6411

*

6412

* This function will wait until the ramdord completion returns.

6413

* Return 0 if success, -ENODEV if ramrod doesn't return.

6471

6414

*/

6472

6415

static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)

6473

6416

{

6476

6419

u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +

6477

6420

BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;

6478

6421

u32 cl_bit_vec = (1 << iscsi_l2_cl_id);

6422

u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;

6479

6423

6480

6424

/* Send a SET_MAC ramrod */

6481

bnx2x_set_mac_addr_gen(bp, set, bp->iscsi_mac, cl_bit_vec,

6425

bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,

6482

6426

cam_offset, 0);

6483

6427

6484

bnx2x_set_mac_in_nig(bp, set, bp->iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);

6428

bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);

6485

6429

6486

6430

return 0;

6487

6431

}

6488

6432

6489

6433

/**

6490

* Set FCoE L2 MAC(s) at the next enties in the CAM after the

6491

* ETH MAC(s). This function will wait until the ramdord

6492

* completion returns.

6493

*

6494

* @param bp driver handle

6495

* @param set set or clear the CAM entry

6496

*

6497

* @return 0 if cussess, -ENODEV if ramrod doesn't return.

6434

* bnx2x_set_fip_eth_mac_addr - set FCoE L2 MAC(s)

6435

*

6436

* @bp: driver handle

6437

* @set: set or clear the CAM entry

6438

*

6439

* This function will wait until the ramrod completion returns.

6440

* Returns 0 if success, -ENODEV if ramrod doesn't return.

6498

6441

*/

6499

6442

int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)

6500

6443

{

6698

6641

}

6699

6642

6700

6643

/**

6701

* Configure interrupt mode according to current configuration.

6644

* bnx2x_set_int_mode - configure interrupt mode

6645

*

6646

* @bp: driver handle

6647

*

6702

6648

* In case of MSI-X it will also try to enable MSI-X.

6703

*

6704

* @param bp

6705

*

6706

* @return int

6707

6649

*/

6708

6650

static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)

6709

6651

{

7123

7065

/* Give HW time to discard old tx messages */

7124

7066

msleep(1);

7125

7067

7126

if (CHIP_IS_E1(bp)) {

7127

/* invalidate mc list,

7128

* wait and poll (interrupts are off)

7129

*/

7130

bnx2x_invlidate_e1_mc_list(bp);

7131

bnx2x_set_eth_mac(bp, 0);

7132

7133

} else {

7068

bnx2x_set_eth_mac(bp, 0);

7069

7070

bnx2x_invalidate_uc_list(bp);

7071

7072

if (CHIP_IS_E1(bp))

7073

bnx2x_invalidate_e1_mc_list(bp);

7074

else {

7075

bnx2x_invalidate_e1h_mc_list(bp);

7134

7076

REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);

7135

7136

bnx2x_set_eth_mac(bp, 0);

7137

7138

for (i = 0; i < MC_HASH_SIZE; i++)

7139

REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);

7140

7077

}

7141

7078

7142

7079

#ifdef BCM_CNIC

7292

7229

MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);

7293

7230

}

7294

7231

7295

/* Restore the value of the `magic' bit.

7232

/**

7233

* bnx2x_clp_reset_done - restore the value of the `magic' bit.

7296

7234

*

7297

* @param pdev Device handle.

7298

* @param magic_val Old value of the `magic' bit.

7235

* @bp: driver handle

7236

* @magic_val: old value of the `magic' bit.

7299

7237

*/

7300

7238

static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)

7301

7239

{

7306

7244

}

7307

7245

7308

7246

/**

7309

* Prepares for MCP reset: takes care of CLP configurations.

7310

*

7311

* @param bp

7312

* @param magic_val Old value of 'magic' bit.

7247

* bnx2x_reset_mcp_prep - prepare for MCP reset.

7248

*

7249

* @bp: driver handle

7250

* @magic_val: old value of 'magic' bit.

7251

*

7252

* Takes care of CLP configurations.

7313

7253

*/

7314

7254

static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)

7315

7255

{

7334

7274

#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */

7335

7275

#define MCP_ONE_TIMEOUT 100 /* 100 ms */

7336

7276

7337

/* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,

7338

* depending on the HW type.

7277

/**

7278

* bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT

7339

7279

*

7340

* @param bp

7280

* @bp: driver handle

7341

7281

*/

7342

7282

static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)

7343

7283

{

7349

7289

msleep(MCP_ONE_TIMEOUT);

7350

7290

}

7351

7291

7292

/*

7293

* initializes bp->common.shmem_base and waits for validity signature to appear

7294

*/

7295

static int bnx2x_init_shmem(struct bnx2x *bp)

7296

{

7297

int cnt = 0;

7298

u32 val = 0;

7299

7300

do {

7301

bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);

7302

if (bp->common.shmem_base) {

7303

val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);

7304

if (val & SHR_MEM_VALIDITY_MB)

7305

return 0;

7306

}

7307

7308

bnx2x_mcp_wait_one(bp);

7309

7310

} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));

7311

7312

BNX2X_ERR("BAD MCP validity signature\n");

7313

7314

return -ENODEV;

7315

}

7316

7352

7317

static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)

7353

7318

{

7354

u32 shmem, cnt, validity_offset, val;

7355

int rc = 0;

7356

7357

msleep(100);

7358

7359

/* Get shmem offset */

7360

shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);

7361

if (shmem == 0) {

7362

BNX2X_ERR("Shmem 0 return failure\n");

7363

rc = -ENOTTY;

7364

goto exit_lbl;

7365

}

7366

7367

validity_offset = offsetof(struct shmem_region, validity_map[0]);

7368

7369

/* Wait for MCP to come up */

7370

for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {

7371

/* TBD: its best to check validity map of last port.

7372

* currently checks on port 0.

7373

*/

7374

val = REG_RD(bp, shmem + validity_offset);

7375

DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,

7376

shmem + validity_offset, val);

7377

7378

/* check that shared memory is valid. */

7379

if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))

7380

== (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))

7381

break;

7382

7383

bnx2x_mcp_wait_one(bp);

7384

}

7385

7386

DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);

7387

7388

/* Check that shared memory is valid. This indicates that MCP is up. */

7389

if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=

7390

(SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {

7391

BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");

7392

rc = -ENOTTY;

7393

goto exit_lbl;

7394

}

7395

7396

exit_lbl:

7319

int rc = bnx2x_init_shmem(bp);

7320

7397

7321

/* Restore the `magic' bit value */

7398

7322

if (!CHIP_IS_E1(bp))

7399

7323

bnx2x_clp_reset_done(bp, magic_val);

7906

7830

BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",

7907

7831

bp->common.flash_size, bp->common.flash_size);

7908

7832

7909

bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);

7833

bnx2x_init_shmem(bp);

7834

7910

7835

bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?

7911

7836

MISC_REG_GENERIC_CR_1 :

7912

7837

MISC_REG_GENERIC_CR_0));

7838

7913

7839

bp->link_params.shmem_base = bp->common.shmem_base;

7914

7840

bp->link_params.shmem2_base = bp->common.shmem2_base;

7915

7841

BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",

7921

7847

return;

7922

7848

}

7923

7849

7924

val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);

7925

if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))

7926

!= (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))

7927

BNX2X_ERR("BAD MCP validity signature\n");

7928

7929

7850

bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);

7930

7851

BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);

7931

7852

7959

7880

(val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?

7960

7881

FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;

7961

7882

7962

if (BP_E1HVN(bp) == 0) {

7963

pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);

7964

bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;

7965

} else {

7966

/* no WOL capability for E1HVN != 0 */

7967

bp->flags |= NO_WOL_FLAG;

7968

}

7883

pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);

7884

bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;

7885

7969

7886

BNX2X_DEV_INFO("%sWoL capable\n",

7970

7887

(bp->flags & NO_WOL_FLAG) ? "not " : "");

7971

7888

8405

8322

bp->common.shmem2_base);

8406

8323

}

8407

8324

8325

#ifdef BCM_CNIC

8326

static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)

8327

{

8328

u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,

8329

drv_lic_key[BP_PORT(bp)].max_iscsi_conn);

8330

u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,

8331

drv_lic_key[BP_PORT(bp)].max_fcoe_conn);

8332

8333

/* Get the number of maximum allowed iSCSI and FCoE connections */

8334

bp->cnic_eth_dev.max_iscsi_conn =

8335

(max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>

8336

BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;

8337

8338

bp->cnic_eth_dev.max_fcoe_conn =

8339

(max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>

8340

BNX2X_MAX_FCOE_INIT_CONN_SHIFT;

8341

8342

BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",

8343

bp->cnic_eth_dev.max_iscsi_conn,

8344

bp->cnic_eth_dev.max_fcoe_conn);

8345

8346

/* If mamimum allowed number of connections is zero -

8347

* disable the feature.

8348

*/

8349

if (!bp->cnic_eth_dev.max_iscsi_conn)

8350

bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;

8351

8352

if (!bp->cnic_eth_dev.max_fcoe_conn)

8353

bp->flags |= NO_FCOE_FLAG;

8354

}

8355

#endif

8356

8408

8357

static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)

8409

8358

{

8410

8359

u32 val, val2;

8411

8360

int func = BP_ABS_FUNC(bp);

8412

8361

int port = BP_PORT(bp);

8362

#ifdef BCM_CNIC

8363

u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;

8364

u8 *fip_mac = bp->fip_mac;

8365

#endif

8413

8366

8414

8367

if (BP_NOMCP(bp)) {

8415

8368

BNX2X_ERROR("warning: random MAC workaround active\n");

8422

8375

bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);

8423

8376

8424

8377

#ifdef BCM_CNIC

8425

/* iSCSI NPAR MAC */

8378

/* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or

8379

* FCoE MAC then the appropriate feature should be disabled.

8380

*/

8426

8381

if (IS_MF_SI(bp)) {

8427

8382

u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);

8428

8383

if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {

8430

8385

iscsi_mac_addr_upper);

8431

8386

val = MF_CFG_RD(bp, func_ext_config[func].

8432

8387

iscsi_mac_addr_lower);

8433

bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);

8434

}

8388

BNX2X_DEV_INFO("Read iSCSI MAC: "

8389

"0x%x:0x%04x\n", val2, val);

8390

bnx2x_set_mac_buf(iscsi_mac, val, val2);

8391

} else

8392

bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;

8393

8394

if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {

8395

val2 = MF_CFG_RD(bp, func_ext_config[func].

8396

fcoe_mac_addr_upper);

8397

val = MF_CFG_RD(bp, func_ext_config[func].

8398

fcoe_mac_addr_lower);

8399

BNX2X_DEV_INFO("Read FCoE MAC to "

8400

"0x%x:0x%04x\n", val2, val);

8401

bnx2x_set_mac_buf(fip_mac, val, val2);

8402

8403

} else

8404

bp->flags |= NO_FCOE_FLAG;

8435

8405

}

8436

8406

#endif

8437

8407

} else {

8445

8415

iscsi_mac_upper);

8446

8416

val = SHMEM_RD(bp, dev_info.port_hw_config[port].

8447

8417

iscsi_mac_lower);

8448

bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);

8418

bnx2x_set_mac_buf(iscsi_mac, val, val2);

8449

8419

#endif

8450

8420

}

8451

8421

8453

8423

memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);

8454

8424

8455

8425

#ifdef BCM_CNIC

8456

/* Inform the upper layers about FCoE MAC */

8426

/* Set the FCoE MAC in modes other then MF_SI */

8457

8427

if (!CHIP_IS_E1x(bp)) {

8458

8428

if (IS_MF_SD(bp))

8459

memcpy(bp->fip_mac, bp->dev->dev_addr,

8460

sizeof(bp->fip_mac));

8461

else

8462

memcpy(bp->fip_mac, bp->iscsi_mac,

8463

sizeof(bp->fip_mac));

8429

memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);

8430

else if (!IS_MF(bp))

8431

memcpy(fip_mac, iscsi_mac, ETH_ALEN);

8432

}

8433

8434

/* Disable iSCSI if MAC configuration is

8435

* invalid.

8436

*/

8437

if (!is_valid_ether_addr(iscsi_mac)) {

8438

bp->flags |= NO_ISCSI_FLAG;

8439

memset(iscsi_mac, 0, ETH_ALEN);

8440

}

8441

8442

/* Disable FCoE if MAC configuration is

8443

* invalid.

8444

*/

8445

if (!is_valid_ether_addr(fip_mac)) {

8446

bp->flags |= NO_FCOE_FLAG;

8447

memset(bp->fip_mac, 0, ETH_ALEN);

8464

8448

}

8465

8449

#endif

8466

8450

}

8468

8452

static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)

8469

8453

{

8470

8454

int /*abs*/func = BP_ABS_FUNC(bp);

8471

int vn, port;

8455

int vn;

8472

8456

u32 val = 0;

8473

8457

int rc = 0;

8474

8458

8503

8487

bp->mf_ov = 0;

8504

8488

bp->mf_mode = 0;

8505

8489

vn = BP_E1HVN(bp);

8506

port = BP_PORT(bp);

8507

8490

8508

8491

if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {

8509

8492

DP(NETIF_MSG_PROBE,

8518

8501

E1H_FUNC_MAX * sizeof(struct drv_func_mb);

8519

8502

/*

8520

8503

* get mf configuration:

8521

* 1. existance of MF configuration

8504

* 1. existence of MF configuration

8522

8505

* 2. MAC address must be legal (check only upper bytes)

8523

8506

* for Switch-Independent mode;

8524

8507

* OVLAN must be legal for Switch-Dependent mode

8560

8543

default:

8561

8544

/* Unknown configuration: reset mf_config */

8562

8545

bp->mf_config[vn] = 0;

8563

DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",

8546

DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",

8564

8547

val);

8565

8548

}

8566

8549

}

8623

8606

/* Get MAC addresses */

8624

8607

bnx2x_get_mac_hwinfo(bp);

8625

8608

8609

#ifdef BCM_CNIC

8610

bnx2x_get_cnic_info(bp);

8611

#endif

8612

8626

8613

return rc;

8627

8614

}

8628

8615

8733

8720

bp->multi_mode = multi_mode;

8734

8721

bp->int_mode = int_mode;

8735

8722

8736

bp->dev->features |= NETIF_F_GRO;

8737

8738

8723

/* Set TPA flags */

8739

8724

if (disable_tpa) {

8740

8725

bp->flags &= ~TPA_ENABLE_FLAG;

8754

8739

8755

8740

bp->tx_ring_size = MAX_TX_AVAIL;

8756

8741

8757

bp->rx_csum = 1;

8758

8759

8742

/* make sure that the numbers are in the right granularity */

8760

8743

bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;

8761

8744

bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;

8837

8820

return 0;

8838

8821

}

8839

8822

8823

#define E1_MAX_UC_LIST 29

8824

#define E1H_MAX_UC_LIST 30

8825

#define E2_MAX_UC_LIST 14

8826

static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)

8827

{

8828

if (CHIP_IS_E1(bp))

8829

return E1_MAX_UC_LIST;

8830

else if (CHIP_IS_E1H(bp))

8831

return E1H_MAX_UC_LIST;

8832

else

8833

return E2_MAX_UC_LIST;

8834

}

8835

8836

8837

static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)

8838

{

8839

if (CHIP_IS_E1(bp))

8840

/* CAM Entries for Port0:

8841

* 0 - prim ETH MAC

8842

* 1 - BCAST MAC

8843

* 2 - iSCSI L2 ring ETH MAC

8844

* 3-31 - UC MACs

8845

*

8846

* Port1 entries are allocated the same way starting from

8847

* entry 32.

8848

*/

8849

return 3 + 32 * BP_PORT(bp);

8850

else if (CHIP_IS_E1H(bp)) {

8851

/* CAM Entries:

8852

* 0-7 - prim ETH MAC for each function

8853

* 8-15 - iSCSI L2 ring ETH MAC for each function

8854

* 16 till 255 UC MAC lists for each function

8855

*

8856

* Remark: There is no FCoE support for E1H, thus FCoE related

8857

* MACs are not considered.

8858

*/

8859

return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +

8860

bnx2x_max_uc_list(bp) * BP_FUNC(bp);

8861

} else {

8862

/* CAM Entries (there is a separate CAM per engine):

8863

* 0-4 - prim ETH MAC for each function

8864

* 4-7 - iSCSI L2 ring ETH MAC for each function

8865

* 8-11 - FIP ucast L2 MAC for each function

8866

* 12-15 - ALL_ENODE_MACS mcast MAC for each function

8867

* 16 till 71 UC MAC lists for each function

8868

*/

8869

u8 func_idx =

8870

(CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));

8871

8872

return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +

8873

bnx2x_max_uc_list(bp) * func_idx;

8874

}

8875

}

8876

8877

/* set uc list, do not wait as wait implies sleep and

8878

* set_rx_mode can be invoked from non-sleepable context.

8879

*

8880

* Instead we use the same ramrod data buffer each time we need

8881

* to configure a list of addresses, and use the fact that the

8882

* list of MACs is changed in an incremental way and that the

8883

* function is called under the netif_addr_lock. A temporary

8884

* inconsistent CAM configuration (possible in case of very fast

8885

* sequence of add/del/add on the host side) will shortly be

8886

* restored by the handler of the last ramrod.

8887

*/

8888

static int bnx2x_set_uc_list(struct bnx2x *bp)

8889

{

8890

int i = 0, old;

8891

struct net_device *dev = bp->dev;

8892

u8 offset = bnx2x_uc_list_cam_offset(bp);

8893

struct netdev_hw_addr *ha;

8894

struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);

8895

dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);

8896

8897

if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))

8898

return -EINVAL;

8899

8900

netdev_for_each_uc_addr(ha, dev) {

8901

/* copy mac */

8902

config_cmd->config_table[i].msb_mac_addr =

8903

swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);

8904

config_cmd->config_table[i].middle_mac_addr =

8905

swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);

8906

config_cmd->config_table[i].lsb_mac_addr =

8907

swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);

8908

8909

config_cmd->config_table[i].vlan_id = 0;

8910

config_cmd->config_table[i].pf_id = BP_FUNC(bp);

8911

config_cmd->config_table[i].clients_bit_vector =

8912

cpu_to_le32(1 << BP_L_ID(bp));

8913

8914

SET_FLAG(config_cmd->config_table[i].flags,

8915

MAC_CONFIGURATION_ENTRY_ACTION_TYPE,

8916

T_ETH_MAC_COMMAND_SET);

8917

8918

DP(NETIF_MSG_IFUP,

8919

"setting UCAST[%d] (%04x:%04x:%04x)\n", i,

8920

config_cmd->config_table[i].msb_mac_addr,

8921

config_cmd->config_table[i].middle_mac_addr,

8922

config_cmd->config_table[i].lsb_mac_addr);

8923

8924

i++;

8925

8926

/* Set uc MAC in NIG */

8927

bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),

8928

LLH_CAM_ETH_LINE + i);

8929

}

8930

old = config_cmd->hdr.length;

8931

if (old > i) {

8932

for (; i < old; i++) {

8933

if (CAM_IS_INVALID(config_cmd->

8934

config_table[i])) {

8935

/* already invalidated */

8936

break;

8937

}

8938

/* invalidate */

8939

SET_FLAG(config_cmd->config_table[i].flags,

8940

MAC_CONFIGURATION_ENTRY_ACTION_TYPE,

8941

T_ETH_MAC_COMMAND_INVALIDATE);

8942

}

8943

}

8944

8945

wmb();

8946

8947

config_cmd->hdr.length = i;

8948

config_cmd->hdr.offset = offset;

8949

config_cmd->hdr.client_id = 0xff;

8950

/* Mark that this ramrod doesn't use bp->set_mac_pending for

8951

* synchronization.

8952

*/

8953

config_cmd->hdr.echo = 0;

8954

8955

mb();

8956

8957

return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,

8958

U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);

8959

8960

}

8961

8962

void bnx2x_invalidate_uc_list(struct bnx2x *bp)

8963

{

8964

int i;

8965

struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);

8966

dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);

8967

int ramrod_flags = WAIT_RAMROD_COMMON;

8968

u8 offset = bnx2x_uc_list_cam_offset(bp);

8969

u8 max_list_size = bnx2x_max_uc_list(bp);

8970

8971

for (i = 0; i < max_list_size; i++) {

8972

SET_FLAG(config_cmd->config_table[i].flags,

8973

MAC_CONFIGURATION_ENTRY_ACTION_TYPE,

8974

T_ETH_MAC_COMMAND_INVALIDATE);

8975

bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);

8976

}

8977

8978

wmb();

8979

8980

config_cmd->hdr.length = max_list_size;

8981

config_cmd->hdr.offset = offset;

8982

config_cmd->hdr.client_id = 0xff;

8983

/* We'll wait for a completion this time... */

8984

config_cmd->hdr.echo = 1;

8985

8986

bp->set_mac_pending = 1;

8987

8988

mb();

8989

8990

bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,

8991

U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);

8992

8993

/* Wait for a completion */

8994

bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,

8995

ramrod_flags);

8996

8997

}

8998

8999

static inline int bnx2x_set_mc_list(struct bnx2x *bp)

9000

{

9001

/* some multicasts */

9002

if (CHIP_IS_E1(bp)) {

9003

return bnx2x_set_e1_mc_list(bp);

9004

} else { /* E1H and newer */

9005

return bnx2x_set_e1h_mc_list(bp);

9006

}

9007

}

9008

8840

9009

/* called with netif_tx_lock from dev_mcast.c */

8841

9010

void bnx2x_set_rx_mode(struct net_device *dev)

8842

9011

{

8843

9012

struct bnx2x *bp = netdev_priv(dev);

8844

9013

u32 rx_mode = BNX2X_RX_MODE_NORMAL;

8845

int port = BP_PORT(bp);

8846

9014

8847

9015

if (bp->state != BNX2X_STATE_OPEN) {

8848

9016

DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);

8853

9021

8854

9022

if (dev->flags & IFF_PROMISC)

8855

9023

rx_mode = BNX2X_RX_MODE_PROMISC;

8856

else if ((dev->flags & IFF_ALLMULTI) ||

8857

((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&

8858

CHIP_IS_E1(bp)))

9024

else if (dev->flags & IFF_ALLMULTI)

8859

9025

rx_mode = BNX2X_RX_MODE_ALLMULTI;

8860

else { /* some multicasts */

8861

if (CHIP_IS_E1(bp)) {

8862

/*

8863

* set mc list, do not wait as wait implies sleep

8864

* and set_rx_mode can be invoked from non-sleepable

8865

* context

8866

*/

8867

u8 offset = (CHIP_REV_IS_SLOW(bp) ?

8868

BNX2X_MAX_EMUL_MULTI*(1 + port) :

8869

BNX2X_MAX_MULTICAST*(1 + port));

8870

8871

bnx2x_set_e1_mc_list(bp, offset);

8872

} else { /* E1H */

8873

/* Accept one or more multicasts */

8874

struct netdev_hw_addr *ha;

8875

u32 mc_filter[MC_HASH_SIZE];

8876

u32 crc, bit, regidx;

8877

int i;

8878

8879

memset(mc_filter, 0, 4 * MC_HASH_SIZE);

8880

8881

netdev_for_each_mc_addr(ha, dev) {

8882

DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",

8883

bnx2x_mc_addr(ha));

8884

8885

crc = crc32c_le(0, bnx2x_mc_addr(ha),

8886

ETH_ALEN);

8887

bit = (crc >> 24) & 0xff;

8888

regidx = bit >> 5;

8889

bit &= 0x1f;

8890

mc_filter[regidx] |= (1 << bit);

8891

}

8892

8893

for (i = 0; i < MC_HASH_SIZE; i++)

8894

REG_WR(bp, MC_HASH_OFFSET(bp, i),

8895

mc_filter[i]);

8896

}

9026

else {

9027

/* some multicasts */

9028

if (bnx2x_set_mc_list(bp))

9029

rx_mode = BNX2X_RX_MODE_ALLMULTI;

9030

9031

/* some unicasts */

9032

if (bnx2x_set_uc_list(bp))

9033

rx_mode = BNX2X_RX_MODE_PROMISC;

8897

9034

}

8898

9035

8899

9036

bp->rx_mode = rx_mode;

8974

9111

.ndo_stop = bnx2x_close,

8975

9112

.ndo_start_xmit = bnx2x_start_xmit,

8976

9113

.ndo_select_queue = bnx2x_select_queue,

8977

.ndo_set_multicast_list = bnx2x_set_rx_mode,

9114

.ndo_set_rx_mode = bnx2x_set_rx_mode,

8978

9115

.ndo_set_mac_address = bnx2x_change_mac_addr,

8979

9116

.ndo_validate_addr = eth_validate_addr,

8980

9117

.ndo_do_ioctl = bnx2x_ioctl,

8981

9118

.ndo_change_mtu = bnx2x_change_mtu,

9119

.ndo_fix_features = bnx2x_fix_features,

9120

.ndo_set_features = bnx2x_set_features,

8982

9121

.ndo_tx_timeout = bnx2x_tx_timeout,

8983

9122

#ifdef CONFIG_NET_POLL_CONTROLLER

8984

9123

.ndo_poll_controller = poll_bnx2x,

9105

9244

9106

9245

dev->netdev_ops = &bnx2x_netdev_ops;

9107

9246

bnx2x_set_ethtool_ops(dev);

9108

dev->features |= NETIF_F_SG;

9109

dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;

9247

9248

dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |

9249

NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |

9250

NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;

9251

9252

dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |

9253

NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;

9254

9255

dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;

9110

9256

if (bp->flags & USING_DAC_FLAG)

9111

9257

dev->features |= NETIF_F_HIGHDMA;

9112

dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);

9113

dev->features |= NETIF_F_TSO6;

9114

dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);

9115

9116

dev->vlan_features |= NETIF_F_SG;

9117

dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;

9118

if (bp->flags & USING_DAC_FLAG)

9119

dev->vlan_features |= NETIF_F_HIGHDMA;

9120

dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);

9121

dev->vlan_features |= NETIF_F_TSO6;

9122

9123

#ifdef BCM_DCB

9258

9259

/* Add Loopback capability to the device */

9260

dev->hw_features |= NETIF_F_LOOPBACK;

9261

9262

#ifdef BCM_DCBNL

9124

9263

dev->dcbnl_ops = &bnx2x_dcbnl_ops;

9125

9264

#endif

9126

9265

9452

9591

9453

9592

#endif

9454

9593

9455

/* Configure interupt mode: try to enable MSI-X/MSI if

9594

/* Configure interrupt mode: try to enable MSI-X/MSI if

9456

9595

* needed, set bp->num_queues appropriately.

9457

9596

*/

9458

9597

bnx2x_set_int_mode(bp);

9527

9666

}

9528

9667

#endif

9529

9668

9669

#ifdef BCM_DCBNL

9670

/* Delete app tlvs from dcbnl */

9671

bnx2x_dcbnl_update_applist(bp, true);

9672

#endif

9673

9530

9674

unregister_netdev(dev);

9531

9675

9532

9676

/* Delete all NAPI objects */

9800

9944

HW_CID(bp, BNX2X_ISCSI_ETH_CID));

9801

9945

}

9802

9946

9803

/* There may be not more than 8 L2 and COMMON SPEs and not more

9804

* than 8 L5 SPEs in the air.

9947

/* There may be not more than 8 L2 and not more than 8 L5 SPEs

9948

* We also check that the number of outstanding

9949

* COMMON ramrods is not more than the EQ and SPQ can

9950

* accommodate.

9805

9951

*/

9806

if ((type == NONE_CONNECTION_TYPE) ||

9807

(type == ETH_CONNECTION_TYPE)) {

9808

if (!atomic_read(&bp->spq_left))

9809

break;

9810

else

9811

atomic_dec(&bp->spq_left);

9952

if (type == ETH_CONNECTION_TYPE) {

9953

if (!atomic_read(&bp->cq_spq_left))

9954

break;

9955

else

9956

atomic_dec(&bp->cq_spq_left);

9957

} else if (type == NONE_CONNECTION_TYPE) {

9958

if (!atomic_read(&bp->eq_spq_left))

9959

break;

9960

else

9961

atomic_dec(&bp->eq_spq_left);

9812

9962

} else if ((type == ISCSI_CONNECTION_TYPE) ||

9813

9963

(type == FCOE_CONNECTION_TYPE)) {

9814

9964

if (bp->cnic_spq_pending >=

9886

10036

int rc = 0;

9887

10037

9888

10038

mutex_lock(&bp->cnic_mutex);

9889

c_ops = bp->cnic_ops;

10039

c_ops = rcu_dereference_protected(bp->cnic_ops,

10040

lockdep_is_held(&bp->cnic_mutex));

9890

10041

if (c_ops)

9891

10042

rc = c_ops->cnic_ctl(bp->cnic_data, ctl);

9892

10043

mutex_unlock(&bp->cnic_mutex);

10000

10151

int count = ctl->data.credit.credit_count;

10001

10152

10002

10153

smp_mb__before_atomic_inc();

10003

atomic_add(count, &bp->spq_left);

10154

atomic_add(count, &bp->cq_spq_left);

10004

10155

smp_mb__after_atomic_inc();

10005

10156

break;

10006

10157

}

10007

10158

10159

case DRV_CTL_ISCSI_STOPPED_CMD: {

10160

bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_ISCSI_STOPPED);

10161

break;

10162

}

10163

10008

10164

default:

10009

10165

BNX2X_ERR("unknown command %x\n", ctl->cmd);

10010

10166

rc = -EINVAL;

10096

10252

struct bnx2x *bp = netdev_priv(dev);

10097

10253

struct cnic_eth_dev *cp = &bp->cnic_eth_dev;

10098

10254

10255

/* If both iSCSI and FCoE are disabled - return NULL in

10256

* order to indicate CNIC that it should not try to work

10257

* with this device.

10258

*/

10259

if (NO_ISCSI(bp) && NO_FCOE(bp))

10260

return NULL;

10261

10099

10262

cp->drv_owner = THIS_MODULE;

10100

10263

cp->chip_id = CHIP_ID(bp);

10101

10264

cp->pdev = bp->pdev;

10116

10279

BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;

10117

10280

cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;

10118

10281

10282

if (NO_ISCSI_OOO(bp))

10283

cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;

10284

10285

if (NO_ISCSI(bp))

10286

cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;

10287

10288

if (NO_FCOE(bp))

10289

cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;

10290

10119

10291

DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "

10120

10292

"starting cid %d\n",

10121

10293

cp->ctx_blk_size,