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  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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sound/pci/rme9652/hdspm.c
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 *      Modified 2006-06-01 for AES32 support by Remy Bruno
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 *                                               <remy.bruno@trinnov.com>
10
10
 *
 
11
 *      Modified 2009-04-13 for proper metering by Florian Faber
 
12
 *                                               <faber@faberman.de>
 
13
 *
 
14
 *      Modified 2009-04-14 for native float support by Florian Faber
 
15
 *                                               <faber@faberman.de>
 
16
 *
 
17
 *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
 
18
 *                                               <faber@faberman.de>
 
19
 *
 
20
 *      Modified 2009-04-30 added hw serial number support by Florian Faber
 
21
 *
 
22
 *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
 
23
 *
 
24
 *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
 
25
 *
11
26
 *   This program is free software; you can redistribute it and/or modify
12
27
 *   it under the terms of the GNU General Public License as published by
13
28
 *   the Free Software Foundation; either version 2 of the License, or
35
50
#include <sound/core.h>
36
51
#include <sound/control.h>
37
52
#include <sound/pcm.h>
 
53
#include <sound/pcm_params.h>
38
54
#include <sound/info.h>
39
55
#include <sound/asoundef.h>
40
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#include <sound/rawmidi.h>
47
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static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
48
64
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
49
65
 
50
 
/* Disable precise pointer at start */
51
 
static int precise_ptr[SNDRV_CARDS];
52
 
 
53
 
/* Send all playback to line outs */
54
 
static int line_outs_monitor[SNDRV_CARDS];
55
 
 
56
 
/* Enable Analog Outs on Channel 63/64 by default */
57
 
static int enable_monitor[SNDRV_CARDS];
58
 
 
59
66
module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
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65
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module_param_array(enable, bool, NULL, 0444);
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MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
67
74
 
68
 
module_param_array(precise_ptr, bool, NULL, 0444);
69
 
MODULE_PARM_DESC(precise_ptr, "Enable or disable precise pointer.");
70
 
 
71
 
module_param_array(line_outs_monitor, bool, NULL, 0444);
72
 
MODULE_PARM_DESC(line_outs_monitor,
73
 
                 "Send playback streams to analog outs by default.");
74
 
 
75
 
module_param_array(enable_monitor, bool, NULL, 0444);
76
 
MODULE_PARM_DESC(enable_monitor,
77
 
                 "Enable Analog Out on Channel 63/64 by default.");
78
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79
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MODULE_AUTHOR
80
 
      ("Winfried Ritsch <ritsch_AT_iem.at>, "
81
 
       "Paul Davis <paul@linuxaudiosystems.com>, "
82
 
       "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
83
 
       "Remy Bruno <remy.bruno@trinnov.com>");
 
77
(
 
78
        "Winfried Ritsch <ritsch_AT_iem.at>, "
 
79
        "Paul Davis <paul@linuxaudiosystems.com>, "
 
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        "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
 
81
        "Remy Bruno <remy.bruno@trinnov.com>, "
 
82
        "Florian Faber <faberman@linuxproaudio.org>, "
 
83
        "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
 
84
);
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MODULE_DESCRIPTION("RME HDSPM");
85
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MODULE_LICENSE("GPL");
86
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MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
87
88
 
88
 
/* --- Write registers. --- 
 
89
/* --- Write registers. ---
89
90
  These are defined as byte-offsets from the iobase value.  */
90
91
 
 
92
#define HDSPM_WR_SETTINGS             0
 
93
#define HDSPM_outputBufferAddress    32
 
94
#define HDSPM_inputBufferAddress     36
91
95
#define HDSPM_controlRegister        64
92
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#define HDSPM_interruptConfirmation  96
93
97
#define HDSPM_control2Reg            256  /* not in specs ???????? */
94
98
#define HDSPM_freqReg                256  /* for AES32 */
95
 
#define HDSPM_midiDataOut0           352  /* just believe in old code */
96
 
#define HDSPM_midiDataOut1           356
 
99
#define HDSPM_midiDataOut0           352  /* just believe in old code */
 
100
#define HDSPM_midiDataOut1           356
97
101
#define HDSPM_eeprom_wr              384  /* for AES32 */
98
102
 
99
103
/* DMA enable for 64 channels, only Bit 0 is relevant */
100
 
#define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */ 
 
104
#define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
101
105
#define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
102
106
 
103
 
/* 16 page addresses for each of the 64 channels DMA buffer in and out 
 
107
/* 16 page addresses for each of the 64 channels DMA buffer in and out
104
108
   (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
105
109
#define HDSPM_pageAddressBufferOut       8192
106
110
#define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
119
123
#define HDSPM_statusRegister2  192
120
124
#define HDSPM_timecodeRegister 128
121
125
 
 
126
/* AIO, RayDAT */
 
127
#define HDSPM_RD_STATUS_0 0
 
128
#define HDSPM_RD_STATUS_1 64
 
129
#define HDSPM_RD_STATUS_2 128
 
130
#define HDSPM_RD_STATUS_3 192
 
131
 
 
132
#define HDSPM_RD_TCO           256
 
133
#define HDSPM_RD_PLL_FREQ      512
 
134
#define HDSPM_WR_TCO           128
 
135
 
 
136
#define HDSPM_TCO1_TCO_lock                     0x00000001
 
137
#define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 
138
#define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 
139
#define HDSPM_TCO1_LTC_Input_valid              0x00000008
 
140
#define HDSPM_TCO1_WCK_Input_valid              0x00000010
 
141
#define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 
142
#define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 
143
 
 
144
#define HDSPM_TCO1_set_TC                       0x00000100
 
145
#define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 
146
#define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 
147
#define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 
148
 
 
149
#define HDSPM_TCO2_TC_run                       0x00010000
 
150
#define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 
151
#define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 
152
#define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 
153
#define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 
154
#define HDSPM_TCO2_set_jam_sync                 0x00200000
 
155
#define HDSPM_TCO2_set_flywheel                 0x00400000
 
156
 
 
157
#define HDSPM_TCO2_set_01_4                     0x01000000
 
158
#define HDSPM_TCO2_set_pull_down                0x02000000
 
159
#define HDSPM_TCO2_set_pull_up                  0x04000000
 
160
#define HDSPM_TCO2_set_freq                     0x08000000
 
161
#define HDSPM_TCO2_set_term_75R                 0x10000000
 
162
#define HDSPM_TCO2_set_input_LSB                0x20000000
 
163
#define HDSPM_TCO2_set_input_MSB                0x40000000
 
164
#define HDSPM_TCO2_set_freq_from_app            0x80000000
 
165
 
 
166
 
 
167
#define HDSPM_midiDataOut0    352
 
168
#define HDSPM_midiDataOut1    356
 
169
#define HDSPM_midiDataOut2    368
 
170
 
122
171
#define HDSPM_midiDataIn0     360
123
172
#define HDSPM_midiDataIn1     364
 
173
#define HDSPM_midiDataIn2     372
 
174
#define HDSPM_midiDataIn3     376
124
175
 
125
176
/* status is data bytes in MIDI-FIFO (0-128) */
126
 
#define HDSPM_midiStatusOut0  384       
127
 
#define HDSPM_midiStatusOut1  388       
128
 
#define HDSPM_midiStatusIn0   392       
129
 
#define HDSPM_midiStatusIn1   396       
 
177
#define HDSPM_midiStatusOut0  384
 
178
#define HDSPM_midiStatusOut1  388
 
179
#define HDSPM_midiStatusOut2  400
 
180
 
 
181
#define HDSPM_midiStatusIn0   392
 
182
#define HDSPM_midiStatusIn1   396
 
183
#define HDSPM_midiStatusIn2   404
 
184
#define HDSPM_midiStatusIn3   408
130
185
 
131
186
 
132
187
/* the meters are regular i/o-mapped registers, but offset
133
188
   considerably from the rest. the peak registers are reset
134
 
   when read; the least-significant 4 bits are full-scale counters; 
 
189
   when read; the least-significant 4 bits are full-scale counters;
135
190
   the actual peak value is in the most-significant 24 bits.
136
191
*/
137
 
#define HDSPM_MADI_peakrmsbase  4096    /* 4096-8191 2x64x32Bit Meters */
 
192
 
 
193
#define HDSPM_MADI_INPUT_PEAK           4096
 
194
#define HDSPM_MADI_PLAYBACK_PEAK        4352
 
195
#define HDSPM_MADI_OUTPUT_PEAK          4608
 
196
 
 
197
#define HDSPM_MADI_INPUT_RMS_L          6144
 
198
#define HDSPM_MADI_PLAYBACK_RMS_L       6400
 
199
#define HDSPM_MADI_OUTPUT_RMS_L         6656
 
200
 
 
201
#define HDSPM_MADI_INPUT_RMS_H          7168
 
202
#define HDSPM_MADI_PLAYBACK_RMS_H       7424
 
203
#define HDSPM_MADI_OUTPUT_RMS_H         7680
138
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139
205
/* --- Control Register bits --------- */
140
206
#define HDSPM_Start                (1<<0) /* start engine */
143
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#define HDSPM_Latency1             (1<<2) /* where n is defined */
144
210
#define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
145
211
 
146
 
#define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Slave/Autosync */
 
212
#define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 
213
#define HDSPM_c0Master          0x1    /* Master clock bit in settings
 
214
                                          register [RayDAT, AIO] */
147
215
 
148
216
#define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
149
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157
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                                     56channelMODE=0 */ /* MADI ONLY*/
158
226
#define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
159
227
 
160
 
#define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode, 
 
228
#define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
161
229
                                     0=off, 1=on  */ /* MADI ONLY */
162
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#define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
163
231
 
166
234
                                    */
167
235
#define HDSPM_InputSelect1 (1<<15) /* should be 0 */
168
236
 
169
 
#define HDSPM_SyncRef0     (1<<16) /* 0=WOrd, 1=MADI */
170
 
#define HDSPM_SyncRef1     (1<<17) /* for AES32: SyncRefN codes the AES # */
171
237
#define HDSPM_SyncRef2     (1<<13)
172
238
#define HDSPM_SyncRef3     (1<<25)
173
239
 
174
240
#define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
175
 
#define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use 
 
241
#define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
176
242
                                      AES additional bits in
177
243
                                      lower 5 Audiodatabits ??? */
178
244
#define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
179
245
#define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
180
246
 
181
 
#define HDSPM_Midi0InterruptEnable (1<<22)
182
 
#define HDSPM_Midi1InterruptEnable (1<<23)
 
247
#define HDSPM_Midi0InterruptEnable 0x0400000
 
248
#define HDSPM_Midi1InterruptEnable 0x0800000
 
249
#define HDSPM_Midi2InterruptEnable 0x0200000
 
250
#define HDSPM_Midi3InterruptEnable 0x4000000
183
251
 
184
252
#define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 
253
#define HDSPe_FLOAT_FORMAT         0x2000000
185
254
 
186
255
#define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
187
256
#define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
198
267
#define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
199
268
#define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
200
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                              HDSPM_SyncRef2|HDSPM_SyncRef3)
201
 
#define HDSPM_SyncRef_Word   0
202
 
#define HDSPM_SyncRef_MADI   (HDSPM_SyncRef0)
203
 
 
204
 
#define HDSPM_SYNC_FROM_WORD 0  /* Preferred sync reference */
205
 
#define HDSPM_SYNC_FROM_MADI 1  /* choices - used by "pref_sync_ref" */
 
270
 
 
271
#define HDSPM_c0_SyncRef0      0x2
 
272
#define HDSPM_c0_SyncRef1      0x4
 
273
#define HDSPM_c0_SyncRef2      0x8
 
274
#define HDSPM_c0_SyncRef3      0x10
 
275
#define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 
276
                                HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 
277
 
 
278
#define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 
279
#define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 
280
#define HDSPM_SYNC_FROM_TCO     2
 
281
#define HDSPM_SYNC_FROM_SYNC_IN 3
206
282
 
207
283
#define HDSPM_Frequency32KHz    HDSPM_Frequency0
208
284
#define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
216
292
#define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
217
293
                                 HDSPM_Frequency0)
218
294
 
219
 
/* --- for internal discrimination */
220
 
#define HDSPM_CLOCK_SOURCE_AUTOSYNC          0  /* Sample Clock Sources */
221
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ    1
222
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ  2
223
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ    3
224
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ    4
225
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ  5
226
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ    6
227
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ   7
228
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
229
 
#define HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ   9
230
295
 
231
296
/* Synccheck Status */
232
297
#define HDSPM_SYNC_CHECK_NO_LOCK 0
236
301
/* AutoSync References - used by "autosync_ref" control switch */
237
302
#define HDSPM_AUTOSYNC_FROM_WORD      0
238
303
#define HDSPM_AUTOSYNC_FROM_MADI      1
239
 
#define HDSPM_AUTOSYNC_FROM_NONE      2
 
304
#define HDSPM_AUTOSYNC_FROM_TCO       2
 
305
#define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 
306
#define HDSPM_AUTOSYNC_FROM_NONE      4
240
307
 
241
308
/* Possible sources of MADI input */
242
309
#define HDSPM_OPTICAL 0         /* optical   */
243
310
#define HDSPM_COAXIAL 1         /* BNC */
244
311
 
245
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#define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
246
 
#define hdspm_decode_latency(x)       (((x) & HDSPM_LatencyMask)>>1)
 
313
#define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
247
314
 
248
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#define hdspm_encode_in(x) (((x)&0x3)<<14)
249
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#define hdspm_decode_in(x) (((x)>>14)&0x3)
270
337
#define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
271
338
                                         * (like inp0)
272
339
                                         */
 
340
 
273
341
#define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 
342
#define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 
343
 
 
344
#define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
 
345
#define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
 
346
 
 
347
#define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
 
348
#define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
274
349
 
275
350
#define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
276
 
                                           /* since 64byte accurate last 6 bits 
277
 
                                              are not used */
278
 
 
279
 
#define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 
351
                        /* since 64byte accurate, last 6 bits are not used */
 
352
 
 
353
 
 
354
 
280
355
#define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
281
356
 
282
357
#define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
287
362
#define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
288
363
                                         * Interrupt
289
364
                                         */
290
 
#define HDSPM_midi0IRQPending   (1<<30) /* MIDI IRQ is pending  */
291
 
#define HDSPM_midi1IRQPending   (1<<31) /* and aktiv */
 
365
#define HDSPM_tco_detect         0x08000000
 
366
#define HDSPM_tco_lock           0x20000000
 
367
 
 
368
#define HDSPM_s2_tco_detect      0x00000040
 
369
#define HDSPM_s2_AEBO_D          0x00000080
 
370
#define HDSPM_s2_AEBI_D          0x00000100
 
371
 
 
372
 
 
373
#define HDSPM_midi0IRQPending    0x40000000
 
374
#define HDSPM_midi1IRQPending    0x80000000
 
375
#define HDSPM_midi2IRQPending    0x20000000
 
376
#define HDSPM_midi2IRQPendingAES 0x00000020
 
377
#define HDSPM_midi3IRQPending    0x00200000
292
378
 
293
379
/* --- status bit helpers */
294
380
#define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
305
391
 
306
392
/* Status2 Register bits */ /* MADI ONLY */
307
393
 
308
 
#define HDSPM_version0 (1<<0)   /* not realy defined but I guess */
 
394
#define HDSPM_version0 (1<<0)   /* not really defined but I guess */
309
395
#define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
310
396
#define HDSPM_version2 (1<<2)
311
397
 
317
403
#define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
318
404
/* missing Bit   for               111=128, 1000=176.4, 1001=192 */
319
405
 
320
 
#define HDSPM_SelSyncRef0 (1<<8)        /* Sync Source in slave mode */
 
406
#define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 
407
#define HDSPM_SyncRef1 0x20000
 
408
 
 
409
#define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
321
410
#define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
322
411
#define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
323
412
 
331
420
#define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
332
421
#define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
333
422
 
 
423
#define HDSPM_status1_F_0 0x0400000
 
424
#define HDSPM_status1_F_1 0x0800000
 
425
#define HDSPM_status1_F_2 0x1000000
 
426
#define HDSPM_status1_F_3 0x2000000
 
427
#define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 
428
 
334
429
 
335
430
#define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
336
431
                                    HDSPM_SelSyncRef2)
337
432
#define HDSPM_SelSyncRef_WORD      0
338
433
#define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 
434
#define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 
435
#define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
339
436
#define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
340
437
                                    HDSPM_SelSyncRef2)
341
438
 
345
442
/* status */
346
443
#define HDSPM_AES32_wcLock      0x0200000
347
444
#define HDSPM_AES32_wcFreq_bit  22
348
 
/* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 
 
445
/* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
349
446
  HDSPM_bit2freq */
350
447
#define HDSPM_AES32_syncref_bit  16
351
448
/* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
398
495
#define MADI_DS_CHANNELS       32
399
496
#define MADI_QS_CHANNELS       16
400
497
 
 
498
#define RAYDAT_SS_CHANNELS     36
 
499
#define RAYDAT_DS_CHANNELS     20
 
500
#define RAYDAT_QS_CHANNELS     12
 
501
 
 
502
#define AIO_IN_SS_CHANNELS        14
 
503
#define AIO_IN_DS_CHANNELS        10
 
504
#define AIO_IN_QS_CHANNELS        8
 
505
#define AIO_OUT_SS_CHANNELS        16
 
506
#define AIO_OUT_DS_CHANNELS        12
 
507
#define AIO_OUT_QS_CHANNELS        10
 
508
 
 
509
#define AES32_CHANNELS          16
 
510
 
401
511
/* the size of a substream (1 mono data stream) */
402
512
#define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
403
513
#define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
404
514
 
405
515
/* the size of the area we need to allocate for DMA transfers. the
406
516
   size is the same regardless of the number of channels, and
407
 
   also the latency to use. 
 
517
   also the latency to use.
408
518
   for one direction !!!
409
519
*/
410
520
#define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
411
521
#define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
412
522
 
413
523
/* revisions >= 230 indicate AES32 card */
414
 
#define HDSPM_AESREVISION 230
 
524
#define HDSPM_MADI_OLD_REV      207
 
525
#define HDSPM_MADI_REV          210
 
526
#define HDSPM_RAYDAT_REV        211
 
527
#define HDSPM_AIO_REV           212
 
528
#define HDSPM_MADIFACE_REV      213
 
529
#define HDSPM_AES_REV           240
 
530
#define HDSPM_AES32_REV         234
 
531
#define HDSPM_AES32_OLD_REV     233
415
532
 
416
533
/* speed factor modes */
417
534
#define HDSPM_SPEED_SINGLE 0
418
535
#define HDSPM_SPEED_DOUBLE 1
419
536
#define HDSPM_SPEED_QUAD   2
 
537
 
420
538
/* names for speed modes */
421
539
static char *hdspm_speed_names[] = { "single", "double", "quad" };
422
540
 
 
541
static char *texts_autosync_aes_tco[] = { "Word Clock",
 
542
                                          "AES1", "AES2", "AES3", "AES4",
 
543
                                          "AES5", "AES6", "AES7", "AES8",
 
544
                                          "TCO" };
 
545
static char *texts_autosync_aes[] = { "Word Clock",
 
546
                                      "AES1", "AES2", "AES3", "AES4",
 
547
                                      "AES5", "AES6", "AES7", "AES8" };
 
548
static char *texts_autosync_madi_tco[] = { "Word Clock",
 
549
                                           "MADI", "TCO", "Sync In" };
 
550
static char *texts_autosync_madi[] = { "Word Clock",
 
551
                                       "MADI", "Sync In" };
 
552
 
 
553
static char *texts_autosync_raydat_tco[] = {
 
554
        "Word Clock",
 
555
        "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 
556
        "AES", "SPDIF", "TCO", "Sync In"
 
557
};
 
558
static char *texts_autosync_raydat[] = {
 
559
        "Word Clock",
 
560
        "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 
561
        "AES", "SPDIF", "Sync In"
 
562
};
 
563
static char *texts_autosync_aio_tco[] = {
 
564
        "Word Clock",
 
565
        "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 
566
};
 
567
static char *texts_autosync_aio[] = { "Word Clock",
 
568
                                      "ADAT", "AES", "SPDIF", "Sync In" };
 
569
 
 
570
static char *texts_freq[] = {
 
571
        "No Lock",
 
572
        "32 kHz",
 
573
        "44.1 kHz",
 
574
        "48 kHz",
 
575
        "64 kHz",
 
576
        "88.2 kHz",
 
577
        "96 kHz",
 
578
        "128 kHz",
 
579
        "176.4 kHz",
 
580
        "192 kHz"
 
581
};
 
582
 
 
583
static char *texts_ports_madi[] = {
 
584
        "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 
585
        "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 
586
        "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 
587
        "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 
588
        "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 
589
        "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 
590
        "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 
591
        "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 
592
        "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 
593
        "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 
594
        "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 
595
};
 
596
 
 
597
 
 
598
static char *texts_ports_raydat_ss[] = {
 
599
        "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 
600
        "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 
601
        "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 
602
        "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 
603
        "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 
604
        "ADAT4.7", "ADAT4.8",
 
605
        "AES.L", "AES.R",
 
606
        "SPDIF.L", "SPDIF.R"
 
607
};
 
608
 
 
609
static char *texts_ports_raydat_ds[] = {
 
610
        "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 
611
        "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 
612
        "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 
613
        "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 
614
        "AES.L", "AES.R",
 
615
        "SPDIF.L", "SPDIF.R"
 
616
};
 
617
 
 
618
static char *texts_ports_raydat_qs[] = {
 
619
        "ADAT1.1", "ADAT1.2",
 
620
        "ADAT2.1", "ADAT2.2",
 
621
        "ADAT3.1", "ADAT3.2",
 
622
        "ADAT4.1", "ADAT4.2",
 
623
        "AES.L", "AES.R",
 
624
        "SPDIF.L", "SPDIF.R"
 
625
};
 
626
 
 
627
 
 
628
static char *texts_ports_aio_in_ss[] = {
 
629
        "Analogue.L", "Analogue.R",
 
630
        "AES.L", "AES.R",
 
631
        "SPDIF.L", "SPDIF.R",
 
632
        "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 
633
        "ADAT.7", "ADAT.8"
 
634
};
 
635
 
 
636
static char *texts_ports_aio_out_ss[] = {
 
637
        "Analogue.L", "Analogue.R",
 
638
        "AES.L", "AES.R",
 
639
        "SPDIF.L", "SPDIF.R",
 
640
        "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 
641
        "ADAT.7", "ADAT.8",
 
642
        "Phone.L", "Phone.R"
 
643
};
 
644
 
 
645
static char *texts_ports_aio_in_ds[] = {
 
646
        "Analogue.L", "Analogue.R",
 
647
        "AES.L", "AES.R",
 
648
        "SPDIF.L", "SPDIF.R",
 
649
        "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
 
650
};
 
651
 
 
652
static char *texts_ports_aio_out_ds[] = {
 
653
        "Analogue.L", "Analogue.R",
 
654
        "AES.L", "AES.R",
 
655
        "SPDIF.L", "SPDIF.R",
 
656
        "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 
657
        "Phone.L", "Phone.R"
 
658
};
 
659
 
 
660
static char *texts_ports_aio_in_qs[] = {
 
661
        "Analogue.L", "Analogue.R",
 
662
        "AES.L", "AES.R",
 
663
        "SPDIF.L", "SPDIF.R",
 
664
        "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
 
665
};
 
666
 
 
667
static char *texts_ports_aio_out_qs[] = {
 
668
        "Analogue.L", "Analogue.R",
 
669
        "AES.L", "AES.R",
 
670
        "SPDIF.L", "SPDIF.R",
 
671
        "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 
672
        "Phone.L", "Phone.R"
 
673
};
 
674
 
 
675
static char *texts_ports_aes32[] = {
 
676
        "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 
677
        "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 
678
        "AES.15", "AES.16"
 
679
};
 
680
 
 
681
/* These tables map the ALSA channels 1..N to the channels that we
 
682
   need to use in order to find the relevant channel buffer. RME
 
683
   refers to this kind of mapping as between "the ADAT channel and
 
684
   the DMA channel." We index it using the logical audio channel,
 
685
   and the value is the DMA channel (i.e. channel buffer number)
 
686
   where the data for that channel can be read/written from/to.
 
687
*/
 
688
 
 
689
static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 
690
        0, 1, 2, 3, 4, 5, 6, 7,
 
691
        8, 9, 10, 11, 12, 13, 14, 15,
 
692
        16, 17, 18, 19, 20, 21, 22, 23,
 
693
        24, 25, 26, 27, 28, 29, 30, 31,
 
694
        32, 33, 34, 35, 36, 37, 38, 39,
 
695
        40, 41, 42, 43, 44, 45, 46, 47,
 
696
        48, 49, 50, 51, 52, 53, 54, 55,
 
697
        56, 57, 58, 59, 60, 61, 62, 63
 
698
};
 
699
 
 
700
static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 
701
        4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 
702
        12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 
703
        20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 
704
        28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 
705
        0, 1,                   /* AES */
 
706
        2, 3,                   /* SPDIF */
 
707
        -1, -1, -1, -1,
 
708
        -1, -1, -1, -1, -1, -1, -1, -1,
 
709
        -1, -1, -1, -1, -1, -1, -1, -1,
 
710
        -1, -1, -1, -1, -1, -1, -1, -1,
 
711
};
 
712
 
 
713
static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 
714
        4, 5, 6, 7,             /* ADAT 1 */
 
715
        8, 9, 10, 11,           /* ADAT 2 */
 
716
        12, 13, 14, 15,         /* ADAT 3 */
 
717
        16, 17, 18, 19,         /* ADAT 4 */
 
718
        0, 1,                   /* AES */
 
719
        2, 3,                   /* SPDIF */
 
720
        -1, -1, -1, -1,
 
721
        -1, -1, -1, -1, -1, -1, -1, -1,
 
722
        -1, -1, -1, -1, -1, -1, -1, -1,
 
723
        -1, -1, -1, -1, -1, -1, -1, -1,
 
724
        -1, -1, -1, -1, -1, -1, -1, -1,
 
725
        -1, -1, -1, -1, -1, -1, -1, -1,
 
726
};
 
727
 
 
728
static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 
729
        4, 5,                   /* ADAT 1 */
 
730
        6, 7,                   /* ADAT 2 */
 
731
        8, 9,                   /* ADAT 3 */
 
732
        10, 11,                 /* ADAT 4 */
 
733
        0, 1,                   /* AES */
 
734
        2, 3,                   /* SPDIF */
 
735
        -1, -1, -1, -1,
 
736
        -1, -1, -1, -1, -1, -1, -1, -1,
 
737
        -1, -1, -1, -1, -1, -1, -1, -1,
 
738
        -1, -1, -1, -1, -1, -1, -1, -1,
 
739
        -1, -1, -1, -1, -1, -1, -1, -1,
 
740
        -1, -1, -1, -1, -1, -1, -1, -1,
 
741
        -1, -1, -1, -1, -1, -1, -1, -1,
 
742
};
 
743
 
 
744
static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 
745
        0, 1,                   /* line in */
 
746
        8, 9,                   /* aes in, */
 
747
        10, 11,                 /* spdif in */
 
748
        12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 
749
        -1, -1,
 
750
        -1, -1, -1, -1, -1, -1, -1, -1,
 
751
        -1, -1, -1, -1, -1, -1, -1, -1,
 
752
        -1, -1, -1, -1, -1, -1, -1, -1,
 
753
        -1, -1, -1, -1, -1, -1, -1, -1,
 
754
        -1, -1, -1, -1, -1, -1, -1, -1,
 
755
        -1, -1, -1, -1, -1, -1, -1, -1,
 
756
};
 
757
 
 
758
static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 
759
        0, 1,                   /* line out */
 
760
        8, 9,                   /* aes out */
 
761
        10, 11,                 /* spdif out */
 
762
        12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 
763
        6, 7,                   /* phone out */
 
764
        -1, -1, -1, -1, -1, -1, -1, -1,
 
765
        -1, -1, -1, -1, -1, -1, -1, -1,
 
766
        -1, -1, -1, -1, -1, -1, -1, -1,
 
767
        -1, -1, -1, -1, -1, -1, -1, -1,
 
768
        -1, -1, -1, -1, -1, -1, -1, -1,
 
769
        -1, -1, -1, -1, -1, -1, -1, -1,
 
770
};
 
771
 
 
772
static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 
773
        0, 1,                   /* line in */
 
774
        8, 9,                   /* aes in */
 
775
        10, 11,                 /* spdif in */
 
776
        12, 14, 16, 18,         /* adat in */
 
777
        -1, -1, -1, -1, -1, -1,
 
778
        -1, -1, -1, -1, -1, -1, -1, -1,
 
779
        -1, -1, -1, -1, -1, -1, -1, -1,
 
780
        -1, -1, -1, -1, -1, -1, -1, -1,
 
781
        -1, -1, -1, -1, -1, -1, -1, -1,
 
782
        -1, -1, -1, -1, -1, -1, -1, -1,
 
783
        -1, -1, -1, -1, -1, -1, -1, -1
 
784
};
 
785
 
 
786
static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 
787
        0, 1,                   /* line out */
 
788
        8, 9,                   /* aes out */
 
789
        10, 11,                 /* spdif out */
 
790
        12, 14, 16, 18,         /* adat out */
 
791
        6, 7,                   /* phone out */
 
792
        -1, -1, -1, -1,
 
793
        -1, -1, -1, -1, -1, -1, -1, -1,
 
794
        -1, -1, -1, -1, -1, -1, -1, -1,
 
795
        -1, -1, -1, -1, -1, -1, -1, -1,
 
796
        -1, -1, -1, -1, -1, -1, -1, -1,
 
797
        -1, -1, -1, -1, -1, -1, -1, -1,
 
798
        -1, -1, -1, -1, -1, -1, -1, -1
 
799
};
 
800
 
 
801
static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 
802
        0, 1,                   /* line in */
 
803
        8, 9,                   /* aes in */
 
804
        10, 11,                 /* spdif in */
 
805
        12, 16,                 /* adat in */
 
806
        -1, -1, -1, -1, -1, -1, -1, -1,
 
807
        -1, -1, -1, -1, -1, -1, -1, -1,
 
808
        -1, -1, -1, -1, -1, -1, -1, -1,
 
809
        -1, -1, -1, -1, -1, -1, -1, -1,
 
810
        -1, -1, -1, -1, -1, -1, -1, -1,
 
811
        -1, -1, -1, -1, -1, -1, -1, -1,
 
812
        -1, -1, -1, -1, -1, -1, -1, -1
 
813
};
 
814
 
 
815
static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 
816
        0, 1,                   /* line out */
 
817
        8, 9,                   /* aes out */
 
818
        10, 11,                 /* spdif out */
 
819
        12, 16,                 /* adat out */
 
820
        6, 7,                   /* phone out */
 
821
        -1, -1, -1, -1, -1, -1,
 
822
        -1, -1, -1, -1, -1, -1, -1, -1,
 
823
        -1, -1, -1, -1, -1, -1, -1, -1,
 
824
        -1, -1, -1, -1, -1, -1, -1, -1,
 
825
        -1, -1, -1, -1, -1, -1, -1, -1,
 
826
        -1, -1, -1, -1, -1, -1, -1, -1,
 
827
        -1, -1, -1, -1, -1, -1, -1, -1
 
828
};
 
829
 
 
830
static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 
831
        0, 1, 2, 3, 4, 5, 6, 7,
 
832
        8, 9, 10, 11, 12, 13, 14, 15,
 
833
        -1, -1, -1, -1, -1, -1, -1, -1,
 
834
        -1, -1, -1, -1, -1, -1, -1, -1,
 
835
        -1, -1, -1, -1, -1, -1, -1, -1,
 
836
        -1, -1, -1, -1, -1, -1, -1, -1,
 
837
        -1, -1, -1, -1, -1, -1, -1, -1,
 
838
        -1, -1, -1, -1, -1, -1, -1, -1
 
839
};
 
840
 
423
841
struct hdspm_midi {
424
842
        struct hdspm *hdspm;
425
843
        int id;
430
848
        struct timer_list timer;
431
849
        spinlock_t lock;
432
850
        int pending;
 
851
        int dataIn;
 
852
        int statusIn;
 
853
        int dataOut;
 
854
        int statusOut;
 
855
        int ie;
 
856
        int irq;
 
857
};
 
858
 
 
859
struct hdspm_tco {
 
860
        int input;
 
861
        int framerate;
 
862
        int wordclock;
 
863
        int samplerate;
 
864
        int pull;
 
865
        int term; /* 0 = off, 1 = on */
433
866
};
434
867
 
435
868
struct hdspm {
441
874
        char *card_name;             /* for procinfo */
442
875
        unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
443
876
 
444
 
        unsigned char is_aes32;    /* indicates if card is AES32 */
 
877
        uint8_t io_type;
445
878
 
446
 
        int precise_ptr;        /* use precise pointers, to be tested */
447
879
        int monitor_outs;       /* set up monitoring outs init flag */
448
880
 
449
881
        u32 control_register;   /* cached value */
450
882
        u32 control2_register;  /* cached value */
 
883
        u32 settings_register;
451
884
 
452
 
        struct hdspm_midi midi[2];
 
885
        struct hdspm_midi midi[4];
453
886
        struct tasklet_struct midi_tasklet;
454
887
 
455
888
        size_t period_bytes;
456
 
        unsigned char ss_channels;      /* channels of card in single speed */
457
 
        unsigned char ds_channels;      /* Double Speed */
458
 
        unsigned char qs_channels;      /* Quad Speed */
 
889
        unsigned char ss_in_channels;
 
890
        unsigned char ds_in_channels;
 
891
        unsigned char qs_in_channels;
 
892
        unsigned char ss_out_channels;
 
893
        unsigned char ds_out_channels;
 
894
        unsigned char qs_out_channels;
 
895
 
 
896
        unsigned char max_channels_in;
 
897
        unsigned char max_channels_out;
 
898
 
 
899
        signed char *channel_map_in;
 
900
        signed char *channel_map_out;
 
901
 
 
902
        signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
 
903
        signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
 
904
 
 
905
        char **port_names_in;
 
906
        char **port_names_out;
 
907
 
 
908
        char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
 
909
        char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
459
910
 
460
911
        unsigned char *playback_buffer; /* suitably aligned address */
461
912
        unsigned char *capture_buffer;  /* suitably aligned address */
468
919
        int last_internal_sample_rate;
469
920
        int system_sample_rate;
470
921
 
471
 
        char *channel_map;      /* channel map for DS and Quadspeed */
472
 
 
473
922
        int dev;                /* Hardware vars... */
474
923
        int irq;
475
924
        unsigned long port;
476
925
        void __iomem *iobase;
477
926
 
478
927
        int irq_count;          /* for debug */
 
928
        int midiPorts;
479
929
 
480
930
        struct snd_card *card;  /* one card */
481
931
        struct snd_pcm *pcm;            /* has one pcm */
490
940
        /* full mixer accessible over mixer ioctl or hwdep-device */
491
941
        struct hdspm_mixer *mixer;
492
942
 
493
 
};
494
 
 
495
 
/* These tables map the ALSA channels 1..N to the channels that we
496
 
   need to use in order to find the relevant channel buffer. RME
497
 
   refer to this kind of mapping as between "the ADAT channel and
498
 
   the DMA channel." We index it using the logical audio channel,
499
 
   and the value is the DMA channel (i.e. channel buffer number)
500
 
   where the data for that channel can be read/written from/to.
501
 
*/
502
 
 
503
 
static char channel_map_madi_ss[HDSPM_MAX_CHANNELS] = {
504
 
   0, 1, 2, 3, 4, 5, 6, 7,
505
 
   8, 9, 10, 11, 12, 13, 14, 15,
506
 
   16, 17, 18, 19, 20, 21, 22, 23,
507
 
   24, 25, 26, 27, 28, 29, 30, 31,
508
 
   32, 33, 34, 35, 36, 37, 38, 39,
509
 
   40, 41, 42, 43, 44, 45, 46, 47,
510
 
   48, 49, 50, 51, 52, 53, 54, 55,
511
 
   56, 57, 58, 59, 60, 61, 62, 63
 
943
        struct hdspm_tco *tco;  /* NULL if no TCO detected */
 
944
 
 
945
        char **texts_autosync;
 
946
        int texts_autosync_items;
 
947
 
 
948
        cycles_t last_interrupt;
 
949
 
 
950
        struct hdspm_peak_rms peak_rms;
512
951
};
513
952
 
514
953
 
532
971
static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
533
972
                                          struct hdspm * hdspm);
534
973
 
535
 
static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm);
536
 
static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm);
537
 
static int hdspm_autosync_ref(struct hdspm * hdspm);
538
 
static int snd_hdspm_set_defaults(struct hdspm * hdspm);
539
 
static void hdspm_set_sgbuf(struct hdspm * hdspm,
 
974
static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
 
975
static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
 
976
static int hdspm_autosync_ref(struct hdspm *hdspm);
 
977
static int snd_hdspm_set_defaults(struct hdspm *hdspm);
 
978
static void hdspm_set_sgbuf(struct hdspm *hdspm,
540
979
                            struct snd_pcm_substream *substream,
541
980
                             unsigned int reg, int channels);
542
981
 
550
989
        return bit2freq_tab[n];
551
990
}
552
991
 
553
 
/* Write/read to/from HDSPM with Addresses in Bytes
 
992
/* Write/read to/from HDSPM with Adresses in Bytes
554
993
   not words but only 32Bit writes are allowed */
555
994
 
556
995
static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
564
1003
        return readl(hdspm->iobase + reg);
565
1004
}
566
1005
 
567
 
/* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 
568
 
   mixer is write only on hardware so we have to cache him for read 
 
1006
/* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
 
1007
   mixer is write only on hardware so we have to cache him for read
569
1008
   each fader is a u32, but uses only the first 16 bit */
570
1009
 
571
1010
static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
641
1080
/* check for external sample rate */
642
1081
static int hdspm_external_sample_rate(struct hdspm *hdspm)
643
1082
{
644
 
        if (hdspm->is_aes32) {
645
 
                unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
646
 
                unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
647
 
                unsigned int timecode =
648
 
                        hdspm_read(hdspm, HDSPM_timecodeRegister);
649
 
 
650
 
                int syncref = hdspm_autosync_ref(hdspm);
 
1083
        unsigned int status, status2, timecode;
 
1084
        int syncref, rate = 0, rate_bits;
 
1085
 
 
1086
        switch (hdspm->io_type) {
 
1087
        case AES32:
 
1088
                status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 
1089
                status = hdspm_read(hdspm, HDSPM_statusRegister);
 
1090
                timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
 
1091
 
 
1092
                syncref = hdspm_autosync_ref(hdspm);
651
1093
 
652
1094
                if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
653
1095
                                status & HDSPM_AES32_wcLock)
654
 
                        return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit)
655
 
                                              & 0xF);
 
1096
                        return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
 
1097
 
656
1098
                if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
657
 
                        syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
658
 
                        status2 & (HDSPM_LockAES >>
659
 
                                  (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
660
 
                        return HDSPM_bit2freq((timecode >>
661
 
                          (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
 
1099
                                syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
 
1100
                                status2 & (HDSPM_LockAES >>
 
1101
                                (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
 
1102
                        return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
662
1103
                return 0;
663
 
        } else {
664
 
                unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
665
 
                unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
666
 
                unsigned int rate_bits;
667
 
                int rate = 0;
 
1104
                break;
 
1105
 
 
1106
        case MADIface:
 
1107
                status = hdspm_read(hdspm, HDSPM_statusRegister);
 
1108
 
 
1109
                if (!(status & HDSPM_madiLock)) {
 
1110
                        rate = 0;  /* no lock */
 
1111
                } else {
 
1112
                        switch (status & (HDSPM_status1_freqMask)) {
 
1113
                        case HDSPM_status1_F_0*1:
 
1114
                                rate = 32000; break;
 
1115
                        case HDSPM_status1_F_0*2:
 
1116
                                rate = 44100; break;
 
1117
                        case HDSPM_status1_F_0*3:
 
1118
                                rate = 48000; break;
 
1119
                        case HDSPM_status1_F_0*4:
 
1120
                                rate = 64000; break;
 
1121
                        case HDSPM_status1_F_0*5:
 
1122
                                rate = 88200; break;
 
1123
                        case HDSPM_status1_F_0*6:
 
1124
                                rate = 96000; break;
 
1125
                        case HDSPM_status1_F_0*7:
 
1126
                                rate = 128000; break;
 
1127
                        case HDSPM_status1_F_0*8:
 
1128
                                rate = 176400; break;
 
1129
                        case HDSPM_status1_F_0*9:
 
1130
                                rate = 192000; break;
 
1131
                        default:
 
1132
                                rate = 0; break;
 
1133
                        }
 
1134
                }
 
1135
 
 
1136
                break;
 
1137
 
 
1138
        case MADI:
 
1139
        case AIO:
 
1140
        case RayDAT:
 
1141
                status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 
1142
                status = hdspm_read(hdspm, HDSPM_statusRegister);
 
1143
                rate = 0;
668
1144
 
669
1145
                /* if wordclock has synced freq and wordclock is valid */
670
1146
                if ((status2 & HDSPM_wcLock) != 0 &&
671
 
                                (status & HDSPM_SelSyncRef0) == 0) {
 
1147
                                (status2 & HDSPM_SelSyncRef0) == 0) {
672
1148
 
673
1149
                        rate_bits = status2 & HDSPM_wcFreqMask;
674
1150
 
 
1151
 
675
1152
                        switch (rate_bits) {
676
1153
                        case HDSPM_wcFreq32:
677
1154
                                rate = 32000;
691
1168
                        case HDSPM_wcFreq96:
692
1169
                                rate = 96000;
693
1170
                                break;
694
 
                                /* Quadspeed Bit missing ???? */
695
1171
                        default:
696
1172
                                rate = 0;
697
1173
                                break;
702
1178
                 * word has priority to MADI
703
1179
                 */
704
1180
                if (rate != 0 &&
705
 
                    (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
 
1181
                (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
706
1182
                        return rate;
707
1183
 
708
 
                /* maby a madi input (which is taken if sel sync is madi) */
 
1184
                /* maybe a madi input (which is taken if sel sync is madi) */
709
1185
                if (status & HDSPM_madiLock) {
710
1186
                        rate_bits = status & HDSPM_madiFreqMask;
711
1187
 
742
1218
                                break;
743
1219
                        }
744
1220
                }
745
 
                return rate;
 
1221
                break;
746
1222
        }
 
1223
 
 
1224
        return rate;
747
1225
}
748
1226
 
749
1227
/* Latency function */
750
 
static inline void hdspm_compute_period_size(struct hdspm * hdspm)
 
1228
static inline void hdspm_compute_period_size(struct hdspm *hdspm)
751
1229
{
752
 
        hdspm->period_bytes =
753
 
            1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
 
1230
        hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
754
1231
}
755
1232
 
756
 
static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm * hdspm)
 
1233
 
 
1234
static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
757
1235
{
758
1236
        int position;
759
1237
 
760
1238
        position = hdspm_read(hdspm, HDSPM_statusRegister);
761
1239
 
762
 
        if (!hdspm->precise_ptr)
763
 
                return (position & HDSPM_BufferID) ?
 
1240
        switch (hdspm->io_type) {
 
1241
        case RayDAT:
 
1242
        case AIO:
 
1243
                position &= HDSPM_BufferPositionMask;
 
1244
                position /= 4; /* Bytes per sample */
 
1245
                break;
 
1246
        default:
 
1247
                position = (position & HDSPM_BufferID) ?
764
1248
                        (hdspm->period_bytes / 4) : 0;
765
 
 
766
 
        /* hwpointer comes in bytes and is 64Bytes accurate (by docu since
767
 
           PCI Burst)
768
 
           i have experimented that it is at most 64 Byte to much for playing 
769
 
           so substraction of 64 byte should be ok for ALSA, but use it only
770
 
           for application where you know what you do since if you come to
771
 
           near with record pointer it can be a disaster */
772
 
 
773
 
        position &= HDSPM_BufferPositionMask;
774
 
        position = ((position - 64) % (2 * hdspm->period_bytes)) / 4;
 
1249
        }
775
1250
 
776
1251
        return position;
777
1252
}
805
1280
        }
806
1281
}
807
1282
 
808
 
static int hdspm_set_interrupt_interval(struct hdspm * s, unsigned int frames)
 
1283
static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
809
1284
{
810
1285
        int n;
811
1286
 
829
1304
        return 0;
830
1305
}
831
1306
 
 
1307
static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
 
1308
{
 
1309
        u64 freq_const;
 
1310
 
 
1311
        if (period == 0)
 
1312
                return 0;
 
1313
 
 
1314
        switch (hdspm->io_type) {
 
1315
        case MADI:
 
1316
        case AES32:
 
1317
                freq_const = 110069313433624ULL;
 
1318
                break;
 
1319
        case RayDAT:
 
1320
        case AIO:
 
1321
                freq_const = 104857600000000ULL;
 
1322
                break;
 
1323
        case MADIface:
 
1324
                freq_const = 131072000000000ULL;
 
1325
        }
 
1326
 
 
1327
        return div_u64(freq_const, period);
 
1328
}
 
1329
 
 
1330
 
832
1331
static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
833
1332
{
834
1333
        u64 n;
835
 
        
 
1334
 
836
1335
        if (rate >= 112000)
837
1336
                rate /= 4;
838
1337
        else if (rate >= 56000)
839
1338
                rate /= 2;
840
1339
 
841
 
        /* RME says n = 104857600000000, but in the windows MADI driver, I see:
842
 
//      return 104857600000000 / rate; // 100 MHz
843
 
        return 110100480000000 / rate; // 105 MHz
844
 
        */         
845
 
        /* n = 104857600000000ULL; */ /*  =  2^20 * 10^8 */
846
 
        n = 110100480000000ULL;    /* Value checked for AES32 and MADI */
 
1340
        switch (hdspm->io_type) {
 
1341
        case MADIface:
 
1342
          n = 131072000000000ULL;  /* 125 MHz */
 
1343
          break;
 
1344
        case MADI:
 
1345
        case AES32:
 
1346
          n = 110069313433624ULL;  /* 105 MHz */
 
1347
          break;
 
1348
        case RayDAT:
 
1349
        case AIO:
 
1350
          n = 104857600000000ULL;  /* 100 MHz */
 
1351
          break;
 
1352
        }
 
1353
 
847
1354
        n = div_u64(n, rate);
848
1355
        /* n should be less than 2^32 for being written to FREQ register */
849
1356
        snd_BUG_ON(n >> 32);
864
1371
 
865
1372
        if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
866
1373
 
867
 
                /* SLAVE --- */ 
 
1374
                /* SLAVE --- */
868
1375
                if (called_internally) {
869
1376
 
870
 
                  /* request from ctl or card initialization 
871
 
                     just make a warning an remember setting 
872
 
                     for future master mode switching */
873
 
    
 
1377
                        /* request from ctl or card initialization
 
1378
                           just make a warning an remember setting
 
1379
                           for future master mode switching */
 
1380
 
874
1381
                        snd_printk(KERN_WARNING "HDSPM: "
875
1382
                                   "Warning: device is not running "
876
1383
                                   "as a clock master.\n");
907
1414
 
908
1415
           Note that a similar but essentially insoluble problem exists for
909
1416
           externally-driven rate changes. All we can do is to flag rate
910
 
           changes in the read/write routines.  
 
1417
           changes in the read/write routines.
911
1418
         */
912
1419
 
913
1420
        if (current_rate <= 48000)
975
1482
        /* For AES32, need to set DDS value in FREQ register
976
1483
           For MADI, also apparently */
977
1484
        hdspm_set_dds_value(hdspm, rate);
978
 
        
979
 
        if (hdspm->is_aes32 && rate != current_rate)
 
1485
 
 
1486
        if (AES32 == hdspm->io_type && rate != current_rate)
980
1487
                hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
981
 
        
982
 
        /* For AES32 and for MADI (at least rev 204), channel_map needs to
983
 
         * always be channel_map_madi_ss, whatever the sample rate */
984
 
        hdspm->channel_map = channel_map_madi_ss;
985
1488
 
986
1489
        hdspm->system_sample_rate = rate;
987
1490
 
 
1491
        if (rate <= 48000) {
 
1492
                hdspm->channel_map_in = hdspm->channel_map_in_ss;
 
1493
                hdspm->channel_map_out = hdspm->channel_map_out_ss;
 
1494
                hdspm->max_channels_in = hdspm->ss_in_channels;
 
1495
                hdspm->max_channels_out = hdspm->ss_out_channels;
 
1496
                hdspm->port_names_in = hdspm->port_names_in_ss;
 
1497
                hdspm->port_names_out = hdspm->port_names_out_ss;
 
1498
        } else if (rate <= 96000) {
 
1499
                hdspm->channel_map_in = hdspm->channel_map_in_ds;
 
1500
                hdspm->channel_map_out = hdspm->channel_map_out_ds;
 
1501
                hdspm->max_channels_in = hdspm->ds_in_channels;
 
1502
                hdspm->max_channels_out = hdspm->ds_out_channels;
 
1503
                hdspm->port_names_in = hdspm->port_names_in_ds;
 
1504
                hdspm->port_names_out = hdspm->port_names_out_ds;
 
1505
        } else {
 
1506
                hdspm->channel_map_in = hdspm->channel_map_in_qs;
 
1507
                hdspm->channel_map_out = hdspm->channel_map_out_qs;
 
1508
                hdspm->max_channels_in = hdspm->qs_in_channels;
 
1509
                hdspm->max_channels_out = hdspm->qs_out_channels;
 
1510
                hdspm->port_names_in = hdspm->port_names_in_qs;
 
1511
                hdspm->port_names_out = hdspm->port_names_out_qs;
 
1512
        }
 
1513
 
988
1514
        if (not_set != 0)
989
1515
                return -1;
990
1516
 
1019
1545
                                                      int id)
1020
1546
{
1021
1547
        /* the hardware already does the relevant bit-mask with 0xff */
1022
 
        if (id)
1023
 
                return hdspm_read(hdspm, HDSPM_midiDataIn1);
1024
 
        else
1025
 
                return hdspm_read(hdspm, HDSPM_midiDataIn0);
 
1548
        return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1026
1549
}
1027
1550
 
1028
1551
static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1029
1552
                                              int val)
1030
1553
{
1031
1554
        /* the hardware already does the relevant bit-mask with 0xff */
1032
 
        if (id)
1033
 
                hdspm_write(hdspm, HDSPM_midiDataOut1, val);
1034
 
        else
1035
 
                hdspm_write(hdspm, HDSPM_midiDataOut0, val);
 
1555
        return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1036
1556
}
1037
1557
 
1038
1558
static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1039
1559
{
1040
 
        if (id)
1041
 
                return (hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff);
1042
 
        else
1043
 
                return (hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff);
 
1560
        return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1044
1561
}
1045
1562
 
1046
1563
static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1047
1564
{
1048
1565
        int fifo_bytes_used;
1049
1566
 
1050
 
        if (id)
1051
 
                fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut1);
1052
 
        else
1053
 
                fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut0);
1054
 
        fifo_bytes_used &= 0xff;
 
1567
        fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1055
1568
 
1056
1569
        if (fifo_bytes_used < 128)
1057
1570
                return  128 - fifo_bytes_used;
1074
1587
        unsigned char buf[128];
1075
1588
 
1076
1589
        /* Output is not interrupt driven */
1077
 
                
 
1590
 
1078
1591
        spin_lock_irqsave (&hmidi->lock, flags);
1079
1592
        if (hmidi->output &&
1080
1593
            !snd_rawmidi_transmit_empty (hmidi->output)) {
1083
1596
                if (n_pending > 0) {
1084
1597
                        if (n_pending > (int)sizeof (buf))
1085
1598
                                n_pending = sizeof (buf);
1086
 
                
 
1599
 
1087
1600
                        to_write = snd_rawmidi_transmit (hmidi->output, buf,
1088
1601
                                                         n_pending);
1089
1602
                        if (to_write > 0) {
1090
 
                                for (i = 0; i < to_write; ++i) 
 
1603
                                for (i = 0; i < to_write; ++i)
1091
1604
                                        snd_hdspm_midi_write_byte (hmidi->hdspm,
1092
1605
                                                                   hmidi->id,
1093
1606
                                                                   buf[i]);
1127
1640
                }
1128
1641
        }
1129
1642
        hmidi->pending = 0;
1130
 
        if (hmidi->id)
1131
 
                hmidi->hdspm->control_register |= HDSPM_Midi1InterruptEnable;
1132
 
        else
1133
 
                hmidi->hdspm->control_register |= HDSPM_Midi0InterruptEnable;
 
1643
        spin_unlock_irqrestore(&hmidi->lock, flags);
 
1644
 
 
1645
        spin_lock_irqsave(&hmidi->hdspm->lock, flags);
 
1646
        hmidi->hdspm->control_register |= hmidi->ie;
1134
1647
        hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1135
1648
                    hmidi->hdspm->control_register);
1136
 
        spin_unlock_irqrestore (&hmidi->lock, flags);
 
1649
        spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
 
1650
 
1137
1651
        return snd_hdspm_midi_output_write (hmidi);
1138
1652
}
1139
1653
 
1143
1657
        struct hdspm *hdspm;
1144
1658
        struct hdspm_midi *hmidi;
1145
1659
        unsigned long flags;
1146
 
        u32 ie;
1147
1660
 
1148
1661
        hmidi = substream->rmidi->private_data;
1149
1662
        hdspm = hmidi->hdspm;
1150
 
        ie = hmidi->id ?
1151
 
                HDSPM_Midi1InterruptEnable : HDSPM_Midi0InterruptEnable;
 
1663
 
1152
1664
        spin_lock_irqsave (&hdspm->lock, flags);
1153
1665
        if (up) {
1154
 
                if (!(hdspm->control_register & ie)) {
 
1666
                if (!(hdspm->control_register & hmidi->ie)) {
1155
1667
                        snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1156
 
                        hdspm->control_register |= ie;
 
1668
                        hdspm->control_register |= hmidi->ie;
1157
1669
                }
1158
1670
        } else {
1159
 
                hdspm->control_register &= ~ie;
 
1671
                hdspm->control_register &= ~hmidi->ie;
1160
1672
        }
1161
1673
 
1162
1674
        hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1167
1679
{
1168
1680
        struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1169
1681
        unsigned long flags;
1170
 
        
 
1682
 
1171
1683
        snd_hdspm_midi_output_write(hmidi);
1172
1684
        spin_lock_irqsave (&hmidi->lock, flags);
1173
1685
 
1174
1686
        /* this does not bump hmidi->istimer, because the
1175
1687
           kernel automatically removed the timer when it
1176
1688
           expired, and we are now adding it back, thus
1177
 
           leaving istimer wherever it was set before.  
 
1689
           leaving istimer wherever it was set before.
1178
1690
        */
1179
1691
 
1180
1692
        if (hmidi->istimer) {
1288
1800
        hdspm->midi[id].hdspm = hdspm;
1289
1801
        spin_lock_init (&hdspm->midi[id].lock);
1290
1802
 
1291
 
        sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1292
 
        err = snd_rawmidi_new (card, buf, id, 1, 1, &hdspm->midi[id].rmidi);
1293
 
        if (err < 0)
1294
 
                return err;
1295
 
 
1296
 
        sprintf(hdspm->midi[id].rmidi->name, "HDSPM MIDI %d", id+1);
1297
 
        hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1298
 
 
1299
 
        snd_rawmidi_set_ops(hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
1300
 
                            &snd_hdspm_midi_output);
1301
 
        snd_rawmidi_set_ops(hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
1302
 
                            &snd_hdspm_midi_input);
1303
 
 
1304
 
        hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1305
 
                SNDRV_RAWMIDI_INFO_INPUT |
1306
 
                SNDRV_RAWMIDI_INFO_DUPLEX;
 
1803
        if (0 == id) {
 
1804
                if (MADIface == hdspm->io_type) {
 
1805
                        /* MIDI-over-MADI on HDSPe MADIface */
 
1806
                        hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
 
1807
                        hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
 
1808
                        hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
 
1809
                        hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
 
1810
                        hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
 
1811
                        hdspm->midi[0].irq = HDSPM_midi2IRQPending;
 
1812
                } else {
 
1813
                        hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
 
1814
                        hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
 
1815
                        hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
 
1816
                        hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
 
1817
                        hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
 
1818
                        hdspm->midi[0].irq = HDSPM_midi0IRQPending;
 
1819
                }
 
1820
        } else if (1 == id) {
 
1821
                hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
 
1822
                hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
 
1823
                hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
 
1824
                hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
 
1825
                hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
 
1826
                hdspm->midi[1].irq = HDSPM_midi1IRQPending;
 
1827
        } else if ((2 == id) && (MADI == hdspm->io_type)) {
 
1828
                /* MIDI-over-MADI on HDSPe MADI */
 
1829
                hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
 
1830
                hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
 
1831
                hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
 
1832
                hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
 
1833
                hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
 
1834
                hdspm->midi[2].irq = HDSPM_midi2IRQPending;
 
1835
        } else if (2 == id) {
 
1836
                /* TCO MTC, read only */
 
1837
                hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
 
1838
                hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
 
1839
                hdspm->midi[2].dataOut = -1;
 
1840
                hdspm->midi[2].statusOut = -1;
 
1841
                hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
 
1842
                hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
 
1843
        } else if (3 == id) {
 
1844
                /* TCO MTC on HDSPe MADI */
 
1845
                hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
 
1846
                hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
 
1847
                hdspm->midi[3].dataOut = -1;
 
1848
                hdspm->midi[3].statusOut = -1;
 
1849
                hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
 
1850
                hdspm->midi[3].irq = HDSPM_midi3IRQPending;
 
1851
        }
 
1852
 
 
1853
        if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
 
1854
                                        (MADIface == hdspm->io_type)))) {
 
1855
                if ((id == 0) && (MADIface == hdspm->io_type)) {
 
1856
                        sprintf(buf, "%s MIDIoverMADI", card->shortname);
 
1857
                } else if ((id == 2) && (MADI == hdspm->io_type)) {
 
1858
                        sprintf(buf, "%s MIDIoverMADI", card->shortname);
 
1859
                } else {
 
1860
                        sprintf(buf, "%s MIDI %d", card->shortname, id+1);
 
1861
                }
 
1862
                err = snd_rawmidi_new(card, buf, id, 1, 1,
 
1863
                                &hdspm->midi[id].rmidi);
 
1864
                if (err < 0)
 
1865
                        return err;
 
1866
 
 
1867
                sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
 
1868
                                card->id, id+1);
 
1869
                hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
 
1870
 
 
1871
                snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
 
1872
                                SNDRV_RAWMIDI_STREAM_OUTPUT,
 
1873
                                &snd_hdspm_midi_output);
 
1874
                snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
 
1875
                                SNDRV_RAWMIDI_STREAM_INPUT,
 
1876
                                &snd_hdspm_midi_input);
 
1877
 
 
1878
                hdspm->midi[id].rmidi->info_flags |=
 
1879
                        SNDRV_RAWMIDI_INFO_OUTPUT |
 
1880
                        SNDRV_RAWMIDI_INFO_INPUT |
 
1881
                        SNDRV_RAWMIDI_INFO_DUPLEX;
 
1882
        } else {
 
1883
                /* TCO MTC, read only */
 
1884
                sprintf(buf, "%s MTC %d", card->shortname, id+1);
 
1885
                err = snd_rawmidi_new(card, buf, id, 1, 1,
 
1886
                                &hdspm->midi[id].rmidi);
 
1887
                if (err < 0)
 
1888
                        return err;
 
1889
 
 
1890
                sprintf(hdspm->midi[id].rmidi->name,
 
1891
                                "%s MTC %d", card->id, id+1);
 
1892
                hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
 
1893
 
 
1894
                snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
 
1895
                                SNDRV_RAWMIDI_STREAM_INPUT,
 
1896
                                &snd_hdspm_midi_input);
 
1897
 
 
1898
                hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
 
1899
        }
1307
1900
 
1308
1901
        return 0;
1309
1902
}
1312
1905
static void hdspm_midi_tasklet(unsigned long arg)
1313
1906
{
1314
1907
        struct hdspm *hdspm = (struct hdspm *)arg;
1315
 
        
1316
 
        if (hdspm->midi[0].pending)
1317
 
                snd_hdspm_midi_input_read (&hdspm->midi[0]);
1318
 
        if (hdspm->midi[1].pending)
1319
 
                snd_hdspm_midi_input_read (&hdspm->midi[1]);
1320
 
} 
 
1908
        int i = 0;
 
1909
 
 
1910
        while (i < hdspm->midiPorts) {
 
1911
                if (hdspm->midi[i].pending)
 
1912
                        snd_hdspm_midi_input_read(&hdspm->midi[i]);
 
1913
 
 
1914
                i++;
 
1915
        }
 
1916
}
1321
1917
 
1322
1918
 
1323
1919
/*-----------------------------------------------------------------------------
1326
1922
 
1327
1923
/* get the system sample rate which is set */
1328
1924
 
 
1925
 
 
1926
/**
 
1927
 * Calculate the real sample rate from the
 
1928
 * current DDS value.
 
1929
 **/
 
1930
static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
 
1931
{
 
1932
        unsigned int period, rate;
 
1933
 
 
1934
        period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
 
1935
        rate = hdspm_calc_dds_value(hdspm, period);
 
1936
 
 
1937
        return rate;
 
1938
}
 
1939
 
 
1940
 
1329
1941
#define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1330
1942
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1331
1943
  .name = xname, \
1340
1952
{
1341
1953
        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1342
1954
        uinfo->count = 1;
 
1955
        uinfo->value.integer.min = 27000;
 
1956
        uinfo->value.integer.max = 207000;
 
1957
        uinfo->value.integer.step = 1;
1343
1958
        return 0;
1344
1959
}
1345
1960
 
 
1961
 
1346
1962
static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1347
1963
                                            struct snd_ctl_elem_value *
1348
1964
                                            ucontrol)
1349
1965
{
1350
1966
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1351
1967
 
1352
 
        ucontrol->value.enumerated.item[0] = hdspm->system_sample_rate;
1353
 
        return 0;
1354
 
}
 
1968
        ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
 
1969
        return 0;
 
1970
}
 
1971
 
 
1972
 
 
1973
/**
 
1974
 * Returns the WordClock sample rate class for the given card.
 
1975
 **/
 
1976
static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
 
1977
{
 
1978
        int status;
 
1979
 
 
1980
        switch (hdspm->io_type) {
 
1981
        case RayDAT:
 
1982
        case AIO:
 
1983
                status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
 
1984
                return (status >> 16) & 0xF;
 
1985
                break;
 
1986
        default:
 
1987
                break;
 
1988
        }
 
1989
 
 
1990
 
 
1991
        return 0;
 
1992
}
 
1993
 
 
1994
 
 
1995
/**
 
1996
 * Returns the TCO sample rate class for the given card.
 
1997
 **/
 
1998
static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
 
1999
{
 
2000
        int status;
 
2001
 
 
2002
        if (hdspm->tco) {
 
2003
                switch (hdspm->io_type) {
 
2004
                case RayDAT:
 
2005
                case AIO:
 
2006
                        status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
 
2007
                        return (status >> 20) & 0xF;
 
2008
                        break;
 
2009
                default:
 
2010
                        break;
 
2011
                }
 
2012
        }
 
2013
 
 
2014
        return 0;
 
2015
}
 
2016
 
 
2017
 
 
2018
/**
 
2019
 * Returns the SYNC_IN sample rate class for the given card.
 
2020
 **/
 
2021
static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
 
2022
{
 
2023
        int status;
 
2024
 
 
2025
        if (hdspm->tco) {
 
2026
                switch (hdspm->io_type) {
 
2027
                case RayDAT:
 
2028
                case AIO:
 
2029
                        status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
 
2030
                        return (status >> 12) & 0xF;
 
2031
                        break;
 
2032
                default:
 
2033
                        break;
 
2034
                }
 
2035
        }
 
2036
 
 
2037
        return 0;
 
2038
}
 
2039
 
 
2040
 
 
2041
/**
 
2042
 * Returns the sample rate class for input source <idx> for
 
2043
 * 'new style' cards like the AIO and RayDAT.
 
2044
 **/
 
2045
static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
 
2046
{
 
2047
        int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
 
2048
 
 
2049
        return (status >> (idx*4)) & 0xF;
 
2050
}
 
2051
 
 
2052
 
1355
2053
 
1356
2054
#define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1357
 
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1358
 
  .name = xname, \
1359
 
  .index = xindex, \
1360
 
  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1361
 
  .info = snd_hdspm_info_autosync_sample_rate, \
1362
 
  .get = snd_hdspm_get_autosync_sample_rate \
 
2055
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
2056
        .name = xname, \
 
2057
        .private_value = xindex, \
 
2058
        .access = SNDRV_CTL_ELEM_ACCESS_READ, \
 
2059
        .info = snd_hdspm_info_autosync_sample_rate, \
 
2060
        .get = snd_hdspm_get_autosync_sample_rate \
1363
2061
}
1364
2062
 
 
2063
 
1365
2064
static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1366
2065
                                               struct snd_ctl_elem_info *uinfo)
1367
2066
{
1368
 
        static char *texts[] = { "32000", "44100", "48000",
1369
 
                "64000", "88200", "96000",
1370
 
                "128000", "176400", "192000",
1371
 
                "None"
1372
 
        };
1373
2067
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1374
2068
        uinfo->count = 1;
1375
2069
        uinfo->value.enumerated.items = 10;
 
2070
 
1376
2071
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1377
 
                uinfo->value.enumerated.item =
1378
 
                    uinfo->value.enumerated.items - 1;
 
2072
                uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1379
2073
        strcpy(uinfo->value.enumerated.name,
1380
 
               texts[uinfo->value.enumerated.item]);
 
2074
                        texts_freq[uinfo->value.enumerated.item]);
1381
2075
        return 0;
1382
2076
}
1383
2077
 
 
2078
 
1384
2079
static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1385
2080
                                              struct snd_ctl_elem_value *
1386
2081
                                              ucontrol)
1387
2082
{
1388
2083
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1389
2084
 
1390
 
        switch (hdspm_external_sample_rate(hdspm)) {
1391
 
        case 32000:
1392
 
                ucontrol->value.enumerated.item[0] = 0;
1393
 
                break;
1394
 
        case 44100:
1395
 
                ucontrol->value.enumerated.item[0] = 1;
1396
 
                break;
1397
 
        case 48000:
1398
 
                ucontrol->value.enumerated.item[0] = 2;
1399
 
                break;
1400
 
        case 64000:
1401
 
                ucontrol->value.enumerated.item[0] = 3;
1402
 
                break;
1403
 
        case 88200:
1404
 
                ucontrol->value.enumerated.item[0] = 4;
1405
 
                break;
1406
 
        case 96000:
1407
 
                ucontrol->value.enumerated.item[0] = 5;
1408
 
                break;
1409
 
        case 128000:
1410
 
                ucontrol->value.enumerated.item[0] = 6;
1411
 
                break;
1412
 
        case 176400:
1413
 
                ucontrol->value.enumerated.item[0] = 7;
1414
 
                break;
1415
 
        case 192000:
1416
 
                ucontrol->value.enumerated.item[0] = 8;
1417
 
                break;
1418
 
 
 
2085
        switch (hdspm->io_type) {
 
2086
        case RayDAT:
 
2087
                switch (kcontrol->private_value) {
 
2088
                case 0:
 
2089
                        ucontrol->value.enumerated.item[0] =
 
2090
                                hdspm_get_wc_sample_rate(hdspm);
 
2091
                        break;
 
2092
                case 7:
 
2093
                        ucontrol->value.enumerated.item[0] =
 
2094
                                hdspm_get_tco_sample_rate(hdspm);
 
2095
                        break;
 
2096
                case 8:
 
2097
                        ucontrol->value.enumerated.item[0] =
 
2098
                                hdspm_get_sync_in_sample_rate(hdspm);
 
2099
                        break;
 
2100
                default:
 
2101
                        ucontrol->value.enumerated.item[0] =
 
2102
                                hdspm_get_s1_sample_rate(hdspm,
 
2103
                                                kcontrol->private_value-1);
 
2104
                }
 
2105
 
 
2106
        case AIO:
 
2107
                switch (kcontrol->private_value) {
 
2108
                case 0: /* WC */
 
2109
                        ucontrol->value.enumerated.item[0] =
 
2110
                                hdspm_get_wc_sample_rate(hdspm);
 
2111
                        break;
 
2112
                case 4: /* TCO */
 
2113
                        ucontrol->value.enumerated.item[0] =
 
2114
                                hdspm_get_tco_sample_rate(hdspm);
 
2115
                        break;
 
2116
                case 5: /* SYNC_IN */
 
2117
                        ucontrol->value.enumerated.item[0] =
 
2118
                                hdspm_get_sync_in_sample_rate(hdspm);
 
2119
                        break;
 
2120
                default:
 
2121
                        ucontrol->value.enumerated.item[0] =
 
2122
                                hdspm_get_s1_sample_rate(hdspm,
 
2123
                                                ucontrol->id.index-1);
 
2124
                }
 
2125
 
 
2126
        case AES32:
 
2127
 
 
2128
                switch (kcontrol->private_value) {
 
2129
                case 0: /* WC */
 
2130
                        ucontrol->value.enumerated.item[0] =
 
2131
                                hdspm_get_wc_sample_rate(hdspm);
 
2132
                        break;
 
2133
                case 9: /* TCO */
 
2134
                        ucontrol->value.enumerated.item[0] =
 
2135
                                hdspm_get_tco_sample_rate(hdspm);
 
2136
                        break;
 
2137
                case 10: /* SYNC_IN */
 
2138
                        ucontrol->value.enumerated.item[0] =
 
2139
                                hdspm_get_sync_in_sample_rate(hdspm);
 
2140
                        break;
 
2141
                default: /* AES1 to AES8 */
 
2142
                        ucontrol->value.enumerated.item[0] =
 
2143
                                hdspm_get_s1_sample_rate(hdspm,
 
2144
                                                kcontrol->private_value-1);
 
2145
                        break;
 
2146
 
 
2147
                }
1419
2148
        default:
1420
 
                ucontrol->value.enumerated.item[0] = 9;
 
2149
                break;
1421
2150
        }
 
2151
 
1422
2152
        return 0;
1423
2153
}
1424
2154
 
 
2155
 
1425
2156
#define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
1426
 
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1427
 
  .name = xname, \
1428
 
  .index = xindex, \
1429
 
  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1430
 
  .info = snd_hdspm_info_system_clock_mode, \
1431
 
  .get = snd_hdspm_get_system_clock_mode, \
 
2157
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
2158
        .name = xname, \
 
2159
        .index = xindex, \
 
2160
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
2161
                SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
2162
        .info = snd_hdspm_info_system_clock_mode, \
 
2163
        .get = snd_hdspm_get_system_clock_mode, \
 
2164
        .put = snd_hdspm_put_system_clock_mode, \
1432
2165
}
1433
2166
 
1434
2167
 
1435
 
 
1436
 
static int hdspm_system_clock_mode(struct hdspm * hdspm)
 
2168
/**
 
2169
 * Returns the system clock mode for the given card.
 
2170
 * @returns 0 - master, 1 - slave
 
2171
 **/
 
2172
static int hdspm_system_clock_mode(struct hdspm *hdspm)
1437
2173
{
1438
 
        /* Always reflect the hardware info, rme is never wrong !!!! */
1439
 
 
1440
 
        if (hdspm->control_register & HDSPM_ClockModeMaster)
1441
 
                return 0;
 
2174
        switch (hdspm->io_type) {
 
2175
        case AIO:
 
2176
        case RayDAT:
 
2177
                if (hdspm->settings_register & HDSPM_c0Master)
 
2178
                        return 0;
 
2179
                break;
 
2180
 
 
2181
        default:
 
2182
                if (hdspm->control_register & HDSPM_ClockModeMaster)
 
2183
                        return 0;
 
2184
        }
 
2185
 
1442
2186
        return 1;
1443
2187
}
1444
2188
 
 
2189
 
 
2190
/**
 
2191
 * Sets the system clock mode.
 
2192
 * @param mode 0 - master, 1 - slave
 
2193
 **/
 
2194
static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
 
2195
{
 
2196
        switch (hdspm->io_type) {
 
2197
        case AIO:
 
2198
        case RayDAT:
 
2199
                if (0 == mode)
 
2200
                        hdspm->settings_register |= HDSPM_c0Master;
 
2201
                else
 
2202
                        hdspm->settings_register &= ~HDSPM_c0Master;
 
2203
 
 
2204
                hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
 
2205
                break;
 
2206
 
 
2207
        default:
 
2208
                if (0 == mode)
 
2209
                        hdspm->control_register |= HDSPM_ClockModeMaster;
 
2210
                else
 
2211
                        hdspm->control_register &= ~HDSPM_ClockModeMaster;
 
2212
 
 
2213
                hdspm_write(hdspm, HDSPM_controlRegister,
 
2214
                                hdspm->control_register);
 
2215
        }
 
2216
}
 
2217
 
 
2218
 
1445
2219
static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
1446
2220
                                            struct snd_ctl_elem_info *uinfo)
1447
2221
{
1448
 
        static char *texts[] = { "Master", "Slave" };
 
2222
        static char *texts[] = { "Master", "AutoSync" };
1449
2223
 
1450
2224
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1451
2225
        uinfo->count = 1;
1463
2237
{
1464
2238
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1465
2239
 
1466
 
        ucontrol->value.enumerated.item[0] =
1467
 
            hdspm_system_clock_mode(hdspm);
1468
 
        return 0;
1469
 
}
1470
 
 
1471
 
#define HDSPM_CLOCK_SOURCE(xname, xindex) \
1472
 
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1473
 
  .name = xname, \
1474
 
  .index = xindex, \
1475
 
  .info = snd_hdspm_info_clock_source, \
1476
 
  .get = snd_hdspm_get_clock_source, \
1477
 
  .put = snd_hdspm_put_clock_source \
1478
 
}
 
2240
        ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
 
2241
        return 0;
 
2242
}
 
2243
 
 
2244
static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
 
2245
                                           struct snd_ctl_elem_value *ucontrol)
 
2246
{
 
2247
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
2248
        int val;
 
2249
 
 
2250
        if (!snd_hdspm_use_is_exclusive(hdspm))
 
2251
                return -EBUSY;
 
2252
 
 
2253
        val = ucontrol->value.enumerated.item[0];
 
2254
        if (val < 0)
 
2255
                val = 0;
 
2256
        else if (val > 1)
 
2257
                val = 1;
 
2258
 
 
2259
        hdspm_set_system_clock_mode(hdspm, val);
 
2260
 
 
2261
        return 0;
 
2262
}
 
2263
 
 
2264
 
 
2265
#define HDSPM_INTERNAL_CLOCK(xname, xindex) \
 
2266
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
2267
        .name = xname, \
 
2268
        .index = xindex, \
 
2269
        .info = snd_hdspm_info_clock_source, \
 
2270
        .get = snd_hdspm_get_clock_source, \
 
2271
        .put = snd_hdspm_put_clock_source \
 
2272
}
 
2273
 
1479
2274
 
1480
2275
static int hdspm_clock_source(struct hdspm * hdspm)
1481
2276
{
1482
 
        if (hdspm->control_register & HDSPM_ClockModeMaster) {
1483
 
                switch (hdspm->system_sample_rate) {
1484
 
                case 32000:
1485
 
                        return 1;
1486
 
                case 44100:
1487
 
                        return 2;
1488
 
                case 48000:
1489
 
                        return 3;
1490
 
                case 64000:
1491
 
                        return 4;
1492
 
                case 88200:
1493
 
                        return 5;
1494
 
                case 96000:
1495
 
                        return 6;
1496
 
                case 128000:
1497
 
                        return 7;
1498
 
                case 176400:
1499
 
                        return 8;
1500
 
                case 192000:
1501
 
                        return 9;
1502
 
                default:
1503
 
                        return 3;
1504
 
                }
1505
 
        } else {
1506
 
                return 0;
 
2277
        switch (hdspm->system_sample_rate) {
 
2278
        case 32000: return 0;
 
2279
        case 44100: return 1;
 
2280
        case 48000: return 2;
 
2281
        case 64000: return 3;
 
2282
        case 88200: return 4;
 
2283
        case 96000: return 5;
 
2284
        case 128000: return 6;
 
2285
        case 176400: return 7;
 
2286
        case 192000: return 8;
1507
2287
        }
 
2288
 
 
2289
        return -1;
1508
2290
}
1509
2291
 
1510
2292
static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
1511
2293
{
1512
2294
        int rate;
1513
2295
        switch (mode) {
1514
 
 
1515
 
        case HDSPM_CLOCK_SOURCE_AUTOSYNC:
1516
 
                if (hdspm_external_sample_rate(hdspm) != 0) {
1517
 
                        hdspm->control_register &= ~HDSPM_ClockModeMaster;
1518
 
                        hdspm_write(hdspm, HDSPM_controlRegister,
1519
 
                                    hdspm->control_register);
1520
 
                        return 0;
1521
 
                }
1522
 
                return -1;
1523
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
1524
 
                rate = 32000;
1525
 
                break;
1526
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1527
 
                rate = 44100;
1528
 
                break;
1529
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
 
2296
        case 0:
 
2297
                rate = 32000; break;
 
2298
        case 1:
 
2299
                rate = 44100; break;
 
2300
        case 2:
 
2301
                rate = 48000; break;
 
2302
        case 3:
 
2303
                rate = 64000; break;
 
2304
        case 4:
 
2305
                rate = 88200; break;
 
2306
        case 5:
 
2307
                rate = 96000; break;
 
2308
        case 6:
 
2309
                rate = 128000; break;
 
2310
        case 7:
 
2311
                rate = 176400; break;
 
2312
        case 8:
 
2313
                rate = 192000; break;
 
2314
        default:
1530
2315
                rate = 48000;
1531
 
                break;
1532
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
1533
 
                rate = 64000;
1534
 
                break;
1535
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1536
 
                rate = 88200;
1537
 
                break;
1538
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
1539
 
                rate = 96000;
1540
 
                break;
1541
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
1542
 
                rate = 128000;
1543
 
                break;
1544
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1545
 
                rate = 176400;
1546
 
                break;
1547
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
1548
 
                rate = 192000;
1549
 
                break;
1550
 
 
1551
 
        default:
1552
 
                rate = 44100;
1553
2316
        }
1554
 
        hdspm->control_register |= HDSPM_ClockModeMaster;
1555
 
        hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1556
2317
        hdspm_set_rate(hdspm, rate, 1);
1557
2318
        return 0;
1558
2319
}
1560
2321
static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
1561
2322
                                       struct snd_ctl_elem_info *uinfo)
1562
2323
{
1563
 
        static char *texts[] = { "AutoSync",
1564
 
                "Internal 32.0 kHz", "Internal 44.1 kHz",
1565
 
                    "Internal 48.0 kHz",
1566
 
                "Internal 64.0 kHz", "Internal 88.2 kHz",
1567
 
                    "Internal 96.0 kHz",
1568
 
                "Internal 128.0 kHz", "Internal 176.4 kHz",
1569
 
                    "Internal 192.0 kHz"
1570
 
        };
1571
 
 
1572
2324
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1573
2325
        uinfo->count = 1;
1574
 
        uinfo->value.enumerated.items = 10;
 
2326
        uinfo->value.enumerated.items = 9;
1575
2327
 
1576
2328
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1577
2329
                uinfo->value.enumerated.item =
1578
2330
                    uinfo->value.enumerated.items - 1;
1579
2331
 
1580
2332
        strcpy(uinfo->value.enumerated.name,
1581
 
               texts[uinfo->value.enumerated.item]);
 
2333
               texts_freq[uinfo->value.enumerated.item+1]);
1582
2334
 
1583
2335
        return 0;
1584
2336
}
1615
2367
        return change;
1616
2368
}
1617
2369
 
 
2370
 
1618
2371
#define HDSPM_PREF_SYNC_REF(xname, xindex) \
1619
 
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1620
 
  .name = xname, \
1621
 
  .index = xindex, \
1622
 
  .info = snd_hdspm_info_pref_sync_ref, \
1623
 
  .get = snd_hdspm_get_pref_sync_ref, \
1624
 
  .put = snd_hdspm_put_pref_sync_ref \
 
2372
{.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
2373
        .name = xname, \
 
2374
        .index = xindex, \
 
2375
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
2376
                        SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
2377
        .info = snd_hdspm_info_pref_sync_ref, \
 
2378
        .get = snd_hdspm_get_pref_sync_ref, \
 
2379
        .put = snd_hdspm_put_pref_sync_ref \
1625
2380
}
1626
2381
 
 
2382
 
 
2383
/**
 
2384
 * Returns the current preferred sync reference setting.
 
2385
 * The semantics of the return value are depending on the
 
2386
 * card, please see the comments for clarification.
 
2387
 **/
1627
2388
static int hdspm_pref_sync_ref(struct hdspm * hdspm)
1628
2389
{
1629
 
        /* Notice that this looks at the requested sync source,
1630
 
           not the one actually in use.
1631
 
         */
1632
 
        if (hdspm->is_aes32) {
1633
 
                switch (hdspm->control_register & HDSPM_SyncRefMask) {
1634
 
                /* number gives AES index, except for 0 which
1635
 
                   corresponds to WordClock */
1636
 
                case 0: return 0;
1637
 
                case HDSPM_SyncRef0: return 1;
1638
 
                case HDSPM_SyncRef1: return 2;
1639
 
                case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3;
1640
 
                case HDSPM_SyncRef2: return 4;
1641
 
                case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5;
1642
 
                case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6;
1643
 
                case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: return 7;
1644
 
                case HDSPM_SyncRef3: return 8;
1645
 
                }
1646
 
        } else {
1647
 
                switch (hdspm->control_register & HDSPM_SyncRefMask) {
1648
 
                case HDSPM_SyncRef_Word:
1649
 
                        return HDSPM_SYNC_FROM_WORD;
1650
 
                case HDSPM_SyncRef_MADI:
1651
 
                        return HDSPM_SYNC_FROM_MADI;
1652
 
                }
 
2390
        switch (hdspm->io_type) {
 
2391
        case AES32:
 
2392
                switch (hdspm->control_register & HDSPM_SyncRefMask) {
 
2393
                case 0: return 0;  /* WC */
 
2394
                case HDSPM_SyncRef0: return 1; /* AES 1 */
 
2395
                case HDSPM_SyncRef1: return 2; /* AES 2 */
 
2396
                case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
 
2397
                case HDSPM_SyncRef2: return 4; /* AES 4 */
 
2398
                case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
 
2399
                case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
 
2400
                case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
 
2401
                                                    return 7; /* AES 7 */
 
2402
                case HDSPM_SyncRef3: return 8; /* AES 8 */
 
2403
                case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
 
2404
                }
 
2405
                break;
 
2406
 
 
2407
        case MADI:
 
2408
        case MADIface:
 
2409
                if (hdspm->tco) {
 
2410
                        switch (hdspm->control_register & HDSPM_SyncRefMask) {
 
2411
                        case 0: return 0;  /* WC */
 
2412
                        case HDSPM_SyncRef0: return 1;  /* MADI */
 
2413
                        case HDSPM_SyncRef1: return 2;  /* TCO */
 
2414
                        case HDSPM_SyncRef1+HDSPM_SyncRef0:
 
2415
                                             return 3;  /* SYNC_IN */
 
2416
                        }
 
2417
                } else {
 
2418
                        switch (hdspm->control_register & HDSPM_SyncRefMask) {
 
2419
                        case 0: return 0;  /* WC */
 
2420
                        case HDSPM_SyncRef0: return 1;  /* MADI */
 
2421
                        case HDSPM_SyncRef1+HDSPM_SyncRef0:
 
2422
                                             return 2;  /* SYNC_IN */
 
2423
                        }
 
2424
                }
 
2425
                break;
 
2426
 
 
2427
        case RayDAT:
 
2428
                if (hdspm->tco) {
 
2429
                        switch ((hdspm->settings_register &
 
2430
                                HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
 
2431
                        case 0: return 0;  /* WC */
 
2432
                        case 3: return 1;  /* ADAT 1 */
 
2433
                        case 4: return 2;  /* ADAT 2 */
 
2434
                        case 5: return 3;  /* ADAT 3 */
 
2435
                        case 6: return 4;  /* ADAT 4 */
 
2436
                        case 1: return 5;  /* AES */
 
2437
                        case 2: return 6;  /* SPDIF */
 
2438
                        case 9: return 7;  /* TCO */
 
2439
                        case 10: return 8; /* SYNC_IN */
 
2440
                        }
 
2441
                } else {
 
2442
                        switch ((hdspm->settings_register &
 
2443
                                HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
 
2444
                        case 0: return 0;  /* WC */
 
2445
                        case 3: return 1;  /* ADAT 1 */
 
2446
                        case 4: return 2;  /* ADAT 2 */
 
2447
                        case 5: return 3;  /* ADAT 3 */
 
2448
                        case 6: return 4;  /* ADAT 4 */
 
2449
                        case 1: return 5;  /* AES */
 
2450
                        case 2: return 6;  /* SPDIF */
 
2451
                        case 10: return 7; /* SYNC_IN */
 
2452
                        }
 
2453
                }
 
2454
 
 
2455
                break;
 
2456
 
 
2457
        case AIO:
 
2458
                if (hdspm->tco) {
 
2459
                        switch ((hdspm->settings_register &
 
2460
                                HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
 
2461
                        case 0: return 0;  /* WC */
 
2462
                        case 3: return 1;  /* ADAT */
 
2463
                        case 1: return 2;  /* AES */
 
2464
                        case 2: return 3;  /* SPDIF */
 
2465
                        case 9: return 4;  /* TCO */
 
2466
                        case 10: return 5; /* SYNC_IN */
 
2467
                        }
 
2468
                } else {
 
2469
                        switch ((hdspm->settings_register &
 
2470
                                HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
 
2471
                        case 0: return 0;  /* WC */
 
2472
                        case 3: return 1;  /* ADAT */
 
2473
                        case 1: return 2;  /* AES */
 
2474
                        case 2: return 3;  /* SPDIF */
 
2475
                        case 10: return 4; /* SYNC_IN */
 
2476
                        }
 
2477
                }
 
2478
 
 
2479
                break;
1653
2480
        }
1654
2481
 
1655
 
        return HDSPM_SYNC_FROM_WORD;
 
2482
        return -1;
1656
2483
}
1657
2484
 
 
2485
 
 
2486
/**
 
2487
 * Set the preferred sync reference to <pref>. The semantics
 
2488
 * of <pref> are depending on the card type, see the comments
 
2489
 * for clarification.
 
2490
 **/
1658
2491
static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
1659
2492
{
1660
 
        hdspm->control_register &= ~HDSPM_SyncRefMask;
 
2493
        int p = 0;
1661
2494
 
1662
 
        if (hdspm->is_aes32) {
1663
 
                switch (pref) {
1664
 
                case 0:
1665
 
                       hdspm->control_register |= 0;
1666
 
                       break;
1667
 
                case 1:
1668
 
                       hdspm->control_register |= HDSPM_SyncRef0;
1669
 
                       break;
1670
 
                case 2:
1671
 
                       hdspm->control_register |= HDSPM_SyncRef1;
1672
 
                       break;
1673
 
                case 3:
1674
 
                       hdspm->control_register |= HDSPM_SyncRef1+HDSPM_SyncRef0;
1675
 
                       break;
1676
 
                case 4:
1677
 
                       hdspm->control_register |= HDSPM_SyncRef2;
1678
 
                       break;
1679
 
                case 5:
1680
 
                       hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef0;
1681
 
                       break;
1682
 
                case 6:
1683
 
                       hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1;
1684
 
                       break;
1685
 
                case 7:
1686
 
                       hdspm->control_register |=
1687
 
                               HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
1688
 
                       break;
1689
 
                case 8:
1690
 
                       hdspm->control_register |= HDSPM_SyncRef3;
1691
 
                       break;
1692
 
                default:
1693
 
                       return -1;
1694
 
                }
1695
 
        } else {
1696
 
                switch (pref) {
1697
 
                case HDSPM_SYNC_FROM_MADI:
1698
 
                        hdspm->control_register |= HDSPM_SyncRef_MADI;
1699
 
                        break;
1700
 
                case HDSPM_SYNC_FROM_WORD:
1701
 
                        hdspm->control_register |= HDSPM_SyncRef_Word;
 
2495
        switch (hdspm->io_type) {
 
2496
        case AES32:
 
2497
                hdspm->control_register &= ~HDSPM_SyncRefMask;
 
2498
                switch (pref) {
 
2499
                case 0: /* WC  */
 
2500
                        break;
 
2501
                case 1: /* AES 1 */
 
2502
                        hdspm->control_register |= HDSPM_SyncRef0;
 
2503
                        break;
 
2504
                case 2: /* AES 2 */
 
2505
                        hdspm->control_register |= HDSPM_SyncRef1;
 
2506
                        break;
 
2507
                case 3: /* AES 3 */
 
2508
                        hdspm->control_register |=
 
2509
                                HDSPM_SyncRef1+HDSPM_SyncRef0;
 
2510
                        break;
 
2511
                case 4: /* AES 4 */
 
2512
                        hdspm->control_register |= HDSPM_SyncRef2;
 
2513
                        break;
 
2514
                case 5: /* AES 5 */
 
2515
                        hdspm->control_register |=
 
2516
                                HDSPM_SyncRef2+HDSPM_SyncRef0;
 
2517
                        break;
 
2518
                case 6: /* AES 6 */
 
2519
                        hdspm->control_register |=
 
2520
                                HDSPM_SyncRef2+HDSPM_SyncRef1;
 
2521
                        break;
 
2522
                case 7: /* AES 7 */
 
2523
                        hdspm->control_register |=
 
2524
                                HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
 
2525
                        break;
 
2526
                case 8: /* AES 8 */
 
2527
                        hdspm->control_register |= HDSPM_SyncRef3;
 
2528
                        break;
 
2529
                case 9: /* TCO */
 
2530
                        hdspm->control_register |=
 
2531
                                HDSPM_SyncRef3+HDSPM_SyncRef0;
1702
2532
                        break;
1703
2533
                default:
1704
2534
                        return -1;
1705
2535
                }
1706
 
        }
1707
 
        hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
 
2536
 
 
2537
                break;
 
2538
 
 
2539
        case MADI:
 
2540
        case MADIface:
 
2541
                hdspm->control_register &= ~HDSPM_SyncRefMask;
 
2542
                if (hdspm->tco) {
 
2543
                        switch (pref) {
 
2544
                        case 0: /* WC */
 
2545
                                break;
 
2546
                        case 1: /* MADI */
 
2547
                                hdspm->control_register |= HDSPM_SyncRef0;
 
2548
                                break;
 
2549
                        case 2: /* TCO */
 
2550
                                hdspm->control_register |= HDSPM_SyncRef1;
 
2551
                                break;
 
2552
                        case 3: /* SYNC_IN */
 
2553
                                hdspm->control_register |=
 
2554
                                        HDSPM_SyncRef0+HDSPM_SyncRef1;
 
2555
                                break;
 
2556
                        default:
 
2557
                                return -1;
 
2558
                        }
 
2559
                } else {
 
2560
                        switch (pref) {
 
2561
                        case 0: /* WC */
 
2562
                                break;
 
2563
                        case 1: /* MADI */
 
2564
                                hdspm->control_register |= HDSPM_SyncRef0;
 
2565
                                break;
 
2566
                        case 2: /* SYNC_IN */
 
2567
                                hdspm->control_register |=
 
2568
                                        HDSPM_SyncRef0+HDSPM_SyncRef1;
 
2569
                                break;
 
2570
                        default:
 
2571
                                return -1;
 
2572
                        }
 
2573
                }
 
2574
 
 
2575
                break;
 
2576
 
 
2577
        case RayDAT:
 
2578
                if (hdspm->tco) {
 
2579
                        switch (pref) {
 
2580
                        case 0: p = 0; break;  /* WC */
 
2581
                        case 1: p = 3; break;  /* ADAT 1 */
 
2582
                        case 2: p = 4; break;  /* ADAT 2 */
 
2583
                        case 3: p = 5; break;  /* ADAT 3 */
 
2584
                        case 4: p = 6; break;  /* ADAT 4 */
 
2585
                        case 5: p = 1; break;  /* AES */
 
2586
                        case 6: p = 2; break;  /* SPDIF */
 
2587
                        case 7: p = 9; break;  /* TCO */
 
2588
                        case 8: p = 10; break; /* SYNC_IN */
 
2589
                        default: return -1;
 
2590
                        }
 
2591
                } else {
 
2592
                        switch (pref) {
 
2593
                        case 0: p = 0; break;  /* WC */
 
2594
                        case 1: p = 3; break;  /* ADAT 1 */
 
2595
                        case 2: p = 4; break;  /* ADAT 2 */
 
2596
                        case 3: p = 5; break;  /* ADAT 3 */
 
2597
                        case 4: p = 6; break;  /* ADAT 4 */
 
2598
                        case 5: p = 1; break;  /* AES */
 
2599
                        case 6: p = 2; break;  /* SPDIF */
 
2600
                        case 7: p = 10; break; /* SYNC_IN */
 
2601
                        default: return -1;
 
2602
                        }
 
2603
                }
 
2604
                break;
 
2605
 
 
2606
        case AIO:
 
2607
                if (hdspm->tco) {
 
2608
                        switch (pref) {
 
2609
                        case 0: p = 0; break;  /* WC */
 
2610
                        case 1: p = 3; break;  /* ADAT */
 
2611
                        case 2: p = 1; break;  /* AES */
 
2612
                        case 3: p = 2; break;  /* SPDIF */
 
2613
                        case 4: p = 9; break;  /* TCO */
 
2614
                        case 5: p = 10; break; /* SYNC_IN */
 
2615
                        default: return -1;
 
2616
                        }
 
2617
                } else {
 
2618
                        switch (pref) {
 
2619
                        case 0: p = 0; break;  /* WC */
 
2620
                        case 1: p = 3; break;  /* ADAT */
 
2621
                        case 2: p = 1; break;  /* AES */
 
2622
                        case 3: p = 2; break;  /* SPDIF */
 
2623
                        case 4: p = 10; break; /* SYNC_IN */
 
2624
                        default: return -1;
 
2625
                        }
 
2626
                }
 
2627
                break;
 
2628
        }
 
2629
 
 
2630
        switch (hdspm->io_type) {
 
2631
        case RayDAT:
 
2632
        case AIO:
 
2633
                hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
 
2634
                hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
 
2635
                hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
 
2636
                break;
 
2637
 
 
2638
        case MADI:
 
2639
        case MADIface:
 
2640
        case AES32:
 
2641
                hdspm_write(hdspm, HDSPM_controlRegister,
 
2642
                                hdspm->control_register);
 
2643
        }
 
2644
 
1708
2645
        return 0;
1709
2646
}
1710
2647
 
 
2648
 
1711
2649
static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
1712
2650
                                        struct snd_ctl_elem_info *uinfo)
1713
2651
{
1714
2652
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1715
2653
 
1716
 
        if (hdspm->is_aes32) {
1717
 
                static char *texts[] = { "Word", "AES1", "AES2", "AES3",
1718
 
                        "AES4", "AES5", "AES6", "AES7", "AES8" };
1719
 
 
1720
 
                uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1721
 
                uinfo->count = 1;
1722
 
 
1723
 
                uinfo->value.enumerated.items = 9;
1724
 
 
1725
 
                if (uinfo->value.enumerated.item >=
1726
 
                    uinfo->value.enumerated.items)
1727
 
                        uinfo->value.enumerated.item =
1728
 
                                uinfo->value.enumerated.items - 1;
1729
 
                strcpy(uinfo->value.enumerated.name,
1730
 
                                texts[uinfo->value.enumerated.item]);
1731
 
        } else {
1732
 
                static char *texts[] = { "Word", "MADI" };
1733
 
 
1734
 
                uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1735
 
                uinfo->count = 1;
1736
 
 
1737
 
                uinfo->value.enumerated.items = 2;
1738
 
 
1739
 
                if (uinfo->value.enumerated.item >=
1740
 
                    uinfo->value.enumerated.items)
1741
 
                        uinfo->value.enumerated.item =
1742
 
                                uinfo->value.enumerated.items - 1;
1743
 
                strcpy(uinfo->value.enumerated.name,
1744
 
                                texts[uinfo->value.enumerated.item]);
1745
 
        }
 
2654
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
 
2655
        uinfo->count = 1;
 
2656
        uinfo->value.enumerated.items = hdspm->texts_autosync_items;
 
2657
 
 
2658
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
 
2659
                uinfo->value.enumerated.item =
 
2660
                        uinfo->value.enumerated.items - 1;
 
2661
 
 
2662
        strcpy(uinfo->value.enumerated.name,
 
2663
                        hdspm->texts_autosync[uinfo->value.enumerated.item]);
 
2664
 
1746
2665
        return 0;
1747
2666
}
1748
2667
 
1750
2669
                                       struct snd_ctl_elem_value *ucontrol)
1751
2670
{
1752
2671
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1753
 
 
1754
 
        ucontrol->value.enumerated.item[0] = hdspm_pref_sync_ref(hdspm);
1755
 
        return 0;
 
2672
        int psf = hdspm_pref_sync_ref(hdspm);
 
2673
 
 
2674
        if (psf >= 0) {
 
2675
                ucontrol->value.enumerated.item[0] = psf;
 
2676
                return 0;
 
2677
        }
 
2678
 
 
2679
        return -1;
1756
2680
}
1757
2681
 
1758
2682
static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
1759
2683
                                       struct snd_ctl_elem_value *ucontrol)
1760
2684
{
1761
2685
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1762
 
        int change, max;
1763
 
        unsigned int val;
1764
 
 
1765
 
        max = hdspm->is_aes32 ? 9 : 2;
 
2686
        int val, change = 0;
1766
2687
 
1767
2688
        if (!snd_hdspm_use_is_exclusive(hdspm))
1768
2689
                return -EBUSY;
1769
2690
 
1770
 
        val = ucontrol->value.enumerated.item[0] % max;
 
2691
        val = ucontrol->value.enumerated.item[0];
 
2692
 
 
2693
        if (val < 0)
 
2694
                val = 0;
 
2695
        else if (val >= hdspm->texts_autosync_items)
 
2696
                val = hdspm->texts_autosync_items-1;
1771
2697
 
1772
2698
        spin_lock_irq(&hdspm->lock);
1773
 
        change = (int) val != hdspm_pref_sync_ref(hdspm);
1774
 
        hdspm_set_pref_sync_ref(hdspm, val);
 
2699
        if (val != hdspm_pref_sync_ref(hdspm))
 
2700
                change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
 
2701
 
1775
2702
        spin_unlock_irq(&hdspm->lock);
1776
2703
        return change;
1777
2704
}
1778
2705
 
 
2706
 
1779
2707
#define HDSPM_AUTOSYNC_REF(xname, xindex) \
1780
2708
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1781
2709
  .name = xname, \
1785
2713
  .get = snd_hdspm_get_autosync_ref, \
1786
2714
}
1787
2715
 
1788
 
static int hdspm_autosync_ref(struct hdspm * hdspm)
 
2716
static int hdspm_autosync_ref(struct hdspm *hdspm)
1789
2717
{
1790
 
        if (hdspm->is_aes32) {
 
2718
        if (AES32 == hdspm->io_type) {
1791
2719
                unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
1792
 
                unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) &
1793
 
                        0xF;
 
2720
                unsigned int syncref =
 
2721
                        (status >> HDSPM_AES32_syncref_bit) & 0xF;
1794
2722
                if (syncref == 0)
1795
2723
                        return HDSPM_AES32_AUTOSYNC_FROM_WORD;
1796
2724
                if (syncref <= 8)
1797
2725
                        return syncref;
1798
2726
                return HDSPM_AES32_AUTOSYNC_FROM_NONE;
1799
 
        } else {
 
2727
        } else if (MADI == hdspm->io_type) {
1800
2728
                /* This looks at the autosync selected sync reference */
1801
2729
                unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1802
2730
 
1805
2733
                        return HDSPM_AUTOSYNC_FROM_WORD;
1806
2734
                case HDSPM_SelSyncRef_MADI:
1807
2735
                        return HDSPM_AUTOSYNC_FROM_MADI;
 
2736
                case HDSPM_SelSyncRef_TCO:
 
2737
                        return HDSPM_AUTOSYNC_FROM_TCO;
 
2738
                case HDSPM_SelSyncRef_SyncIn:
 
2739
                        return HDSPM_AUTOSYNC_FROM_SYNC_IN;
1808
2740
                case HDSPM_SelSyncRef_NVALID:
1809
2741
                        return HDSPM_AUTOSYNC_FROM_NONE;
1810
2742
                default:
1811
2743
                        return 0;
1812
2744
                }
1813
2745
 
1814
 
                return 0;
1815
2746
        }
 
2747
        return 0;
1816
2748
}
1817
2749
 
 
2750
 
1818
2751
static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
1819
2752
                                       struct snd_ctl_elem_info *uinfo)
1820
2753
{
1821
2754
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1822
2755
 
1823
 
        if (hdspm->is_aes32) {
 
2756
        if (AES32 == hdspm->io_type) {
1824
2757
                static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
1825
2758
                        "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
1826
2759
 
1833
2766
                                uinfo->value.enumerated.items - 1;
1834
2767
                strcpy(uinfo->value.enumerated.name,
1835
2768
                                texts[uinfo->value.enumerated.item]);
1836
 
        } else {
1837
 
                static char *texts[] = { "WordClock", "MADI", "None" };
 
2769
        } else if (MADI == hdspm->io_type) {
 
2770
                static char *texts[] = {"Word Clock", "MADI", "TCO",
 
2771
                        "Sync In", "None" };
1838
2772
 
1839
2773
                uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1840
2774
                uinfo->count = 1;
1841
 
                uinfo->value.enumerated.items = 3;
 
2775
                uinfo->value.enumerated.items = 5;
1842
2776
                if (uinfo->value.enumerated.item >=
1843
 
                    uinfo->value.enumerated.items)
 
2777
                                uinfo->value.enumerated.items)
1844
2778
                        uinfo->value.enumerated.item =
1845
2779
                                uinfo->value.enumerated.items - 1;
1846
2780
                strcpy(uinfo->value.enumerated.name,
1858
2792
        return 0;
1859
2793
}
1860
2794
 
 
2795
 
1861
2796
#define HDSPM_LINE_OUT(xname, xindex) \
1862
2797
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1863
2798
  .name = xname, \
1914
2849
        return change;
1915
2850
}
1916
2851
 
 
2852
 
1917
2853
#define HDSPM_TX_64(xname, xindex) \
1918
2854
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1919
2855
  .name = xname, \
1969
2905
        return change;
1970
2906
}
1971
2907
 
 
2908
 
1972
2909
#define HDSPM_C_TMS(xname, xindex) \
1973
2910
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1974
2911
  .name = xname, \
2024
2961
        return change;
2025
2962
}
2026
2963
 
 
2964
 
2027
2965
#define HDSPM_SAFE_MODE(xname, xindex) \
2028
2966
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2029
2967
  .name = xname, \
2079
3017
        return change;
2080
3018
}
2081
3019
 
 
3020
 
2082
3021
#define HDSPM_EMPHASIS(xname, xindex) \
2083
3022
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2084
3023
  .name = xname, \
2134
3073
        return change;
2135
3074
}
2136
3075
 
 
3076
 
2137
3077
#define HDSPM_DOLBY(xname, xindex) \
2138
3078
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2139
3079
  .name = xname, \
2189
3129
        return change;
2190
3130
}
2191
3131
 
 
3132
 
2192
3133
#define HDSPM_PROFESSIONAL(xname, xindex) \
2193
3134
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2194
3135
  .name = xname, \
2315
3256
        return change;
2316
3257
}
2317
3258
 
 
3259
 
2318
3260
#define HDSPM_DS_WIRE(xname, xindex) \
2319
3261
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2320
3262
  .name = xname, \
2386
3328
        return change;
2387
3329
}
2388
3330
 
 
3331
 
2389
3332
#define HDSPM_QS_WIRE(xname, xindex) \
2390
3333
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2391
3334
  .name = xname, \
2472
3415
        return change;
2473
3416
}
2474
3417
 
2475
 
/*           Simple Mixer
2476
 
  deprecated since to much faders ???
2477
 
  MIXER interface says output (source, destination, value)
2478
 
   where source > MAX_channels are playback channels 
2479
 
   on MADICARD 
2480
 
  - playback mixer matrix: [channelout+64] [output] [value]
2481
 
  - input(thru) mixer matrix: [channelin] [output] [value]
2482
 
  (better do 2 kontrols for separation ?)
2483
 
*/
2484
3418
 
2485
3419
#define HDSPM_MIXER(xname, xindex) \
2486
3420
{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2586
3520
 
2587
3521
/* The simple mixer control(s) provide gain control for the
2588
3522
   basic 1:1 mappings of playback streams to output
2589
 
   streams. 
 
3523
   streams.
2590
3524
*/
2591
3525
 
2592
3526
#define HDSPM_PLAYBACK_MIXER \
2604
3538
        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2605
3539
        uinfo->count = 1;
2606
3540
        uinfo->value.integer.min = 0;
2607
 
        uinfo->value.integer.max = 65536;
 
3541
        uinfo->value.integer.max = 64;
2608
3542
        uinfo->value.integer.step = 1;
2609
3543
        return 0;
2610
3544
}
2614
3548
{
2615
3549
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2616
3550
        int channel;
2617
 
        int mapped_channel;
2618
3551
 
2619
3552
        channel = ucontrol->id.index - 1;
2620
3553
 
2621
3554
        if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
2622
3555
                return -EINVAL;
2623
3556
 
2624
 
        mapped_channel = hdspm->channel_map[channel];
2625
 
        if (mapped_channel < 0)
2626
 
                return -EINVAL;
2627
 
 
2628
3557
        spin_lock_irq(&hdspm->lock);
2629
3558
        ucontrol->value.integer.value[0] =
2630
 
            hdspm_read_pb_gain(hdspm, mapped_channel, mapped_channel);
 
3559
          (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
2631
3560
        spin_unlock_irq(&hdspm->lock);
2632
3561
 
2633
 
        /*
2634
 
        snd_printdd("get pb mixer index %d, channel %d, mapped_channel %d, "
2635
 
                    "value %d\n",
2636
 
                    ucontrol->id.index, channel, mapped_channel,
2637
 
                    ucontrol->value.integer.value[0]); 
2638
 
        */
2639
3562
        return 0;
2640
3563
}
2641
3564
 
2645
3568
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2646
3569
        int change;
2647
3570
        int channel;
2648
 
        int mapped_channel;
2649
3571
        int gain;
2650
3572
 
2651
3573
        if (!snd_hdspm_use_is_exclusive(hdspm))
2656
3578
        if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
2657
3579
                return -EINVAL;
2658
3580
 
2659
 
        mapped_channel = hdspm->channel_map[channel];
2660
 
        if (mapped_channel < 0)
2661
 
                return -EINVAL;
2662
 
 
2663
 
        gain = ucontrol->value.integer.value[0];
 
3581
        gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
2664
3582
 
2665
3583
        spin_lock_irq(&hdspm->lock);
2666
3584
        change =
2667
 
            gain != hdspm_read_pb_gain(hdspm, mapped_channel,
2668
 
                                       mapped_channel);
 
3585
            gain != hdspm_read_pb_gain(hdspm, channel,
 
3586
                                       channel);
2669
3587
        if (change)
2670
 
                hdspm_write_pb_gain(hdspm, mapped_channel, mapped_channel,
 
3588
                hdspm_write_pb_gain(hdspm, channel, channel,
2671
3589
                                    gain);
2672
3590
        spin_unlock_irq(&hdspm->lock);
2673
3591
        return change;
2674
3592
}
2675
3593
 
2676
 
#define HDSPM_WC_SYNC_CHECK(xname, xindex) \
2677
 
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2678
 
  .name = xname, \
2679
 
  .index = xindex, \
2680
 
  .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2681
 
  .info = snd_hdspm_info_sync_check, \
2682
 
  .get = snd_hdspm_get_wc_sync_check \
 
3594
#define HDSPM_SYNC_CHECK(xname, xindex) \
 
3595
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
3596
        .name = xname, \
 
3597
        .private_value = xindex, \
 
3598
        .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
3599
        .info = snd_hdspm_info_sync_check, \
 
3600
        .get = snd_hdspm_get_sync_check \
2683
3601
}
2684
3602
 
 
3603
 
2685
3604
static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
2686
3605
                                     struct snd_ctl_elem_info *uinfo)
2687
3606
{
2688
 
        static char *texts[] = { "No Lock", "Lock", "Sync" };
 
3607
        static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
2689
3608
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2690
3609
        uinfo->count = 1;
2691
 
        uinfo->value.enumerated.items = 3;
 
3610
        uinfo->value.enumerated.items = 4;
2692
3611
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2693
3612
                uinfo->value.enumerated.item =
2694
 
                    uinfo->value.enumerated.items - 1;
 
3613
                        uinfo->value.enumerated.items - 1;
2695
3614
        strcpy(uinfo->value.enumerated.name,
2696
 
               texts[uinfo->value.enumerated.item]);
 
3615
                        texts[uinfo->value.enumerated.item]);
2697
3616
        return 0;
2698
3617
}
2699
3618
 
2700
 
static int hdspm_wc_sync_check(struct hdspm * hdspm)
 
3619
static int hdspm_wc_sync_check(struct hdspm *hdspm)
2701
3620
{
2702
 
        if (hdspm->is_aes32) {
2703
 
                int status = hdspm_read(hdspm, HDSPM_statusRegister);
2704
 
                if (status & HDSPM_AES32_wcLock) {
2705
 
                        /* I don't know how to differenciate sync from lock.
2706
 
                           Doing as if sync for now */
 
3621
        int status, status2;
 
3622
 
 
3623
        switch (hdspm->io_type) {
 
3624
        case AES32:
 
3625
                status = hdspm_read(hdspm, HDSPM_statusRegister);
 
3626
                if (status & HDSPM_wcSync)
2707
3627
                        return 2;
2708
 
                }
 
3628
                else if (status & HDSPM_wcLock)
 
3629
                        return 1;
2709
3630
                return 0;
2710
 
        } else {
2711
 
                int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 
3631
                break;
 
3632
 
 
3633
        case MADI:
 
3634
                status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2712
3635
                if (status2 & HDSPM_wcLock) {
2713
3636
                        if (status2 & HDSPM_wcSync)
2714
3637
                                return 2;
2716
3639
                                return 1;
2717
3640
                }
2718
3641
                return 0;
 
3642
                break;
 
3643
 
 
3644
        case RayDAT:
 
3645
        case AIO:
 
3646
                status = hdspm_read(hdspm, HDSPM_statusRegister);
 
3647
 
 
3648
                if (status & 0x2000000)
 
3649
                        return 2;
 
3650
                else if (status & 0x1000000)
 
3651
                        return 1;
 
3652
                return 0;
 
3653
 
 
3654
                break;
 
3655
 
 
3656
        case MADIface:
 
3657
                break;
2719
3658
        }
2720
 
}
2721
 
 
2722
 
static int snd_hdspm_get_wc_sync_check(struct snd_kcontrol *kcontrol,
2723
 
                                       struct snd_ctl_elem_value *ucontrol)
2724
 
{
2725
 
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2726
 
 
2727
 
        ucontrol->value.enumerated.item[0] = hdspm_wc_sync_check(hdspm);
2728
 
        return 0;
2729
 
}
2730
 
 
2731
 
 
2732
 
#define HDSPM_MADI_SYNC_CHECK(xname, xindex) \
2733
 
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2734
 
  .name = xname, \
2735
 
  .index = xindex, \
2736
 
  .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2737
 
  .info = snd_hdspm_info_sync_check, \
2738
 
  .get = snd_hdspm_get_madisync_sync_check \
2739
 
}
2740
 
 
2741
 
static int hdspm_madisync_sync_check(struct hdspm * hdspm)
 
3659
 
 
3660
 
 
3661
        return 3;
 
3662
}
 
3663
 
 
3664
 
 
3665
static int hdspm_madi_sync_check(struct hdspm *hdspm)
2742
3666
{
2743
3667
        int status = hdspm_read(hdspm, HDSPM_statusRegister);
2744
3668
        if (status & HDSPM_madiLock) {
2750
3674
        return 0;
2751
3675
}
2752
3676
 
2753
 
static int snd_hdspm_get_madisync_sync_check(struct snd_kcontrol *kcontrol,
2754
 
                                             struct snd_ctl_elem_value *
2755
 
                                             ucontrol)
2756
 
{
2757
 
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2758
 
 
2759
 
        ucontrol->value.enumerated.item[0] =
2760
 
            hdspm_madisync_sync_check(hdspm);
2761
 
        return 0;
2762
 
}
2763
 
 
2764
 
 
2765
 
#define HDSPM_AES_SYNC_CHECK(xname, xindex) \
2766
 
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2767
 
  .name = xname, \
2768
 
  .index = xindex, \
2769
 
  .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2770
 
  .info = snd_hdspm_info_sync_check, \
2771
 
  .get = snd_hdspm_get_aes_sync_check \
2772
 
}
2773
 
 
2774
 
static int hdspm_aes_sync_check(struct hdspm * hdspm, int idx)
2775
 
{
2776
 
        int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2777
 
        if (status2 & (HDSPM_LockAES >> idx)) {
2778
 
                /* I don't know how to differenciate sync from lock.
2779
 
                   Doing as if sync for now */
2780
 
                return 2;
2781
 
        }
2782
 
        return 0;
2783
 
}
2784
 
 
2785
 
static int snd_hdspm_get_aes_sync_check(struct snd_kcontrol *kcontrol,
2786
 
                                        struct snd_ctl_elem_value *ucontrol)
2787
 
{
2788
 
        int offset;
2789
 
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2790
 
 
2791
 
        offset = ucontrol->id.index - 1;
2792
 
        if (offset < 0 || offset >= 8)
2793
 
                return -EINVAL;
2794
 
 
2795
 
        ucontrol->value.enumerated.item[0] =
2796
 
                hdspm_aes_sync_check(hdspm, offset);
2797
 
        return 0;
2798
 
}
 
3677
 
 
3678
static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
 
3679
{
 
3680
        int status, lock, sync;
 
3681
 
 
3682
        status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
 
3683
 
 
3684
        lock = (status & (0x1<<idx)) ? 1 : 0;
 
3685
        sync = (status & (0x100<<idx)) ? 1 : 0;
 
3686
 
 
3687
        if (lock && sync)
 
3688
                return 2;
 
3689
        else if (lock)
 
3690
                return 1;
 
3691
        return 0;
 
3692
}
 
3693
 
 
3694
 
 
3695
static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
 
3696
{
 
3697
        int status, lock = 0, sync = 0;
 
3698
 
 
3699
        switch (hdspm->io_type) {
 
3700
        case RayDAT:
 
3701
        case AIO:
 
3702
                status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
 
3703
                lock = (status & 0x400) ? 1 : 0;
 
3704
                sync = (status & 0x800) ? 1 : 0;
 
3705
                break;
 
3706
 
 
3707
        case MADI:
 
3708
        case AES32:
 
3709
                status = hdspm_read(hdspm, HDSPM_statusRegister2);
 
3710
                lock = (status & HDSPM_syncInLock) ? 1 : 0;
 
3711
                sync = (status & HDSPM_syncInSync) ? 1 : 0;
 
3712
                break;
 
3713
 
 
3714
        case MADIface:
 
3715
                break;
 
3716
        }
 
3717
 
 
3718
        if (lock && sync)
 
3719
                return 2;
 
3720
        else if (lock)
 
3721
                return 1;
 
3722
 
 
3723
        return 0;
 
3724
}
 
3725
 
 
3726
static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
 
3727
{
 
3728
        int status2, lock, sync;
 
3729
        status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 
3730
 
 
3731
        lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
 
3732
        sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
 
3733
 
 
3734
        if (sync)
 
3735
                return 2;
 
3736
        else if (lock)
 
3737
                return 1;
 
3738
        return 0;
 
3739
}
 
3740
 
 
3741
 
 
3742
static int hdspm_tco_sync_check(struct hdspm *hdspm)
 
3743
{
 
3744
        int status;
 
3745
 
 
3746
        if (hdspm->tco) {
 
3747
                switch (hdspm->io_type) {
 
3748
                case MADI:
 
3749
                case AES32:
 
3750
                        status = hdspm_read(hdspm, HDSPM_statusRegister);
 
3751
                        if (status & HDSPM_tcoLock) {
 
3752
                                if (status & HDSPM_tcoSync)
 
3753
                                        return 2;
 
3754
                                else
 
3755
                                        return 1;
 
3756
                        }
 
3757
                        return 0;
 
3758
 
 
3759
                        break;
 
3760
 
 
3761
                case RayDAT:
 
3762
                case AIO:
 
3763
                        status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
 
3764
 
 
3765
                        if (status & 0x8000000)
 
3766
                                return 2; /* Sync */
 
3767
                        if (status & 0x4000000)
 
3768
                                return 1; /* Lock */
 
3769
                        return 0; /* No signal */
 
3770
                        break;
 
3771
 
 
3772
                default:
 
3773
                        break;
 
3774
                }
 
3775
        }
 
3776
 
 
3777
        return 3; /* N/A */
 
3778
}
 
3779
 
 
3780
 
 
3781
static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
 
3782
                                    struct snd_ctl_elem_value *ucontrol)
 
3783
{
 
3784
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
3785
        int val = -1;
 
3786
 
 
3787
        switch (hdspm->io_type) {
 
3788
        case RayDAT:
 
3789
                switch (kcontrol->private_value) {
 
3790
                case 0: /* WC */
 
3791
                        val = hdspm_wc_sync_check(hdspm); break;
 
3792
                case 7: /* TCO */
 
3793
                        val = hdspm_tco_sync_check(hdspm); break;
 
3794
                case 8: /* SYNC IN */
 
3795
                        val = hdspm_sync_in_sync_check(hdspm); break;
 
3796
                default:
 
3797
                        val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
 
3798
                }
 
3799
 
 
3800
        case AIO:
 
3801
                switch (kcontrol->private_value) {
 
3802
                case 0: /* WC */
 
3803
                        val = hdspm_wc_sync_check(hdspm); break;
 
3804
                case 4: /* TCO */
 
3805
                        val = hdspm_tco_sync_check(hdspm); break;
 
3806
                case 5: /* SYNC IN */
 
3807
                        val = hdspm_sync_in_sync_check(hdspm); break;
 
3808
                default:
 
3809
                        val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
 
3810
                }
 
3811
 
 
3812
        case MADI:
 
3813
                switch (kcontrol->private_value) {
 
3814
                case 0: /* WC */
 
3815
                        val = hdspm_wc_sync_check(hdspm); break;
 
3816
                case 1: /* MADI */
 
3817
                        val = hdspm_madi_sync_check(hdspm); break;
 
3818
                case 2: /* TCO */
 
3819
                        val = hdspm_tco_sync_check(hdspm); break;
 
3820
                case 3: /* SYNC_IN */
 
3821
                        val = hdspm_sync_in_sync_check(hdspm); break;
 
3822
                }
 
3823
 
 
3824
        case MADIface:
 
3825
                val = hdspm_madi_sync_check(hdspm); /* MADI */
 
3826
                break;
 
3827
 
 
3828
        case AES32:
 
3829
                switch (kcontrol->private_value) {
 
3830
                case 0: /* WC */
 
3831
                        val = hdspm_wc_sync_check(hdspm); break;
 
3832
                case 9: /* TCO */
 
3833
                        val = hdspm_tco_sync_check(hdspm); break;
 
3834
                case 10 /* SYNC IN */:
 
3835
                        val = hdspm_sync_in_sync_check(hdspm); break;
 
3836
                default: /* AES1 to AES8 */
 
3837
                         val = hdspm_aes_sync_check(hdspm,
 
3838
                                         kcontrol->private_value-1);
 
3839
                }
 
3840
 
 
3841
        }
 
3842
 
 
3843
        if (-1 == val)
 
3844
                val = 3;
 
3845
 
 
3846
        ucontrol->value.enumerated.item[0] = val;
 
3847
        return 0;
 
3848
}
 
3849
 
 
3850
 
 
3851
 
 
3852
/**
 
3853
 * TCO controls
 
3854
 **/
 
3855
static void hdspm_tco_write(struct hdspm *hdspm)
 
3856
{
 
3857
        unsigned int tc[4] = { 0, 0, 0, 0};
 
3858
 
 
3859
        switch (hdspm->tco->input) {
 
3860
        case 0:
 
3861
                tc[2] |= HDSPM_TCO2_set_input_MSB;
 
3862
                break;
 
3863
        case 1:
 
3864
                tc[2] |= HDSPM_TCO2_set_input_LSB;
 
3865
                break;
 
3866
        default:
 
3867
                break;
 
3868
        }
 
3869
 
 
3870
        switch (hdspm->tco->framerate) {
 
3871
        case 1:
 
3872
                tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
 
3873
                break;
 
3874
        case 2:
 
3875
                tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
 
3876
                break;
 
3877
        case 3:
 
3878
                tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
 
3879
                        HDSPM_TCO1_set_drop_frame_flag;
 
3880
                break;
 
3881
        case 4:
 
3882
                tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
 
3883
                        HDSPM_TCO1_LTC_Format_MSB;
 
3884
                break;
 
3885
        case 5:
 
3886
                tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
 
3887
                        HDSPM_TCO1_LTC_Format_MSB +
 
3888
                        HDSPM_TCO1_set_drop_frame_flag;
 
3889
                break;
 
3890
        default:
 
3891
                break;
 
3892
        }
 
3893
 
 
3894
        switch (hdspm->tco->wordclock) {
 
3895
        case 1:
 
3896
                tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
 
3897
                break;
 
3898
        case 2:
 
3899
                tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
 
3900
                break;
 
3901
        default:
 
3902
                break;
 
3903
        }
 
3904
 
 
3905
        switch (hdspm->tco->samplerate) {
 
3906
        case 1:
 
3907
                tc[2] |= HDSPM_TCO2_set_freq;
 
3908
                break;
 
3909
        case 2:
 
3910
                tc[2] |= HDSPM_TCO2_set_freq_from_app;
 
3911
                break;
 
3912
        default:
 
3913
                break;
 
3914
        }
 
3915
 
 
3916
        switch (hdspm->tco->pull) {
 
3917
        case 1:
 
3918
                tc[2] |= HDSPM_TCO2_set_pull_up;
 
3919
                break;
 
3920
        case 2:
 
3921
                tc[2] |= HDSPM_TCO2_set_pull_down;
 
3922
                break;
 
3923
        case 3:
 
3924
                tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
 
3925
                break;
 
3926
        case 4:
 
3927
                tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
 
3928
                break;
 
3929
        default:
 
3930
                break;
 
3931
        }
 
3932
 
 
3933
        if (1 == hdspm->tco->term) {
 
3934
                tc[2] |= HDSPM_TCO2_set_term_75R;
 
3935
        }
 
3936
 
 
3937
        hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
 
3938
        hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
 
3939
        hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
 
3940
        hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
 
3941
}
 
3942
 
 
3943
 
 
3944
#define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
 
3945
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
3946
        .name = xname, \
 
3947
        .index = xindex, \
 
3948
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
3949
                SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
3950
        .info = snd_hdspm_info_tco_sample_rate, \
 
3951
        .get = snd_hdspm_get_tco_sample_rate, \
 
3952
        .put = snd_hdspm_put_tco_sample_rate \
 
3953
}
 
3954
 
 
3955
static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
 
3956
                                          struct snd_ctl_elem_info *uinfo)
 
3957
{
 
3958
        static char *texts[] = { "44.1 kHz", "48 kHz" };
 
3959
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
 
3960
        uinfo->count = 1;
 
3961
        uinfo->value.enumerated.items = 2;
 
3962
 
 
3963
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
 
3964
                uinfo->value.enumerated.item =
 
3965
                        uinfo->value.enumerated.items - 1;
 
3966
 
 
3967
        strcpy(uinfo->value.enumerated.name,
 
3968
                        texts[uinfo->value.enumerated.item]);
 
3969
 
 
3970
        return 0;
 
3971
}
 
3972
 
 
3973
static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
 
3974
                                      struct snd_ctl_elem_value *ucontrol)
 
3975
{
 
3976
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
3977
 
 
3978
        ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
 
3979
 
 
3980
        return 0;
 
3981
}
 
3982
 
 
3983
static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
 
3984
                                         struct snd_ctl_elem_value *ucontrol)
 
3985
{
 
3986
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
3987
 
 
3988
        if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
 
3989
                hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
 
3990
 
 
3991
                hdspm_tco_write(hdspm);
 
3992
 
 
3993
                return 1;
 
3994
        }
 
3995
 
 
3996
        return 0;
 
3997
}
 
3998
 
 
3999
 
 
4000
#define HDSPM_TCO_PULL(xname, xindex) \
 
4001
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
4002
        .name = xname, \
 
4003
        .index = xindex, \
 
4004
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
4005
                SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
4006
        .info = snd_hdspm_info_tco_pull, \
 
4007
        .get = snd_hdspm_get_tco_pull, \
 
4008
        .put = snd_hdspm_put_tco_pull \
 
4009
}
 
4010
 
 
4011
static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
 
4012
                                   struct snd_ctl_elem_info *uinfo)
 
4013
{
 
4014
        static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
 
4015
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
 
4016
        uinfo->count = 1;
 
4017
        uinfo->value.enumerated.items = 5;
 
4018
 
 
4019
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
 
4020
                uinfo->value.enumerated.item =
 
4021
                        uinfo->value.enumerated.items - 1;
 
4022
 
 
4023
        strcpy(uinfo->value.enumerated.name,
 
4024
                        texts[uinfo->value.enumerated.item]);
 
4025
 
 
4026
        return 0;
 
4027
}
 
4028
 
 
4029
static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
 
4030
                                  struct snd_ctl_elem_value *ucontrol)
 
4031
{
 
4032
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4033
 
 
4034
        ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
 
4035
 
 
4036
        return 0;
 
4037
}
 
4038
 
 
4039
static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
 
4040
                                  struct snd_ctl_elem_value *ucontrol)
 
4041
{
 
4042
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4043
 
 
4044
        if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
 
4045
                hdspm->tco->pull = ucontrol->value.enumerated.item[0];
 
4046
 
 
4047
                hdspm_tco_write(hdspm);
 
4048
 
 
4049
                return 1;
 
4050
        }
 
4051
 
 
4052
        return 0;
 
4053
}
 
4054
 
 
4055
#define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
 
4056
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
4057
        .name = xname, \
 
4058
        .index = xindex, \
 
4059
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
4060
                        SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
4061
        .info = snd_hdspm_info_tco_wck_conversion, \
 
4062
        .get = snd_hdspm_get_tco_wck_conversion, \
 
4063
        .put = snd_hdspm_put_tco_wck_conversion \
 
4064
}
 
4065
 
 
4066
static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
 
4067
                                             struct snd_ctl_elem_info *uinfo)
 
4068
{
 
4069
        static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
 
4070
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
 
4071
        uinfo->count = 1;
 
4072
        uinfo->value.enumerated.items = 3;
 
4073
 
 
4074
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
 
4075
                uinfo->value.enumerated.item =
 
4076
                        uinfo->value.enumerated.items - 1;
 
4077
 
 
4078
        strcpy(uinfo->value.enumerated.name,
 
4079
                        texts[uinfo->value.enumerated.item]);
 
4080
 
 
4081
        return 0;
 
4082
}
 
4083
 
 
4084
static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
 
4085
                                            struct snd_ctl_elem_value *ucontrol)
 
4086
{
 
4087
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4088
 
 
4089
        ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
 
4090
 
 
4091
        return 0;
 
4092
}
 
4093
 
 
4094
static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
 
4095
                                            struct snd_ctl_elem_value *ucontrol)
 
4096
{
 
4097
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4098
 
 
4099
        if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
 
4100
                hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
 
4101
 
 
4102
                hdspm_tco_write(hdspm);
 
4103
 
 
4104
                return 1;
 
4105
        }
 
4106
 
 
4107
        return 0;
 
4108
}
 
4109
 
 
4110
 
 
4111
#define HDSPM_TCO_FRAME_RATE(xname, xindex) \
 
4112
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
4113
        .name = xname, \
 
4114
        .index = xindex, \
 
4115
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
4116
                        SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
4117
        .info = snd_hdspm_info_tco_frame_rate, \
 
4118
        .get = snd_hdspm_get_tco_frame_rate, \
 
4119
        .put = snd_hdspm_put_tco_frame_rate \
 
4120
}
 
4121
 
 
4122
static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
 
4123
                                          struct snd_ctl_elem_info *uinfo)
 
4124
{
 
4125
        static char *texts[] = { "24 fps", "25 fps", "29.97fps",
 
4126
                "29.97 dfps", "30 fps", "30 dfps" };
 
4127
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
 
4128
        uinfo->count = 1;
 
4129
        uinfo->value.enumerated.items = 6;
 
4130
 
 
4131
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
 
4132
                uinfo->value.enumerated.item =
 
4133
                        uinfo->value.enumerated.items - 1;
 
4134
 
 
4135
        strcpy(uinfo->value.enumerated.name,
 
4136
                        texts[uinfo->value.enumerated.item]);
 
4137
 
 
4138
        return 0;
 
4139
}
 
4140
 
 
4141
static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
 
4142
                                        struct snd_ctl_elem_value *ucontrol)
 
4143
{
 
4144
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4145
 
 
4146
        ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
 
4147
 
 
4148
        return 0;
 
4149
}
 
4150
 
 
4151
static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
 
4152
                                        struct snd_ctl_elem_value *ucontrol)
 
4153
{
 
4154
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4155
 
 
4156
        if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
 
4157
                hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
 
4158
 
 
4159
                hdspm_tco_write(hdspm);
 
4160
 
 
4161
                return 1;
 
4162
        }
 
4163
 
 
4164
        return 0;
 
4165
}
 
4166
 
 
4167
 
 
4168
#define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
 
4169
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
4170
        .name = xname, \
 
4171
        .index = xindex, \
 
4172
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
4173
                        SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
4174
        .info = snd_hdspm_info_tco_sync_source, \
 
4175
        .get = snd_hdspm_get_tco_sync_source, \
 
4176
        .put = snd_hdspm_put_tco_sync_source \
 
4177
}
 
4178
 
 
4179
static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
 
4180
                                          struct snd_ctl_elem_info *uinfo)
 
4181
{
 
4182
        static char *texts[] = { "LTC", "Video", "WCK" };
 
4183
        uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
 
4184
        uinfo->count = 1;
 
4185
        uinfo->value.enumerated.items = 3;
 
4186
 
 
4187
        if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
 
4188
                uinfo->value.enumerated.item =
 
4189
                        uinfo->value.enumerated.items - 1;
 
4190
 
 
4191
        strcpy(uinfo->value.enumerated.name,
 
4192
                        texts[uinfo->value.enumerated.item]);
 
4193
 
 
4194
        return 0;
 
4195
}
 
4196
 
 
4197
static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
 
4198
                                         struct snd_ctl_elem_value *ucontrol)
 
4199
{
 
4200
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4201
 
 
4202
        ucontrol->value.enumerated.item[0] = hdspm->tco->input;
 
4203
 
 
4204
        return 0;
 
4205
}
 
4206
 
 
4207
static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
 
4208
                                         struct snd_ctl_elem_value *ucontrol)
 
4209
{
 
4210
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4211
 
 
4212
        if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
 
4213
                hdspm->tco->input = ucontrol->value.enumerated.item[0];
 
4214
 
 
4215
                hdspm_tco_write(hdspm);
 
4216
 
 
4217
                return 1;
 
4218
        }
 
4219
 
 
4220
        return 0;
 
4221
}
 
4222
 
 
4223
 
 
4224
#define HDSPM_TCO_WORD_TERM(xname, xindex) \
 
4225
{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
 
4226
        .name = xname, \
 
4227
        .index = xindex, \
 
4228
        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
 
4229
                        SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 
4230
        .info = snd_hdspm_info_tco_word_term, \
 
4231
        .get = snd_hdspm_get_tco_word_term, \
 
4232
        .put = snd_hdspm_put_tco_word_term \
 
4233
}
 
4234
 
 
4235
static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
 
4236
                                        struct snd_ctl_elem_info *uinfo)
 
4237
{
 
4238
        uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
 
4239
        uinfo->count = 1;
 
4240
        uinfo->value.integer.min = 0;
 
4241
        uinfo->value.integer.max = 1;
 
4242
 
 
4243
        return 0;
 
4244
}
 
4245
 
 
4246
 
 
4247
static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
 
4248
                                       struct snd_ctl_elem_value *ucontrol)
 
4249
{
 
4250
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4251
 
 
4252
        ucontrol->value.enumerated.item[0] = hdspm->tco->term;
 
4253
 
 
4254
        return 0;
 
4255
}
 
4256
 
 
4257
 
 
4258
static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
 
4259
                                       struct snd_ctl_elem_value *ucontrol)
 
4260
{
 
4261
        struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
 
4262
 
 
4263
        if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
 
4264
                hdspm->tco->term = ucontrol->value.enumerated.item[0];
 
4265
 
 
4266
                hdspm_tco_write(hdspm);
 
4267
 
 
4268
                return 1;
 
4269
        }
 
4270
 
 
4271
        return 0;
 
4272
}
 
4273
 
 
4274
 
2799
4275
 
2800
4276
 
2801
4277
static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
2802
 
 
2803
4278
        HDSPM_MIXER("Mixer", 0),
2804
 
/* 'Sample Clock Source' complies with the alsa control naming scheme */
2805
 
        HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2806
 
 
 
4279
        HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
2807
4280
        HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2808
4281
        HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2809
4282
        HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2810
4283
        HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2811
 
/* 'External Rate' complies with the alsa control naming scheme */
2812
 
        HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2813
 
        HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2814
 
        HDSPM_MADI_SYNC_CHECK("MADI Sync Lock Status", 0),
 
4284
        HDSPM_SYNC_CHECK("WC SyncCheck", 0),
 
4285
        HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
 
4286
        HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
 
4287
        HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
2815
4288
        HDSPM_LINE_OUT("Line Out", 0),
2816
4289
        HDSPM_TX_64("TX 64 channels mode", 0),
2817
4290
        HDSPM_C_TMS("Clear Track Marker", 0),
2818
4291
        HDSPM_SAFE_MODE("Safe Mode", 0),
2819
 
        HDSPM_INPUT_SELECT("Input Select", 0),
 
4292
        HDSPM_INPUT_SELECT("Input Select", 0)
 
4293
};
 
4294
 
 
4295
 
 
4296
static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
 
4297
        HDSPM_MIXER("Mixer", 0),
 
4298
        HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
 
4299
        HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
 
4300
        HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
 
4301
        HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
 
4302
        HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
 
4303
        HDSPM_TX_64("TX 64 channels mode", 0),
 
4304
        HDSPM_C_TMS("Clear Track Marker", 0),
 
4305
        HDSPM_SAFE_MODE("Safe Mode", 0)
 
4306
};
 
4307
 
 
4308
static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
 
4309
        HDSPM_MIXER("Mixer", 0),
 
4310
        HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
 
4311
        HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
 
4312
        HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
 
4313
        HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
 
4314
        HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
 
4315
        HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
 
4316
        HDSPM_SYNC_CHECK("WC SyncCheck", 0),
 
4317
        HDSPM_SYNC_CHECK("AES SyncCheck", 1),
 
4318
        HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
 
4319
        HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
 
4320
        HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
 
4321
        HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
 
4322
        HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
 
4323
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
 
4324
        HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
 
4325
        HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
 
4326
        HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
 
4327
        HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
 
4328
 
 
4329
                /*
 
4330
                   HDSPM_INPUT_SELECT("Input Select", 0),
 
4331
                   HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
 
4332
                   HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
 
4333
                   HDSPM_SPDIF_IN("SPDIF In", 0);
 
4334
                   HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
 
4335
                   HDSPM_INPUT_LEVEL("Input Level", 0);
 
4336
                   HDSPM_OUTPUT_LEVEL("Output Level", 0);
 
4337
                   HDSPM_PHONES("Phones", 0);
 
4338
                   */
 
4339
};
 
4340
 
 
4341
static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
 
4342
        HDSPM_MIXER("Mixer", 0),
 
4343
        HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
 
4344
        HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
 
4345
        HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
 
4346
        HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
 
4347
        HDSPM_SYNC_CHECK("WC SyncCheck", 0),
 
4348
        HDSPM_SYNC_CHECK("AES SyncCheck", 1),
 
4349
        HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
 
4350
        HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
 
4351
        HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
 
4352
        HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
 
4353
        HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
 
4354
        HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
 
4355
        HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
 
4356
        HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
 
4357
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
 
4358
        HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
 
4359
        HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
 
4360
        HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
 
4361
        HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
 
4362
        HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
 
4363
        HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
 
4364
        HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
2820
4365
};
2821
4366
 
2822
4367
static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
2823
 
 
2824
4368
        HDSPM_MIXER("Mixer", 0),
2825
 
/* 'Sample Clock Source' complies with the alsa control naming scheme */
2826
 
        HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2827
 
 
 
4369
        HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
2828
4370
        HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2829
4371
        HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2830
4372
        HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2831
4373
        HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2832
 
/* 'External Rate' complies with the alsa control naming scheme */
2833
4374
        HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2834
 
        HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2835
 
/*      HDSPM_AES_SYNC_CHECK("AES Lock Status", 0),*/ /* created in snd_hdspm_create_controls() */
 
4375
        HDSPM_SYNC_CHECK("WC Sync Check", 0),
 
4376
        HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
 
4377
        HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
 
4378
        HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
 
4379
        HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
 
4380
        HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
 
4381
        HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
 
4382
        HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
 
4383
        HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
 
4384
        HDSPM_SYNC_CHECK("TCO Sync Check", 9),
 
4385
        HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
 
4386
        HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
 
4387
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
 
4388
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
 
4389
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
 
4390
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
 
4391
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
 
4392
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
 
4393
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
 
4394
        HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
 
4395
        HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
 
4396
        HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
2836
4397
        HDSPM_LINE_OUT("Line Out", 0),
2837
4398
        HDSPM_EMPHASIS("Emphasis", 0),
2838
4399
        HDSPM_DOLBY("Non Audio", 0),
2842
4403
        HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
2843
4404
};
2844
4405
 
 
4406
 
 
4407
 
 
4408
/* Control elements for the optional TCO module */
 
4409
static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
 
4410
        HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
 
4411
        HDSPM_TCO_PULL("TCO Pull", 0),
 
4412
        HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
 
4413
        HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
 
4414
        HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
 
4415
        HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
 
4416
};
 
4417
 
 
4418
 
2845
4419
static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
2846
4420
 
2847
4421
 
2849
4423
{
2850
4424
        int i;
2851
4425
 
2852
 
        for (i = hdspm->ds_channels; i < hdspm->ss_channels; ++i) {
 
4426
        for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
2853
4427
                if (hdspm->system_sample_rate > 48000) {
2854
4428
                        hdspm->playback_mixer_ctls[i]->vd[0].access =
2855
 
                            SNDRV_CTL_ELEM_ACCESS_INACTIVE |
2856
 
                            SNDRV_CTL_ELEM_ACCESS_READ |
2857
 
                            SNDRV_CTL_ELEM_ACCESS_VOLATILE;
 
4429
                                SNDRV_CTL_ELEM_ACCESS_INACTIVE |
 
4430
                                SNDRV_CTL_ELEM_ACCESS_READ |
 
4431
                                SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2858
4432
                } else {
2859
4433
                        hdspm->playback_mixer_ctls[i]->vd[0].access =
2860
 
                            SNDRV_CTL_ELEM_ACCESS_READWRITE |
2861
 
                            SNDRV_CTL_ELEM_ACCESS_VOLATILE;
 
4434
                                SNDRV_CTL_ELEM_ACCESS_READWRITE |
 
4435
                                SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2862
4436
                }
2863
4437
                snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
2864
 
                               SNDRV_CTL_EVENT_MASK_INFO,
2865
 
                               &hdspm->playback_mixer_ctls[i]->id);
 
4438
                                SNDRV_CTL_EVENT_MASK_INFO,
 
4439
                                &hdspm->playback_mixer_ctls[i]->id);
2866
4440
        }
2867
4441
 
2868
4442
        return 0;
2869
4443
}
2870
4444
 
2871
4445
 
2872
 
static int snd_hdspm_create_controls(struct snd_card *card, struct hdspm * hdspm)
 
4446
static int snd_hdspm_create_controls(struct snd_card *card,
 
4447
                                        struct hdspm *hdspm)
2873
4448
{
2874
4449
        unsigned int idx, limit;
2875
4450
        int err;
2876
4451
        struct snd_kcontrol *kctl;
2877
 
 
2878
 
        /* add control list first */
2879
 
        if (hdspm->is_aes32) {
2880
 
                struct snd_kcontrol_new aes_sync_ctl =
2881
 
                        HDSPM_AES_SYNC_CHECK("AES Lock Status", 0);
2882
 
 
2883
 
                for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_aes32);
2884
 
                     idx++) {
2885
 
                        err = snd_ctl_add(card,
2886
 
                                          snd_ctl_new1(&snd_hdspm_controls_aes32[idx],
2887
 
                                                       hdspm));
2888
 
                        if (err < 0)
2889
 
                                return err;
2890
 
                }
2891
 
                for (idx = 1; idx <= 8; idx++) {
2892
 
                        aes_sync_ctl.index = idx;
2893
 
                        err = snd_ctl_add(card,
2894
 
                                          snd_ctl_new1(&aes_sync_ctl, hdspm));
2895
 
                        if (err < 0)
2896
 
                                return err;
2897
 
                }
2898
 
        } else {
2899
 
                for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_madi);
2900
 
                     idx++) {
2901
 
                        err = snd_ctl_add(card,
2902
 
                                          snd_ctl_new1(&snd_hdspm_controls_madi[idx],
2903
 
                                                       hdspm));
2904
 
                        if (err < 0)
2905
 
                                return err;
2906
 
                }
2907
 
        }
2908
 
 
2909
 
        /* Channel playback mixer as default control 
2910
 
           Note: the whole matrix would be 128*HDSPM_MIXER_CHANNELS Faders,
2911
 
           thats too * big for any alsamixer they are accessible via special
2912
 
           IOCTL on hwdep and the mixer 2dimensional mixer control
2913
 
        */
2914
 
 
 
4452
        struct snd_kcontrol_new *list = NULL;
 
4453
 
 
4454
        switch (hdspm->io_type) {
 
4455
        case MADI:
 
4456
                list = snd_hdspm_controls_madi;
 
4457
                limit = ARRAY_SIZE(snd_hdspm_controls_madi);
 
4458
                break;
 
4459
        case MADIface:
 
4460
                list = snd_hdspm_controls_madiface;
 
4461
                limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
 
4462
                break;
 
4463
        case AIO:
 
4464
                list = snd_hdspm_controls_aio;
 
4465
                limit = ARRAY_SIZE(snd_hdspm_controls_aio);
 
4466
                break;
 
4467
        case RayDAT:
 
4468
                list = snd_hdspm_controls_raydat;
 
4469
                limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
 
4470
                break;
 
4471
        case AES32:
 
4472
                list = snd_hdspm_controls_aes32;
 
4473
                limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
 
4474
                break;
 
4475
        }
 
4476
 
 
4477
        if (NULL != list) {
 
4478
                for (idx = 0; idx < limit; idx++) {
 
4479
                        err = snd_ctl_add(card,
 
4480
                                        snd_ctl_new1(&list[idx], hdspm));
 
4481
                        if (err < 0)
 
4482
                                return err;
 
4483
                }
 
4484
        }
 
4485
 
 
4486
 
 
4487
        /* create simple 1:1 playback mixer controls */
2915
4488
        snd_hdspm_playback_mixer.name = "Chn";
2916
 
        limit = HDSPM_MAX_CHANNELS;
2917
 
 
2918
 
        /* The index values are one greater than the channel ID so that
2919
 
         * alsamixer will display them correctly. We want to use the index
2920
 
         * for fast lookup of the relevant channel, but if we use it at all,
2921
 
         * most ALSA software does the wrong thing with it ...
2922
 
         */
2923
 
 
 
4489
        if (hdspm->system_sample_rate >= 128000) {
 
4490
                limit = hdspm->qs_out_channels;
 
4491
        } else if (hdspm->system_sample_rate >= 64000) {
 
4492
                limit = hdspm->ds_out_channels;
 
4493
        } else {
 
4494
                limit = hdspm->ss_out_channels;
 
4495
        }
2924
4496
        for (idx = 0; idx < limit; ++idx) {
2925
4497
                snd_hdspm_playback_mixer.index = idx + 1;
2926
4498
                kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
2930
4502
                hdspm->playback_mixer_ctls[idx] = kctl;
2931
4503
        }
2932
4504
 
 
4505
 
 
4506
        if (hdspm->tco) {
 
4507
                /* add tco control elements */
 
4508
                list = snd_hdspm_controls_tco;
 
4509
                limit = ARRAY_SIZE(snd_hdspm_controls_tco);
 
4510
                for (idx = 0; idx < limit; idx++) {
 
4511
                        err = snd_ctl_add(card,
 
4512
                                        snd_ctl_new1(&list[idx], hdspm));
 
4513
                        if (err < 0)
 
4514
                                return err;
 
4515
                }
 
4516
        }
 
4517
 
2933
4518
        return 0;
2934
4519
}
2935
4520
 
2936
4521
/*------------------------------------------------------------
2937
 
   /proc interface 
 
4522
   /proc interface
2938
4523
 ------------------------------------------------------------*/
2939
4524
 
2940
4525
static void
2942
4527
                         struct snd_info_buffer *buffer)
2943
4528
{
2944
4529
        struct hdspm *hdspm = entry->private_data;
2945
 
        unsigned int status;
2946
 
        unsigned int status2;
 
4530
        unsigned int status, status2, control, freq;
 
4531
 
2947
4532
        char *pref_sync_ref;
2948
4533
        char *autosync_ref;
2949
4534
        char *system_clock_mode;
2950
 
        char *clock_source;
2951
4535
        char *insel;
2952
 
        char *syncref;
2953
4536
        int x, x2;
2954
4537
 
 
4538
        /* TCO stuff */
 
4539
        int a, ltc, frames, seconds, minutes, hours;
 
4540
        unsigned int period;
 
4541
        u64 freq_const = 0;
 
4542
        u32 rate;
 
4543
 
2955
4544
        status = hdspm_read(hdspm, HDSPM_statusRegister);
2956
4545
        status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 
4546
        control = hdspm->control_register;
 
4547
        freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
2957
4548
 
2958
4549
        snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
2959
 
                    hdspm->card_name, hdspm->card->number + 1,
2960
 
                    hdspm->firmware_rev,
2961
 
                    (status2 & HDSPM_version0) |
2962
 
                    (status2 & HDSPM_version1) | (status2 &
2963
 
                                                  HDSPM_version2));
 
4550
                        hdspm->card_name, hdspm->card->number + 1,
 
4551
                        hdspm->firmware_rev,
 
4552
                        (status2 & HDSPM_version0) |
 
4553
                        (status2 & HDSPM_version1) | (status2 &
 
4554
                                HDSPM_version2));
 
4555
 
 
4556
        snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
 
4557
                        (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
 
4558
                        (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
2964
4559
 
2965
4560
        snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
2966
 
                    hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
 
4561
                        hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
2967
4562
 
2968
4563
        snd_iprintf(buffer, "--- System ---\n");
2969
4564
 
2970
4565
        snd_iprintf(buffer,
2971
 
                    "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
2972
 
                    status & HDSPM_audioIRQPending,
2973
 
                    (status & HDSPM_midi0IRQPending) ? 1 : 0,
2974
 
                    (status & HDSPM_midi1IRQPending) ? 1 : 0,
2975
 
                    hdspm->irq_count);
2976
 
        snd_iprintf(buffer,
2977
 
                    "HW pointer: id = %d, rawptr = %d (%d->%d) "
2978
 
                    "estimated= %ld (bytes)\n",
2979
 
                    ((status & HDSPM_BufferID) ? 1 : 0),
2980
 
                    (status & HDSPM_BufferPositionMask),
2981
 
                    (status & HDSPM_BufferPositionMask) %
2982
 
                    (2 * (int)hdspm->period_bytes),
2983
 
                    ((status & HDSPM_BufferPositionMask) - 64) %
2984
 
                    (2 * (int)hdspm->period_bytes),
2985
 
                    (long) hdspm_hw_pointer(hdspm) * 4);
2986
 
 
2987
 
        snd_iprintf(buffer,
2988
 
                    "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
2989
 
                    hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
2990
 
                    hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
2991
 
                    hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
2992
 
                    hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
2993
 
        snd_iprintf(buffer,
2994
 
                    "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
2995
 
                    "status2=0x%x\n",
2996
 
                    hdspm->control_register, hdspm->control2_register,
2997
 
                    status, status2);
 
4566
                "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
 
4567
                status & HDSPM_audioIRQPending,
 
4568
                (status & HDSPM_midi0IRQPending) ? 1 : 0,
 
4569
                (status & HDSPM_midi1IRQPending) ? 1 : 0,
 
4570
                hdspm->irq_count);
 
4571
        snd_iprintf(buffer,
 
4572
                "HW pointer: id = %d, rawptr = %d (%d->%d) "
 
4573
                "estimated= %ld (bytes)\n",
 
4574
                ((status & HDSPM_BufferID) ? 1 : 0),
 
4575
                (status & HDSPM_BufferPositionMask),
 
4576
                (status & HDSPM_BufferPositionMask) %
 
4577
                (2 * (int)hdspm->period_bytes),
 
4578
                ((status & HDSPM_BufferPositionMask) - 64) %
 
4579
                (2 * (int)hdspm->period_bytes),
 
4580
                (long) hdspm_hw_pointer(hdspm) * 4);
 
4581
 
 
4582
        snd_iprintf(buffer,
 
4583
                "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
 
4584
                hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
 
4585
                hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
 
4586
                hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
 
4587
                hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
 
4588
        snd_iprintf(buffer,
 
4589
                "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
 
4590
                hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
 
4591
                hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
 
4592
        snd_iprintf(buffer,
 
4593
                "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
 
4594
                "status2=0x%x\n",
 
4595
                hdspm->control_register, hdspm->control2_register,
 
4596
                status, status2);
 
4597
        if (status & HDSPM_tco_detect) {
 
4598
                snd_iprintf(buffer, "TCO module detected.\n");
 
4599
                a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
 
4600
                if (a & HDSPM_TCO1_LTC_Input_valid) {
 
4601
                        snd_iprintf(buffer, "  LTC valid, ");
 
4602
                        switch (a & (HDSPM_TCO1_LTC_Format_LSB |
 
4603
                                                HDSPM_TCO1_LTC_Format_MSB)) {
 
4604
                        case 0:
 
4605
                                snd_iprintf(buffer, "24 fps, ");
 
4606
                                break;
 
4607
                        case HDSPM_TCO1_LTC_Format_LSB:
 
4608
                                snd_iprintf(buffer, "25 fps, ");
 
4609
                                break;
 
4610
                        case HDSPM_TCO1_LTC_Format_MSB:
 
4611
                                snd_iprintf(buffer, "29.97 fps, ");
 
4612
                                break;
 
4613
                        default:
 
4614
                                snd_iprintf(buffer, "30 fps, ");
 
4615
                                break;
 
4616
                        }
 
4617
                        if (a & HDSPM_TCO1_set_drop_frame_flag) {
 
4618
                                snd_iprintf(buffer, "drop frame\n");
 
4619
                        } else {
 
4620
                                snd_iprintf(buffer, "full frame\n");
 
4621
                        }
 
4622
                } else {
 
4623
                        snd_iprintf(buffer, "  no LTC\n");
 
4624
                }
 
4625
                if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
 
4626
                        snd_iprintf(buffer, "  Video: NTSC\n");
 
4627
                } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
 
4628
                        snd_iprintf(buffer, "  Video: PAL\n");
 
4629
                } else {
 
4630
                        snd_iprintf(buffer, "  No video\n");
 
4631
                }
 
4632
                if (a & HDSPM_TCO1_TCO_lock) {
 
4633
                        snd_iprintf(buffer, "  Sync: lock\n");
 
4634
                } else {
 
4635
                        snd_iprintf(buffer, "  Sync: no lock\n");
 
4636
                }
 
4637
 
 
4638
                switch (hdspm->io_type) {
 
4639
                case MADI:
 
4640
                case AES32:
 
4641
                        freq_const = 110069313433624ULL;
 
4642
                        break;
 
4643
                case RayDAT:
 
4644
                case AIO:
 
4645
                        freq_const = 104857600000000ULL;
 
4646
                        break;
 
4647
                case MADIface:
 
4648
                        break; /* no TCO possible */
 
4649
                }
 
4650
 
 
4651
                period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
 
4652
                snd_iprintf(buffer, "    period: %u\n", period);
 
4653
 
 
4654
 
 
4655
                /* rate = freq_const/period; */
 
4656
                rate = div_u64(freq_const, period);
 
4657
 
 
4658
                if (control & HDSPM_QuadSpeed) {
 
4659
                        rate *= 4;
 
4660
                } else if (control & HDSPM_DoubleSpeed) {
 
4661
                        rate *= 2;
 
4662
                }
 
4663
 
 
4664
                snd_iprintf(buffer, "  Frequency: %u Hz\n",
 
4665
                                (unsigned int) rate);
 
4666
 
 
4667
                ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
 
4668
                frames = ltc & 0xF;
 
4669
                ltc >>= 4;
 
4670
                frames += (ltc & 0x3) * 10;
 
4671
                ltc >>= 4;
 
4672
                seconds = ltc & 0xF;
 
4673
                ltc >>= 4;
 
4674
                seconds += (ltc & 0x7) * 10;
 
4675
                ltc >>= 4;
 
4676
                minutes = ltc & 0xF;
 
4677
                ltc >>= 4;
 
4678
                minutes += (ltc & 0x7) * 10;
 
4679
                ltc >>= 4;
 
4680
                hours = ltc & 0xF;
 
4681
                ltc >>= 4;
 
4682
                hours += (ltc & 0x3) * 10;
 
4683
                snd_iprintf(buffer,
 
4684
                        "  LTC In: %02d:%02d:%02d:%02d\n",
 
4685
                        hours, minutes, seconds, frames);
 
4686
 
 
4687
        } else {
 
4688
                snd_iprintf(buffer, "No TCO module detected.\n");
 
4689
        }
2998
4690
 
2999
4691
        snd_iprintf(buffer, "--- Settings ---\n");
3000
4692
 
3001
4693
        x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
3002
 
                                           HDSPM_LatencyMask));
 
4694
                                                        HDSPM_LatencyMask));
3003
4695
 
3004
4696
        snd_iprintf(buffer,
3005
 
                    "Size (Latency): %d samples (2 periods of %lu bytes)\n",
3006
 
                    x, (unsigned long) hdspm->period_bytes);
 
4697
                "Size (Latency): %d samples (2 periods of %lu bytes)\n",
 
4698
                x, (unsigned long) hdspm->period_bytes);
3007
4699
 
3008
 
        snd_iprintf(buffer, "Line out: %s,   Precise Pointer: %s\n",
3009
 
                    (hdspm->control_register & HDSPM_LineOut) ? "on " : "off",
3010
 
                    (hdspm->precise_ptr) ? "on" : "off");
 
4700
        snd_iprintf(buffer, "Line out: %s\n",
 
4701
                (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
3011
4702
 
3012
4703
        switch (hdspm->control_register & HDSPM_InputMask) {
3013
4704
        case HDSPM_InputOptical:
3017
4708
                insel = "Coaxial";
3018
4709
                break;
3019
4710
        default:
3020
 
                insel = "Unknown";
3021
 
        }
3022
 
 
3023
 
        switch (hdspm->control_register & HDSPM_SyncRefMask) {
3024
 
        case HDSPM_SyncRef_Word:
3025
 
                syncref = "WordClock";
3026
 
                break;
3027
 
        case HDSPM_SyncRef_MADI:
3028
 
                syncref = "MADI";
3029
 
                break;
3030
 
        default:
3031
 
                syncref = "Unknown";
3032
 
        }
3033
 
        snd_iprintf(buffer, "Inputsel = %s, SyncRef = %s\n", insel,
3034
 
                    syncref);
 
4711
                insel = "Unkown";
 
4712
        }
3035
4713
 
3036
4714
        snd_iprintf(buffer,
3037
 
                    "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
3038
 
                    "Auto Input %s\n",
3039
 
                    (hdspm->
3040
 
                     control_register & HDSPM_clr_tms) ? "on" : "off",
3041
 
                    (hdspm->
3042
 
                     control_register & HDSPM_TX_64ch) ? "64" : "56",
3043
 
                    (hdspm->
3044
 
                     control_register & HDSPM_AutoInp) ? "on" : "off");
3045
 
 
3046
 
        switch (hdspm_clock_source(hdspm)) {
3047
 
        case HDSPM_CLOCK_SOURCE_AUTOSYNC:
3048
 
                clock_source = "AutoSync";
3049
 
                break;
3050
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3051
 
                clock_source = "Internal 32 kHz";
3052
 
                break;
3053
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3054
 
                clock_source = "Internal 44.1 kHz";
3055
 
                break;
3056
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3057
 
                clock_source = "Internal 48 kHz";
3058
 
                break;
3059
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3060
 
                clock_source = "Internal 64 kHz";
3061
 
                break;
3062
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3063
 
                clock_source = "Internal 88.2 kHz";
3064
 
                break;
3065
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3066
 
                clock_source = "Internal 96 kHz";
3067
 
                break;
3068
 
        default:
3069
 
                clock_source = "Error";
3070
 
        }
3071
 
        snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
 
4715
                "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
 
4716
                "Auto Input %s\n",
 
4717
                (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
 
4718
                (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
 
4719
                (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
 
4720
 
 
4721
 
3072
4722
        if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3073
 
                system_clock_mode = "Slave";
 
4723
                system_clock_mode = "AutoSync";
3074
4724
        else
3075
4725
                system_clock_mode = "Master";
3076
 
        snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
 
4726
        snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
3077
4727
 
3078
4728
        switch (hdspm_pref_sync_ref(hdspm)) {
3079
4729
        case HDSPM_SYNC_FROM_WORD:
3082
4732
        case HDSPM_SYNC_FROM_MADI:
3083
4733
                pref_sync_ref = "MADI Sync";
3084
4734
                break;
 
4735
        case HDSPM_SYNC_FROM_TCO:
 
4736
                pref_sync_ref = "TCO";
 
4737
                break;
 
4738
        case HDSPM_SYNC_FROM_SYNC_IN:
 
4739
                pref_sync_ref = "Sync In";
 
4740
                break;
3085
4741
        default:
3086
4742
                pref_sync_ref = "XXXX Clock";
3087
4743
                break;
3088
4744
        }
3089
4745
        snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
3090
 
                    pref_sync_ref);
 
4746
                        pref_sync_ref);
3091
4747
 
3092
4748
        snd_iprintf(buffer, "System Clock Frequency: %d\n",
3093
 
                    hdspm->system_sample_rate);
 
4749
                        hdspm->system_sample_rate);
3094
4750
 
3095
4751
 
3096
4752
        snd_iprintf(buffer, "--- Status:\n");
3099
4755
        x2 = status2 & HDSPM_wcSync;
3100
4756
 
3101
4757
        snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
3102
 
                    (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
3103
 
                    "NoLock",
3104
 
                    (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
3105
 
                    "NoLock");
 
4758
                        (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
 
4759
                        "NoLock",
 
4760
                        (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
 
4761
                        "NoLock");
3106
4762
 
3107
4763
        switch (hdspm_autosync_ref(hdspm)) {
 
4764
        case HDSPM_AUTOSYNC_FROM_SYNC_IN:
 
4765
                autosync_ref = "Sync In";
 
4766
                break;
 
4767
        case HDSPM_AUTOSYNC_FROM_TCO:
 
4768
                autosync_ref = "TCO";
 
4769
                break;
3108
4770
        case HDSPM_AUTOSYNC_FROM_WORD:
3109
4771
                autosync_ref = "Word Clock";
3110
4772
                break;
3119
4781
                break;
3120
4782
        }
3121
4783
        snd_iprintf(buffer,
3122
 
                    "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
3123
 
                    autosync_ref, hdspm_external_sample_rate(hdspm),
3124
 
                    (status & HDSPM_madiFreqMask) >> 22,
3125
 
                    (status2 & HDSPM_wcFreqMask) >> 5);
 
4784
                "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
 
4785
                autosync_ref, hdspm_external_sample_rate(hdspm),
 
4786
                (status & HDSPM_madiFreqMask) >> 22,
 
4787
                (status2 & HDSPM_wcFreqMask) >> 5);
3126
4788
 
3127
4789
        snd_iprintf(buffer, "Input: %s, Mode=%s\n",
3128
 
                    (status & HDSPM_AB_int) ? "Coax" : "Optical",
3129
 
                    (status & HDSPM_RX_64ch) ? "64 channels" :
3130
 
                    "56 channels");
 
4790
                (status & HDSPM_AB_int) ? "Coax" : "Optical",
 
4791
                (status & HDSPM_RX_64ch) ? "64 channels" :
 
4792
                "56 channels");
3131
4793
 
3132
4794
        snd_iprintf(buffer, "\n");
3133
4795
}
3142
4804
        unsigned int timecode;
3143
4805
        int pref_syncref;
3144
4806
        char *autosync_ref;
3145
 
        char *system_clock_mode;
3146
 
        char *clock_source;
3147
4807
        int x;
3148
4808
 
3149
4809
        status = hdspm_read(hdspm, HDSPM_statusRegister);
3183
4843
                    hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
3184
4844
                    hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
3185
4845
        snd_iprintf(buffer,
3186
 
                    "Register: ctrl1=0x%x, status1=0x%x, status2=0x%x, "
3187
 
                    "timecode=0x%x\n",
3188
 
                    hdspm->control_register,
3189
 
                    status, status2, timecode);
 
4846
                    "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
 
4847
                    hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
 
4848
                    hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
 
4849
        snd_iprintf(buffer,
 
4850
                    "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
 
4851
                    "status2=0x%x\n",
 
4852
                    hdspm->control_register, hdspm->control2_register,
 
4853
                    status, status2);
3190
4854
 
3191
4855
        snd_iprintf(buffer, "--- Settings ---\n");
3192
4856
 
3193
4857
        x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
3194
 
                                           HDSPM_LatencyMask));
 
4858
                                HDSPM_LatencyMask));
3195
4859
 
3196
4860
        snd_iprintf(buffer,
3197
4861
                    "Size (Latency): %d samples (2 periods of %lu bytes)\n",
3198
4862
                    x, (unsigned long) hdspm->period_bytes);
3199
4863
 
3200
 
        snd_iprintf(buffer, "Line out: %s,   Precise Pointer: %s\n",
 
4864
        snd_iprintf(buffer, "Line out: %s\n",
3201
4865
                    (hdspm->
3202
 
                     control_register & HDSPM_LineOut) ? "on " : "off",
3203
 
                    (hdspm->precise_ptr) ? "on" : "off");
 
4866
                     control_register & HDSPM_LineOut) ? "on " : "off");
3204
4867
 
3205
4868
        snd_iprintf(buffer,
3206
4869
                    "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
3211
4874
                    (hdspm->
3212
4875
                     control_register & HDSPM_Dolby) ? "on" : "off");
3213
4876
 
3214
 
        switch (hdspm_clock_source(hdspm)) {
3215
 
        case HDSPM_CLOCK_SOURCE_AUTOSYNC:
3216
 
                clock_source = "AutoSync";
3217
 
                break;
3218
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3219
 
                clock_source = "Internal 32 kHz";
3220
 
                break;
3221
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3222
 
                clock_source = "Internal 44.1 kHz";
3223
 
                break;
3224
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3225
 
                clock_source = "Internal 48 kHz";
3226
 
                break;
3227
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3228
 
                clock_source = "Internal 64 kHz";
3229
 
                break;
3230
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3231
 
                clock_source = "Internal 88.2 kHz";
3232
 
                break;
3233
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3234
 
                clock_source = "Internal 96 kHz";
3235
 
                break;
3236
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
3237
 
                clock_source = "Internal 128 kHz";
3238
 
                break;
3239
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3240
 
                clock_source = "Internal 176.4 kHz";
3241
 
                break;
3242
 
        case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
3243
 
                clock_source = "Internal 192 kHz";
3244
 
                break;
3245
 
        default:
3246
 
                clock_source = "Error";
3247
 
        }
3248
 
        snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3249
 
        if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3250
 
                system_clock_mode = "Slave";
3251
 
        else
3252
 
                system_clock_mode = "Master";
3253
 
        snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
3254
4877
 
3255
4878
        pref_syncref = hdspm_pref_sync_ref(hdspm);
3256
4879
        if (pref_syncref == 0)
3274
4897
        snd_iprintf(buffer, "--- Status:\n");
3275
4898
 
3276
4899
        snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
3277
 
                    (status & HDSPM_AES32_wcLock)? "Sync   " : "No Lock",
 
4900
                    (status & HDSPM_AES32_wcLock) ? "Sync   " : "No Lock",
3278
4901
                    HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
3279
4902
 
3280
4903
        for (x = 0; x < 8; x++) {
3281
4904
                snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
3282
4905
                            x+1,
3283
4906
                            (status2 & (HDSPM_LockAES >> x)) ?
3284
 
                            "Sync   ": "No Lock",
 
4907
                            "Sync   " : "No Lock",
3285
4908
                            HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
3286
4909
        }
3287
4910
 
3288
4911
        switch (hdspm_autosync_ref(hdspm)) {
3289
 
        case HDSPM_AES32_AUTOSYNC_FROM_NONE: autosync_ref="None"; break;
3290
 
        case HDSPM_AES32_AUTOSYNC_FROM_WORD: autosync_ref="Word Clock"; break;
3291
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES1: autosync_ref="AES1"; break;
3292
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES2: autosync_ref="AES2"; break;
3293
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES3: autosync_ref="AES3"; break;
3294
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES4: autosync_ref="AES4"; break;
3295
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES5: autosync_ref="AES5"; break;
3296
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES6: autosync_ref="AES6"; break;
3297
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES7: autosync_ref="AES7"; break;
3298
 
        case HDSPM_AES32_AUTOSYNC_FROM_AES8: autosync_ref="AES8"; break;
3299
 
        default: autosync_ref = "---"; break;
 
4912
        case HDSPM_AES32_AUTOSYNC_FROM_NONE:
 
4913
                autosync_ref = "None"; break;
 
4914
        case HDSPM_AES32_AUTOSYNC_FROM_WORD:
 
4915
                autosync_ref = "Word Clock"; break;
 
4916
        case HDSPM_AES32_AUTOSYNC_FROM_AES1:
 
4917
                autosync_ref = "AES1"; break;
 
4918
        case HDSPM_AES32_AUTOSYNC_FROM_AES2:
 
4919
                autosync_ref = "AES2"; break;
 
4920
        case HDSPM_AES32_AUTOSYNC_FROM_AES3:
 
4921
                autosync_ref = "AES3"; break;
 
4922
        case HDSPM_AES32_AUTOSYNC_FROM_AES4:
 
4923
                autosync_ref = "AES4"; break;
 
4924
        case HDSPM_AES32_AUTOSYNC_FROM_AES5:
 
4925
                autosync_ref = "AES5"; break;
 
4926
        case HDSPM_AES32_AUTOSYNC_FROM_AES6:
 
4927
                autosync_ref = "AES6"; break;
 
4928
        case HDSPM_AES32_AUTOSYNC_FROM_AES7:
 
4929
                autosync_ref = "AES7"; break;
 
4930
        case HDSPM_AES32_AUTOSYNC_FROM_AES8:
 
4931
                autosync_ref = "AES8"; break;
 
4932
        default:
 
4933
                autosync_ref = "---"; break;
3300
4934
        }
3301
4935
        snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
3302
4936
 
3303
4937
        snd_iprintf(buffer, "\n");
3304
4938
}
3305
4939
 
 
4940
static void
 
4941
snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
 
4942
                         struct snd_info_buffer *buffer)
 
4943
{
 
4944
        struct hdspm *hdspm = entry->private_data;
 
4945
        unsigned int status1, status2, status3, control, i;
 
4946
        unsigned int lock, sync;
 
4947
 
 
4948
        status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
 
4949
        status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
 
4950
        status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
 
4951
 
 
4952
        control = hdspm->control_register;
 
4953
 
 
4954
        snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
 
4955
        snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
 
4956
        snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
 
4957
 
 
4958
 
 
4959
        snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
 
4960
 
 
4961
        snd_iprintf(buffer, "Clock mode      : %s\n",
 
4962
                (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
 
4963
        snd_iprintf(buffer, "System frequency: %d Hz\n",
 
4964
                hdspm_get_system_sample_rate(hdspm));
 
4965
 
 
4966
        snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
 
4967
 
 
4968
        lock = 0x1;
 
4969
        sync = 0x100;
 
4970
 
 
4971
        for (i = 0; i < 8; i++) {
 
4972
                snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
 
4973
                                i,
 
4974
                                (status1 & lock) ? 1 : 0,
 
4975
                                (status1 & sync) ? 1 : 0,
 
4976
                                texts_freq[(status2 >> (i * 4)) & 0xF]);
 
4977
 
 
4978
                lock = lock<<1;
 
4979
                sync = sync<<1;
 
4980
        }
 
4981
 
 
4982
        snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
 
4983
                        (status1 & 0x1000000) ? 1 : 0,
 
4984
                        (status1 & 0x2000000) ? 1 : 0,
 
4985
                        texts_freq[(status1 >> 16) & 0xF]);
 
4986
 
 
4987
        snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
 
4988
                        (status1 & 0x4000000) ? 1 : 0,
 
4989
                        (status1 & 0x8000000) ? 1 : 0,
 
4990
                        texts_freq[(status1 >> 20) & 0xF]);
 
4991
 
 
4992
        snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
 
4993
                        (status3 & 0x400) ? 1 : 0,
 
4994
                        (status3 & 0x800) ? 1 : 0,
 
4995
                        texts_freq[(status2 >> 12) & 0xF]);
 
4996
 
 
4997
}
 
4998
 
3306
4999
#ifdef CONFIG_SND_DEBUG
3307
5000
static void
3308
 
snd_hdspm_proc_read_debug(struct snd_info_entry * entry,
 
5001
snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
3309
5002
                          struct snd_info_buffer *buffer)
3310
5003
{
3311
5004
        struct hdspm *hdspm = entry->private_data;
3322
5015
#endif
3323
5016
 
3324
5017
 
3325
 
 
3326
 
static void __devinit snd_hdspm_proc_init(struct hdspm * hdspm)
 
5018
static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
 
5019
                          struct snd_info_buffer *buffer)
 
5020
{
 
5021
        struct hdspm *hdspm = entry->private_data;
 
5022
        int i;
 
5023
 
 
5024
        snd_iprintf(buffer, "# generated by hdspm\n");
 
5025
 
 
5026
        for (i = 0; i < hdspm->max_channels_in; i++) {
 
5027
                snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
 
5028
        }
 
5029
}
 
5030
 
 
5031
static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
 
5032
                          struct snd_info_buffer *buffer)
 
5033
{
 
5034
        struct hdspm *hdspm = entry->private_data;
 
5035
        int i;
 
5036
 
 
5037
        snd_iprintf(buffer, "# generated by hdspm\n");
 
5038
 
 
5039
        for (i = 0; i < hdspm->max_channels_out; i++) {
 
5040
                snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
 
5041
        }
 
5042
}
 
5043
 
 
5044
 
 
5045
static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
3327
5046
{
3328
5047
        struct snd_info_entry *entry;
3329
5048
 
3330
 
        if (!snd_card_proc_new(hdspm->card, "hdspm", &entry))
3331
 
                snd_info_set_text_ops(entry, hdspm,
3332
 
                                      hdspm->is_aes32 ?
3333
 
                                      snd_hdspm_proc_read_aes32 :
3334
 
                                      snd_hdspm_proc_read_madi);
 
5049
        if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
 
5050
                switch (hdspm->io_type) {
 
5051
                case AES32:
 
5052
                        snd_info_set_text_ops(entry, hdspm,
 
5053
                                        snd_hdspm_proc_read_aes32);
 
5054
                        break;
 
5055
                case MADI:
 
5056
                        snd_info_set_text_ops(entry, hdspm,
 
5057
                                        snd_hdspm_proc_read_madi);
 
5058
                        break;
 
5059
                case MADIface:
 
5060
                        /* snd_info_set_text_ops(entry, hdspm,
 
5061
                         snd_hdspm_proc_read_madiface); */
 
5062
                        break;
 
5063
                case RayDAT:
 
5064
                        snd_info_set_text_ops(entry, hdspm,
 
5065
                                        snd_hdspm_proc_read_raydat);
 
5066
                        break;
 
5067
                case AIO:
 
5068
                        break;
 
5069
                }
 
5070
        }
 
5071
 
 
5072
        if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
 
5073
                snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
 
5074
        }
 
5075
 
 
5076
        if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
 
5077
                snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
 
5078
        }
 
5079
 
3335
5080
#ifdef CONFIG_SND_DEBUG
3336
5081
        /* debug file to read all hdspm registers */
3337
5082
        if (!snd_card_proc_new(hdspm->card, "debug", &entry))
3341
5086
}
3342
5087
 
3343
5088
/*------------------------------------------------------------
3344
 
   hdspm intitialize 
 
5089
   hdspm intitialize
3345
5090
 ------------------------------------------------------------*/
3346
5091
 
3347
5092
static int snd_hdspm_set_defaults(struct hdspm * hdspm)
3348
5093
{
3349
 
        unsigned int i;
3350
 
 
3351
5094
        /* ASSUMPTION: hdspm->lock is either held, or there is no need to
3352
5095
           hold it (e.g. during module initialization).
3353
 
         */
 
5096
           */
3354
5097
 
3355
5098
        /* set defaults:       */
3356
5099
 
3357
 
        if (hdspm->is_aes32)
 
5100
        hdspm->settings_register = 0;
 
5101
 
 
5102
        switch (hdspm->io_type) {
 
5103
        case MADI:
 
5104
        case MADIface:
 
5105
                hdspm->control_register =
 
5106
                        0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
 
5107
                break;
 
5108
 
 
5109
        case RayDAT:
 
5110
        case AIO:
 
5111
                hdspm->settings_register = 0x1 + 0x1000;
 
5112
                /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
 
5113
                 * line_out */
 
5114
                hdspm->control_register =
 
5115
                        0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
 
5116
                break;
 
5117
 
 
5118
        case AES32:
3358
5119
                hdspm->control_register =
3359
5120
                        HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3360
 
                        hdspm_encode_latency(7) | /* latency maximum =
3361
 
                                                   * 8192 samples
3362
 
                                                   */
 
5121
                        hdspm_encode_latency(7) | /* latency max=8192samples */
3363
5122
                        HDSPM_SyncRef0 |        /* AES1 is syncclock */
3364
5123
                        HDSPM_LineOut | /* Analog output in */
3365
5124
                        HDSPM_Professional;  /* Professional mode */
3366
 
        else
3367
 
                hdspm->control_register =
3368
 
                        HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3369
 
                        hdspm_encode_latency(7) | /* latency maximum =
3370
 
                                                   * 8192 samples
3371
 
                                                   */
3372
 
                        HDSPM_InputCoaxial |    /* Input Coax not Optical */
3373
 
                        HDSPM_SyncRef_MADI |    /* Madi is syncclock */
3374
 
                        HDSPM_LineOut | /* Analog output in */
3375
 
                        HDSPM_TX_64ch | /* transmit in 64ch mode */
3376
 
                        HDSPM_AutoInp;  /* AutoInput chossing (takeover) */
3377
 
 
3378
 
        /* ! HDSPM_Frequency0|HDSPM_Frequency1 = 44.1khz */
3379
 
        /* !  HDSPM_DoubleSpeed HDSPM_QuadSpeed = normal speed */
3380
 
        /* ! HDSPM_clr_tms = do not clear bits in track marks */
 
5125
                break;
 
5126
        }
3381
5127
 
3382
5128
        hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3383
5129
 
3384
 
        if (!hdspm->is_aes32) {
 
5130
        if (AES32 == hdspm->io_type) {
3385
5131
                /* No control2 register for AES32 */
3386
5132
#ifdef SNDRV_BIG_ENDIAN
3387
5133
                hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
3397
5143
 
3398
5144
        all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
3399
5145
 
3400
 
        if (line_outs_monitor[hdspm->dev]) {
3401
 
 
3402
 
                snd_printk(KERN_INFO "HDSPM: "
3403
 
                           "sending all playback streams to line outs.\n");
3404
 
 
3405
 
                for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) {
3406
 
                        if (hdspm_write_pb_gain(hdspm, i, i, UNITY_GAIN))
3407
 
                                return -EIO;
3408
 
                }
 
5146
        if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
 
5147
                hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3409
5148
        }
3410
5149
 
3411
5150
        /* set a default rate so that the channel map is set up. */
3412
 
        hdspm->channel_map = channel_map_madi_ss;
3413
 
        hdspm_set_rate(hdspm, 44100, 1);
 
5151
        hdspm_set_rate(hdspm, 48000, 1);
3414
5152
 
3415
5153
        return 0;
3416
5154
}
3417
5155
 
3418
5156
 
3419
5157
/*------------------------------------------------------------
3420
 
   interrupt 
 
5158
   interrupt
3421
5159
 ------------------------------------------------------------*/
3422
5160
 
3423
5161
static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
3424
5162
{
3425
5163
        struct hdspm *hdspm = (struct hdspm *) dev_id;
3426
5164
        unsigned int status;
3427
 
        int audio;
3428
 
        int midi0;
3429
 
        int midi1;
3430
 
        unsigned int midi0status;
3431
 
        unsigned int midi1status;
3432
 
        int schedule = 0;
 
5165
        int i, audio, midi, schedule = 0;
 
5166
        /* cycles_t now; */
3433
5167
 
3434
5168
        status = hdspm_read(hdspm, HDSPM_statusRegister);
3435
5169
 
3436
5170
        audio = status & HDSPM_audioIRQPending;
3437
 
        midi0 = status & HDSPM_midi0IRQPending;
3438
 
        midi1 = status & HDSPM_midi1IRQPending;
3439
 
 
3440
 
        if (!audio && !midi0 && !midi1)
 
5171
        midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
 
5172
                        HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
 
5173
 
 
5174
        /* now = get_cycles(); */
 
5175
        /**
 
5176
         *   LAT_2..LAT_0 period  counter (win)  counter (mac)
 
5177
         *          6       4096   ~256053425     ~514672358
 
5178
         *          5       2048   ~128024983     ~257373821
 
5179
         *          4       1024    ~64023706     ~128718089
 
5180
         *          3        512    ~32005945      ~64385999
 
5181
         *          2        256    ~16003039      ~32260176
 
5182
         *          1        128     ~7998738      ~16194507
 
5183
         *          0         64     ~3998231       ~8191558
 
5184
         **/
 
5185
        /*
 
5186
           snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
 
5187
           now-hdspm->last_interrupt, status & 0xFFC0);
 
5188
           hdspm->last_interrupt = now;
 
5189
        */
 
5190
 
 
5191
        if (!audio && !midi)
3441
5192
                return IRQ_NONE;
3442
5193
 
3443
5194
        hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
3444
5195
        hdspm->irq_count++;
3445
5196
 
3446
 
        midi0status = hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff;
3447
 
        midi1status = hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff;
3448
5197
 
3449
5198
        if (audio) {
3450
 
 
3451
5199
                if (hdspm->capture_substream)
3452
5200
                        snd_pcm_period_elapsed(hdspm->capture_substream);
3453
5201
 
3455
5203
                        snd_pcm_period_elapsed(hdspm->playback_substream);
3456
5204
        }
3457
5205
 
3458
 
        if (midi0 && midi0status) {
3459
 
                /* we disable interrupts for this input until processing
3460
 
                 * is done
3461
 
                 */
3462
 
                hdspm->control_register &= ~HDSPM_Midi0InterruptEnable;
3463
 
                hdspm_write(hdspm, HDSPM_controlRegister,
3464
 
                            hdspm->control_register);
3465
 
                hdspm->midi[0].pending = 1;
3466
 
                schedule = 1;
3467
 
        }
3468
 
        if (midi1 && midi1status) {
3469
 
                /* we disable interrupts for this input until processing
3470
 
                 * is done
3471
 
                 */
3472
 
                hdspm->control_register &= ~HDSPM_Midi1InterruptEnable;
3473
 
                hdspm_write(hdspm, HDSPM_controlRegister,
3474
 
                            hdspm->control_register);
3475
 
                hdspm->midi[1].pending = 1;
3476
 
                schedule = 1;
3477
 
        }
3478
 
        if (schedule)
3479
 
                tasklet_schedule(&hdspm->midi_tasklet);
 
5206
        if (midi) {
 
5207
                i = 0;
 
5208
                while (i < hdspm->midiPorts) {
 
5209
                        if ((hdspm_read(hdspm,
 
5210
                                hdspm->midi[i].statusIn) & 0xff) &&
 
5211
                                        (status & hdspm->midi[i].irq)) {
 
5212
                                /* we disable interrupts for this input until
 
5213
                                 * processing is done
 
5214
                                 */
 
5215
                                hdspm->control_register &= ~hdspm->midi[i].ie;
 
5216
                                hdspm_write(hdspm, HDSPM_controlRegister,
 
5217
                                                hdspm->control_register);
 
5218
                                hdspm->midi[i].pending = 1;
 
5219
                                schedule = 1;
 
5220
                        }
 
5221
 
 
5222
                        i++;
 
5223
                }
 
5224
 
 
5225
                if (schedule)
 
5226
                        tasklet_hi_schedule(&hdspm->midi_tasklet);
 
5227
        }
 
5228
 
3480
5229
        return IRQ_HANDLED;
3481
5230
}
3482
5231
 
3483
5232
/*------------------------------------------------------------
3484
 
   pcm interface 
 
5233
   pcm interface
3485
5234
  ------------------------------------------------------------*/
3486
5235
 
3487
5236
 
3488
 
static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream *
3489
 
                                              substream)
 
5237
static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
 
5238
                                              *substream)
3490
5239
{
3491
5240
        struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3492
5241
        return hdspm_hw_pointer(hdspm);
3493
5242
}
3494
5243
 
3495
 
static char *hdspm_channel_buffer_location(struct hdspm * hdspm,
3496
 
                                           int stream, int channel)
3497
 
{
3498
 
        int mapped_channel;
3499
 
 
3500
 
        if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3501
 
                return NULL;
3502
 
 
3503
 
        mapped_channel = hdspm->channel_map[channel];
3504
 
        if (mapped_channel < 0)
3505
 
                return NULL;
3506
 
 
3507
 
        if (stream == SNDRV_PCM_STREAM_CAPTURE)
3508
 
                return hdspm->capture_buffer +
3509
 
                    mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3510
 
        else
3511
 
                return hdspm->playback_buffer +
3512
 
                    mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3513
 
}
3514
 
 
3515
 
 
3516
 
/* dont know why need it ??? */
3517
 
static int snd_hdspm_playback_copy(struct snd_pcm_substream *substream,
3518
 
                                   int channel, snd_pcm_uframes_t pos,
3519
 
                                   void __user *src, snd_pcm_uframes_t count)
3520
 
{
3521
 
        struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3522
 
        char *channel_buf;
3523
 
 
3524
 
        if (snd_BUG_ON(pos + count > HDSPM_CHANNEL_BUFFER_BYTES / 4))
3525
 
                return -EINVAL;
3526
 
 
3527
 
        channel_buf =
3528
 
                hdspm_channel_buffer_location(hdspm, substream->pstr->stream,
3529
 
                                              channel);
3530
 
 
3531
 
        if (snd_BUG_ON(!channel_buf))
3532
 
                return -EIO;
3533
 
 
3534
 
        return copy_from_user(channel_buf + pos * 4, src, count * 4);
3535
 
}
3536
 
 
3537
 
static int snd_hdspm_capture_copy(struct snd_pcm_substream *substream,
3538
 
                                  int channel, snd_pcm_uframes_t pos,
3539
 
                                  void __user *dst, snd_pcm_uframes_t count)
3540
 
{
3541
 
        struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3542
 
        char *channel_buf;
3543
 
 
3544
 
        if (snd_BUG_ON(pos + count > HDSPM_CHANNEL_BUFFER_BYTES / 4))
3545
 
                return -EINVAL;
3546
 
 
3547
 
        channel_buf =
3548
 
                hdspm_channel_buffer_location(hdspm, substream->pstr->stream,
3549
 
                                              channel);
3550
 
        if (snd_BUG_ON(!channel_buf))
3551
 
                return -EIO;
3552
 
        return copy_to_user(dst, channel_buf + pos * 4, count * 4);
3553
 
}
3554
 
 
3555
 
static int snd_hdspm_hw_silence(struct snd_pcm_substream *substream,
3556
 
                                int channel, snd_pcm_uframes_t pos,
3557
 
                                snd_pcm_uframes_t count)
3558
 
{
3559
 
        struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3560
 
        char *channel_buf;
3561
 
 
3562
 
        channel_buf =
3563
 
                hdspm_channel_buffer_location(hdspm, substream->pstr->stream,
3564
 
                                              channel);
3565
 
        if (snd_BUG_ON(!channel_buf))
3566
 
                return -EIO;
3567
 
        memset(channel_buf + pos * 4, 0, count * 4);
3568
 
        return 0;
3569
 
}
3570
5244
 
3571
5245
static int snd_hdspm_reset(struct snd_pcm_substream *substream)
3572
5246
{
3589
5263
                snd_pcm_group_for_each_entry(s, substream) {
3590
5264
                        if (s == other) {
3591
5265
                                oruntime->status->hw_ptr =
3592
 
                                    runtime->status->hw_ptr;
 
5266
                                        runtime->status->hw_ptr;
3593
5267
                                break;
3594
5268
                        }
3595
5269
                }
3621
5295
                /* The other stream is open, and not by the same
3622
5296
                   task as this one. Make sure that the parameters
3623
5297
                   that matter are the same.
3624
 
                 */
 
5298
                   */
3625
5299
 
3626
5300
                if (params_rate(params) != hdspm->system_sample_rate) {
3627
5301
                        spin_unlock_irq(&hdspm->lock);
3628
5302
                        _snd_pcm_hw_param_setempty(params,
3629
 
                                                   SNDRV_PCM_HW_PARAM_RATE);
 
5303
                                        SNDRV_PCM_HW_PARAM_RATE);
3630
5304
                        return -EBUSY;
3631
5305
                }
3632
5306
 
3633
5307
                if (params_period_size(params) != hdspm->period_bytes / 4) {
3634
5308
                        spin_unlock_irq(&hdspm->lock);
3635
5309
                        _snd_pcm_hw_param_setempty(params,
3636
 
                                           SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
 
5310
                                        SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3637
5311
                        return -EBUSY;
3638
5312
                }
3639
5313
 
3646
5320
        spin_lock_irq(&hdspm->lock);
3647
5321
        err = hdspm_set_rate(hdspm, params_rate(params), 0);
3648
5322
        if (err < 0) {
 
5323
                snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
3649
5324
                spin_unlock_irq(&hdspm->lock);
3650
5325
                _snd_pcm_hw_param_setempty(params,
3651
 
                                           SNDRV_PCM_HW_PARAM_RATE);
 
5326
                                SNDRV_PCM_HW_PARAM_RATE);
3652
5327
                return err;
3653
5328
        }
3654
5329
        spin_unlock_irq(&hdspm->lock);
3655
5330
 
3656
5331
        err = hdspm_set_interrupt_interval(hdspm,
3657
 
                                           params_period_size(params));
 
5332
                        params_period_size(params));
3658
5333
        if (err < 0) {
 
5334
                snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
3659
5335
                _snd_pcm_hw_param_setempty(params,
3660
 
                                           SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
 
5336
                                SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3661
5337
                return err;
3662
5338
        }
3663
5339
 
3667
5343
        /* malloc all buffer even if not enabled to get sure */
3668
5344
        /* Update for MADI rev 204: we need to allocate for all channels,
3669
5345
         * otherwise it doesn't work at 96kHz */
 
5346
 
3670
5347
        err =
3671
 
            snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
3672
 
        if (err < 0)
 
5348
                snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
 
5349
        if (err < 0) {
 
5350
                snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
3673
5351
                return err;
 
5352
        }
3674
5353
 
3675
5354
        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3676
5355
 
3681
5360
                        snd_hdspm_enable_out(hdspm, i, 1);
3682
5361
 
3683
5362
                hdspm->playback_buffer =
3684
 
                    (unsigned char *) substream->runtime->dma_area;
 
5363
                        (unsigned char *) substream->runtime->dma_area;
3685
5364
                snd_printdd("Allocated sample buffer for playback at %p\n",
3686
5365
                                hdspm->playback_buffer);
3687
5366
        } else {
3692
5371
                        snd_hdspm_enable_in(hdspm, i, 1);
3693
5372
 
3694
5373
                hdspm->capture_buffer =
3695
 
                    (unsigned char *) substream->runtime->dma_area;
 
5374
                        (unsigned char *) substream->runtime->dma_area;
3696
5375
                snd_printdd("Allocated sample buffer for capture at %p\n",
3697
5376
                                hdspm->capture_buffer);
3698
5377
        }
 
5378
 
3699
5379
        /*
3700
5380
           snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
3701
5381
           substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3702
5382
           "playback" : "capture",
3703
5383
           snd_pcm_sgbuf_get_addr(substream, 0));
3704
 
         */
 
5384
           */
3705
5385
        /*
3706
 
        snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
3707
 
                        substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3708
 
                          "playback" : "capture",
3709
 
                        params_rate(params), params_channels(params),
3710
 
                        params_buffer_size(params));
3711
 
        */
 
5386
           snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
 
5387
           substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
 
5388
           "playback" : "capture",
 
5389
           params_rate(params), params_channels(params),
 
5390
           params_buffer_size(params));
 
5391
           */
 
5392
 
 
5393
 
 
5394
        /* Switch to native float format if requested */
 
5395
        if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
 
5396
                if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
 
5397
                        snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
 
5398
 
 
5399
                hdspm->control_register |= HDSPe_FLOAT_FORMAT;
 
5400
        } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
 
5401
                if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
 
5402
                        snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
 
5403
 
 
5404
                hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
 
5405
        }
 
5406
        hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
 
5407
 
3712
5408
        return 0;
3713
5409
}
3714
5410
 
3719
5415
 
3720
5416
        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3721
5417
 
3722
 
                /* params_channels(params) should be enough, 
 
5418
                /* params_channels(params) should be enough,
3723
5419
                   but to get sure in case of error */
3724
 
                for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
 
5420
                for (i = 0; i < hdspm->max_channels_out; ++i)
3725
5421
                        snd_hdspm_enable_out(hdspm, i, 0);
3726
5422
 
3727
5423
                hdspm->playback_buffer = NULL;
3728
5424
        } else {
3729
 
                for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
 
5425
                for (i = 0; i < hdspm->max_channels_in; ++i)
3730
5426
                        snd_hdspm_enable_in(hdspm, i, 0);
3731
5427
 
3732
5428
                hdspm->capture_buffer = NULL;
3738
5434
        return 0;
3739
5435
}
3740
5436
 
 
5437
 
3741
5438
static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
3742
 
                                  struct snd_pcm_channel_info * info)
 
5439
                struct snd_pcm_channel_info *info)
3743
5440
{
3744
5441
        struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3745
 
        int mapped_channel;
3746
 
 
3747
 
        if (snd_BUG_ON(info->channel >= HDSPM_MAX_CHANNELS))
3748
 
                return -EINVAL;
3749
 
 
3750
 
        mapped_channel = hdspm->channel_map[info->channel];
3751
 
        if (mapped_channel < 0)
3752
 
                return -EINVAL;
3753
 
 
3754
 
        info->offset = mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
 
5442
 
 
5443
        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 
5444
                if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
 
5445
                        snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
 
5446
                        return -EINVAL;
 
5447
                }
 
5448
 
 
5449
                if (hdspm->channel_map_out[info->channel] < 0) {
 
5450
                        snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
 
5451
                        return -EINVAL;
 
5452
                }
 
5453
 
 
5454
                info->offset = hdspm->channel_map_out[info->channel] *
 
5455
                        HDSPM_CHANNEL_BUFFER_BYTES;
 
5456
        } else {
 
5457
                if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
 
5458
                        snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
 
5459
                        return -EINVAL;
 
5460
                }
 
5461
 
 
5462
                if (hdspm->channel_map_in[info->channel] < 0) {
 
5463
                        snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
 
5464
                        return -EINVAL;
 
5465
                }
 
5466
 
 
5467
                info->offset = hdspm->channel_map_in[info->channel] *
 
5468
                        HDSPM_CHANNEL_BUFFER_BYTES;
 
5469
        }
 
5470
 
3755
5471
        info->first = 0;
3756
5472
        info->step = 32;
3757
5473
        return 0;
3758
5474
}
3759
5475
 
 
5476
 
3760
5477
static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
3761
 
                           unsigned int cmd, void *arg)
 
5478
                unsigned int cmd, void *arg)
3762
5479
{
3763
5480
        switch (cmd) {
3764
5481
        case SNDRV_PCM_IOCTL1_RESET:
3765
5482
                return snd_hdspm_reset(substream);
3766
5483
 
3767
5484
        case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3768
 
        {
3769
 
                struct snd_pcm_channel_info *info = arg;
3770
 
                return snd_hdspm_channel_info(substream, info);
3771
 
        }
 
5485
                {
 
5486
                        struct snd_pcm_channel_info *info = arg;
 
5487
                        return snd_hdspm_channel_info(substream, info);
 
5488
                }
3772
5489
        default:
3773
5490
                break;
3774
5491
        }
3815
5532
                }
3816
5533
                if (cmd == SNDRV_PCM_TRIGGER_START) {
3817
5534
                        if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
3818
 
                            && substream->stream ==
3819
 
                            SNDRV_PCM_STREAM_CAPTURE)
 
5535
                                        && substream->stream ==
 
5536
                                        SNDRV_PCM_STREAM_CAPTURE)
3820
5537
                                hdspm_silence_playback(hdspm);
3821
5538
                } else {
3822
5539
                        if (running &&
3823
 
                            substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 
5540
                                substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3824
5541
                                hdspm_silence_playback(hdspm);
3825
5542
                }
3826
5543
        } else {
3827
5544
                if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3828
5545
                        hdspm_silence_playback(hdspm);
3829
5546
        }
3830
 
      _ok:
 
5547
_ok:
3831
5548
        snd_pcm_trigger_done(substream, substream);
3832
5549
        if (!hdspm->running && running)
3833
5550
                hdspm_start_audio(hdspm);
3844
5561
        return 0;
3845
5562
}
3846
5563
 
3847
 
static unsigned int period_sizes[] =
3848
 
    { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
 
5564
static unsigned int period_sizes_old[] = {
 
5565
        64, 128, 256, 512, 1024, 2048, 4096
 
5566
};
 
5567
 
 
5568
static unsigned int period_sizes_new[] = {
 
5569
        32, 64, 128, 256, 512, 1024, 2048, 4096
 
5570
};
 
5571
 
 
5572
/* RayDAT and AIO always have a buffer of 16384 samples per channel */
 
5573
static unsigned int raydat_aio_buffer_sizes[] = {
 
5574
        16384
 
5575
};
3849
5576
 
3850
5577
static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
3851
5578
        .info = (SNDRV_PCM_INFO_MMAP |
3866
5593
        .buffer_bytes_max =
3867
5594
            HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
3868
5595
        .period_bytes_min = (64 * 4),
3869
 
        .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
 
5596
        .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
3870
5597
        .periods_min = 2,
3871
 
        .periods_max = 2,
 
5598
        .periods_max = 512,
3872
5599
        .fifo_size = 0
3873
5600
};
3874
5601
 
3891
5618
        .buffer_bytes_max =
3892
5619
            HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
3893
5620
        .period_bytes_min = (64 * 4),
3894
 
        .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
 
5621
        .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
3895
5622
        .periods_min = 2,
3896
 
        .periods_max = 2,
 
5623
        .periods_max = 512,
3897
5624
        .fifo_size = 0
3898
5625
};
3899
5626
 
3900
 
static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
3901
 
        .count = ARRAY_SIZE(period_sizes),
3902
 
        .list = period_sizes,
3903
 
        .mask = 0
3904
 
};
3905
 
 
3906
 
 
3907
 
static int snd_hdspm_hw_rule_channels_rate(struct snd_pcm_hw_params *params,
3908
 
                                           struct snd_pcm_hw_rule * rule)
3909
 
{
3910
 
        struct hdspm *hdspm = rule->private;
3911
 
        struct snd_interval *c =
3912
 
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
3913
 
        struct snd_interval *r =
3914
 
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3915
 
 
3916
 
        if (r->min > 48000 && r->max <= 96000) {
3917
 
                struct snd_interval t = {
3918
 
                        .min = hdspm->ds_channels,
3919
 
                        .max = hdspm->ds_channels,
3920
 
                        .integer = 1,
3921
 
                };
3922
 
                return snd_interval_refine(c, &t);
3923
 
        } else if (r->max < 64000) {
3924
 
                struct snd_interval t = {
3925
 
                        .min = hdspm->ss_channels,
3926
 
                        .max = hdspm->ss_channels,
3927
 
                        .integer = 1,
3928
 
                };
3929
 
                return snd_interval_refine(c, &t);
3930
 
        }
3931
 
        return 0;
3932
 
}
3933
 
 
3934
 
static int snd_hdspm_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
3935
 
                                           struct snd_pcm_hw_rule * rule)
3936
 
{
3937
 
        struct hdspm *hdspm = rule->private;
3938
 
        struct snd_interval *c =
3939
 
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
3940
 
        struct snd_interval *r =
3941
 
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3942
 
 
3943
 
        if (c->min >= hdspm->ss_channels) {
3944
 
                struct snd_interval t = {
3945
 
                        .min = 32000,
3946
 
                        .max = 48000,
3947
 
                        .integer = 1,
3948
 
                };
3949
 
                return snd_interval_refine(r, &t);
3950
 
        } else if (c->max <= hdspm->ds_channels) {
3951
 
                struct snd_interval t = {
3952
 
                        .min = 64000,
3953
 
                        .max = 96000,
3954
 
                        .integer = 1,
3955
 
                };
3956
 
 
3957
 
                return snd_interval_refine(r, &t);
3958
 
        }
3959
 
        return 0;
3960
 
}
3961
 
 
3962
 
static int snd_hdspm_hw_rule_channels(struct snd_pcm_hw_params *params,
3963
 
                                      struct snd_pcm_hw_rule *rule)
3964
 
{
3965
 
        unsigned int list[3];
3966
 
        struct hdspm *hdspm = rule->private;
3967
 
        struct snd_interval *c = hw_param_interval(params,
3968
 
                        SNDRV_PCM_HW_PARAM_CHANNELS);
3969
 
        if (hdspm->is_aes32) {
3970
 
                list[0] = hdspm->qs_channels;
3971
 
                list[1] = hdspm->ds_channels;
3972
 
                list[2] = hdspm->ss_channels;
3973
 
                return snd_interval_list(c, 3, list, 0);
 
5627
static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
 
5628
        .count = ARRAY_SIZE(period_sizes_old),
 
5629
        .list = period_sizes_old,
 
5630
        .mask = 0
 
5631
};
 
5632
 
 
5633
static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
 
5634
        .count = ARRAY_SIZE(period_sizes_new),
 
5635
        .list = period_sizes_new,
 
5636
        .mask = 0
 
5637
};
 
5638
 
 
5639
static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
 
5640
        .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
 
5641
        .list = raydat_aio_buffer_sizes,
 
5642
        .mask = 0
 
5643
};
 
5644
 
 
5645
static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
 
5646
                                           struct snd_pcm_hw_rule *rule)
 
5647
{
 
5648
        struct hdspm *hdspm = rule->private;
 
5649
        struct snd_interval *c =
 
5650
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
 
5651
        struct snd_interval *r =
 
5652
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
 
5653
 
 
5654
        if (r->min > 96000 && r->max <= 192000) {
 
5655
                struct snd_interval t = {
 
5656
                        .min = hdspm->qs_in_channels,
 
5657
                        .max = hdspm->qs_in_channels,
 
5658
                        .integer = 1,
 
5659
                };
 
5660
                return snd_interval_refine(c, &t);
 
5661
        } else if (r->min > 48000 && r->max <= 96000) {
 
5662
                struct snd_interval t = {
 
5663
                        .min = hdspm->ds_in_channels,
 
5664
                        .max = hdspm->ds_in_channels,
 
5665
                        .integer = 1,
 
5666
                };
 
5667
                return snd_interval_refine(c, &t);
 
5668
        } else if (r->max < 64000) {
 
5669
                struct snd_interval t = {
 
5670
                        .min = hdspm->ss_in_channels,
 
5671
                        .max = hdspm->ss_in_channels,
 
5672
                        .integer = 1,
 
5673
                };
 
5674
                return snd_interval_refine(c, &t);
 
5675
        }
 
5676
 
 
5677
        return 0;
 
5678
}
 
5679
 
 
5680
static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
 
5681
                                           struct snd_pcm_hw_rule * rule)
 
5682
{
 
5683
        struct hdspm *hdspm = rule->private;
 
5684
        struct snd_interval *c =
 
5685
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
 
5686
        struct snd_interval *r =
 
5687
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
 
5688
 
 
5689
        if (r->min > 96000 && r->max <= 192000) {
 
5690
                struct snd_interval t = {
 
5691
                        .min = hdspm->qs_out_channels,
 
5692
                        .max = hdspm->qs_out_channels,
 
5693
                        .integer = 1,
 
5694
                };
 
5695
                return snd_interval_refine(c, &t);
 
5696
        } else if (r->min > 48000 && r->max <= 96000) {
 
5697
                struct snd_interval t = {
 
5698
                        .min = hdspm->ds_out_channels,
 
5699
                        .max = hdspm->ds_out_channels,
 
5700
                        .integer = 1,
 
5701
                };
 
5702
                return snd_interval_refine(c, &t);
 
5703
        } else if (r->max < 64000) {
 
5704
                struct snd_interval t = {
 
5705
                        .min = hdspm->ss_out_channels,
 
5706
                        .max = hdspm->ss_out_channels,
 
5707
                        .integer = 1,
 
5708
                };
 
5709
                return snd_interval_refine(c, &t);
3974
5710
        } else {
3975
 
                list[0] = hdspm->ds_channels;
3976
 
                list[1] = hdspm->ss_channels;
3977
 
                return snd_interval_list(c, 2, list, 0);
3978
 
        }
 
5711
        }
 
5712
        return 0;
 
5713
}
 
5714
 
 
5715
static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
 
5716
                                           struct snd_pcm_hw_rule * rule)
 
5717
{
 
5718
        struct hdspm *hdspm = rule->private;
 
5719
        struct snd_interval *c =
 
5720
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
 
5721
        struct snd_interval *r =
 
5722
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
 
5723
 
 
5724
        if (c->min >= hdspm->ss_in_channels) {
 
5725
                struct snd_interval t = {
 
5726
                        .min = 32000,
 
5727
                        .max = 48000,
 
5728
                        .integer = 1,
 
5729
                };
 
5730
                return snd_interval_refine(r, &t);
 
5731
        } else if (c->max <= hdspm->qs_in_channels) {
 
5732
                struct snd_interval t = {
 
5733
                        .min = 128000,
 
5734
                        .max = 192000,
 
5735
                        .integer = 1,
 
5736
                };
 
5737
                return snd_interval_refine(r, &t);
 
5738
        } else if (c->max <= hdspm->ds_in_channels) {
 
5739
                struct snd_interval t = {
 
5740
                        .min = 64000,
 
5741
                        .max = 96000,
 
5742
                        .integer = 1,
 
5743
                };
 
5744
                return snd_interval_refine(r, &t);
 
5745
        }
 
5746
 
 
5747
        return 0;
 
5748
}
 
5749
static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
 
5750
                                           struct snd_pcm_hw_rule *rule)
 
5751
{
 
5752
        struct hdspm *hdspm = rule->private;
 
5753
        struct snd_interval *c =
 
5754
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
 
5755
        struct snd_interval *r =
 
5756
            hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
 
5757
 
 
5758
        if (c->min >= hdspm->ss_out_channels) {
 
5759
                struct snd_interval t = {
 
5760
                        .min = 32000,
 
5761
                        .max = 48000,
 
5762
                        .integer = 1,
 
5763
                };
 
5764
                return snd_interval_refine(r, &t);
 
5765
        } else if (c->max <= hdspm->qs_out_channels) {
 
5766
                struct snd_interval t = {
 
5767
                        .min = 128000,
 
5768
                        .max = 192000,
 
5769
                        .integer = 1,
 
5770
                };
 
5771
                return snd_interval_refine(r, &t);
 
5772
        } else if (c->max <= hdspm->ds_out_channels) {
 
5773
                struct snd_interval t = {
 
5774
                        .min = 64000,
 
5775
                        .max = 96000,
 
5776
                        .integer = 1,
 
5777
                };
 
5778
                return snd_interval_refine(r, &t);
 
5779
        }
 
5780
 
 
5781
        return 0;
 
5782
}
 
5783
 
 
5784
static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
 
5785
                                      struct snd_pcm_hw_rule *rule)
 
5786
{
 
5787
        unsigned int list[3];
 
5788
        struct hdspm *hdspm = rule->private;
 
5789
        struct snd_interval *c = hw_param_interval(params,
 
5790
                        SNDRV_PCM_HW_PARAM_CHANNELS);
 
5791
 
 
5792
        list[0] = hdspm->qs_in_channels;
 
5793
        list[1] = hdspm->ds_in_channels;
 
5794
        list[2] = hdspm->ss_in_channels;
 
5795
        return snd_interval_list(c, 3, list, 0);
 
5796
}
 
5797
 
 
5798
static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
 
5799
                                      struct snd_pcm_hw_rule *rule)
 
5800
{
 
5801
        unsigned int list[3];
 
5802
        struct hdspm *hdspm = rule->private;
 
5803
        struct snd_interval *c = hw_param_interval(params,
 
5804
                        SNDRV_PCM_HW_PARAM_CHANNELS);
 
5805
 
 
5806
        list[0] = hdspm->qs_out_channels;
 
5807
        list[1] = hdspm->ds_out_channels;
 
5808
        list[2] = hdspm->ss_out_channels;
 
5809
        return snd_interval_list(c, 3, list, 0);
3979
5810
}
3980
5811
 
3981
5812
 
3999
5830
 
4000
5831
        snd_pcm_set_sync(substream);
4001
5832
 
 
5833
 
4002
5834
        runtime->hw = snd_hdspm_playback_subinfo;
4003
5835
 
4004
5836
        if (hdspm->capture_substream == NULL)
4011
5843
 
4012
5844
        snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4013
5845
 
4014
 
        snd_pcm_hw_constraint_list(runtime, 0,
4015
 
                                   SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
4016
 
                                   &hw_constraints_period_sizes);
4017
 
 
4018
 
        if (hdspm->is_aes32) {
 
5846
        switch (hdspm->io_type) {
 
5847
        case AIO:
 
5848
        case RayDAT:
 
5849
                snd_pcm_hw_constraint_list(runtime, 0,
 
5850
                                SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 
5851
                                &hw_constraints_period_sizes_new);
 
5852
                snd_pcm_hw_constraint_list(runtime, 0,
 
5853
                                SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 
5854
                                &hw_constraints_raydat_io_buffer);
 
5855
 
 
5856
                break;
 
5857
 
 
5858
        default:
 
5859
                snd_pcm_hw_constraint_list(runtime, 0,
 
5860
                                SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 
5861
                                &hw_constraints_period_sizes_old);
 
5862
        }
 
5863
 
 
5864
        if (AES32 == hdspm->io_type) {
4019
5865
                snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4020
5866
                                &hdspm_hw_constraints_aes32_sample_rates);
4021
5867
        } else {
4022
 
                snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4023
 
                                     snd_hdspm_hw_rule_channels, hdspm,
4024
 
                                     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4025
 
                snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4026
 
                                    snd_hdspm_hw_rule_channels_rate, hdspm,
4027
 
                                    SNDRV_PCM_HW_PARAM_RATE, -1);
4028
 
 
4029
5868
                snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4030
 
                                    snd_hdspm_hw_rule_rate_channels, hdspm,
4031
 
                                    SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 
5869
                                snd_hdspm_hw_rule_rate_out_channels, hdspm,
 
5870
                                SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4032
5871
        }
 
5872
 
 
5873
        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 
5874
                        snd_hdspm_hw_rule_out_channels, hdspm,
 
5875
                        SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 
5876
 
 
5877
        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 
5878
                        snd_hdspm_hw_rule_out_channels_rate, hdspm,
 
5879
                        SNDRV_PCM_HW_PARAM_RATE, -1);
 
5880
 
4033
5881
        return 0;
4034
5882
}
4035
5883
 
4066
5914
        spin_unlock_irq(&hdspm->lock);
4067
5915
 
4068
5916
        snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4069
 
        snd_pcm_hw_constraint_list(runtime, 0,
4070
 
                                   SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
4071
 
                                   &hw_constraints_period_sizes);
4072
 
        if (hdspm->is_aes32) {
 
5917
        switch (hdspm->io_type) {
 
5918
        case AIO:
 
5919
        case RayDAT:
 
5920
          snd_pcm_hw_constraint_list(runtime, 0,
 
5921
                                     SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 
5922
                                     &hw_constraints_period_sizes_new);
 
5923
          snd_pcm_hw_constraint_list(runtime, 0,
 
5924
                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 
5925
                                     &hw_constraints_raydat_io_buffer);
 
5926
          break;
 
5927
 
 
5928
        default:
 
5929
          snd_pcm_hw_constraint_list(runtime, 0,
 
5930
                                     SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 
5931
                                     &hw_constraints_period_sizes_old);
 
5932
        }
 
5933
 
 
5934
        if (AES32 == hdspm->io_type) {
4073
5935
                snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4074
5936
                                &hdspm_hw_constraints_aes32_sample_rates);
4075
5937
        } else {
4076
 
                snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4077
 
                                     snd_hdspm_hw_rule_channels, hdspm,
4078
 
                                     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4079
 
                snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4080
 
                                    snd_hdspm_hw_rule_channels_rate, hdspm,
4081
 
                                    SNDRV_PCM_HW_PARAM_RATE, -1);
4082
 
 
4083
5938
                snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4084
 
                                    snd_hdspm_hw_rule_rate_channels, hdspm,
4085
 
                                    SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 
5939
                                snd_hdspm_hw_rule_rate_in_channels, hdspm,
 
5940
                                SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4086
5941
        }
 
5942
 
 
5943
        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 
5944
                        snd_hdspm_hw_rule_in_channels, hdspm,
 
5945
                        SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 
5946
 
 
5947
        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 
5948
                        snd_hdspm_hw_rule_in_channels_rate, hdspm,
 
5949
                        SNDRV_PCM_HW_PARAM_RATE, -1);
 
5950
 
4087
5951
        return 0;
4088
5952
}
4089
5953
 
4100
5964
        return 0;
4101
5965
}
4102
5966
 
4103
 
static int snd_hdspm_hwdep_ioctl(struct snd_hwdep * hw, struct file *file,
4104
 
                                 unsigned int cmd, unsigned long arg)
4105
 
{
 
5967
static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
 
5968
{
 
5969
        /* we have nothing to initialize but the call is required */
 
5970
        return 0;
 
5971
}
 
5972
 
 
5973
static inline int copy_u32_le(void __user *dest, void __iomem *src)
 
5974
{
 
5975
        u32 val = readl(src);
 
5976
        return copy_to_user(dest, &val, 4);
 
5977
}
 
5978
 
 
5979
static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
 
5980
                unsigned int cmd, unsigned long __user arg)
 
5981
{
 
5982
        void __user *argp = (void __user *)arg;
4106
5983
        struct hdspm *hdspm = hw->private_data;
4107
5984
        struct hdspm_mixer_ioctl mixer;
4108
 
        struct hdspm_config_info info;
 
5985
        struct hdspm_config info;
 
5986
        struct hdspm_status status;
4109
5987
        struct hdspm_version hdspm_version;
4110
 
        struct hdspm_peak_rms_ioctl rms;
 
5988
        struct hdspm_peak_rms *levels;
 
5989
        struct hdspm_ltc ltc;
 
5990
        unsigned int statusregister;
 
5991
        long unsigned int s;
 
5992
        int i = 0;
4111
5993
 
4112
5994
        switch (cmd) {
4113
5995
 
4114
5996
        case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
4115
 
                if (copy_from_user(&rms, (void __user *)arg, sizeof(rms)))
4116
 
                        return -EFAULT;
4117
 
                /* maybe there is a chance to memorymap in future
4118
 
                 * so dont touch just copy
4119
 
                 */
4120
 
                if(copy_to_user_fromio((void __user *)rms.peak,
4121
 
                                       hdspm->iobase+HDSPM_MADI_peakrmsbase,
4122
 
                                       sizeof(struct hdspm_peak_rms)) != 0 )
4123
 
                        return -EFAULT;
4124
 
 
4125
 
                break;
4126
 
                
4127
 
 
4128
 
        case SNDRV_HDSPM_IOCTL_GET_CONFIG_INFO:
 
5997
                levels = &hdspm->peak_rms;
 
5998
                for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
 
5999
                        levels->input_peaks[i] =
 
6000
                                readl(hdspm->iobase +
 
6001
                                                HDSPM_MADI_INPUT_PEAK + i*4);
 
6002
                        levels->playback_peaks[i] =
 
6003
                                readl(hdspm->iobase +
 
6004
                                                HDSPM_MADI_PLAYBACK_PEAK + i*4);
 
6005
                        levels->output_peaks[i] =
 
6006
                                readl(hdspm->iobase +
 
6007
                                                HDSPM_MADI_OUTPUT_PEAK + i*4);
 
6008
 
 
6009
                        levels->input_rms[i] =
 
6010
                                ((uint64_t) readl(hdspm->iobase +
 
6011
                                        HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
 
6012
                                (uint64_t) readl(hdspm->iobase +
 
6013
                                                HDSPM_MADI_INPUT_RMS_L + i*4);
 
6014
                        levels->playback_rms[i] =
 
6015
                                ((uint64_t)readl(hdspm->iobase +
 
6016
                                        HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
 
6017
                                (uint64_t)readl(hdspm->iobase +
 
6018
                                        HDSPM_MADI_PLAYBACK_RMS_L + i*4);
 
6019
                        levels->output_rms[i] =
 
6020
                                ((uint64_t)readl(hdspm->iobase +
 
6021
                                        HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
 
6022
                                (uint64_t)readl(hdspm->iobase +
 
6023
                                                HDSPM_MADI_OUTPUT_RMS_L + i*4);
 
6024
                }
 
6025
 
 
6026
                if (hdspm->system_sample_rate > 96000) {
 
6027
                        levels->speed = qs;
 
6028
                } else if (hdspm->system_sample_rate > 48000) {
 
6029
                        levels->speed = ds;
 
6030
                } else {
 
6031
                        levels->speed = ss;
 
6032
                }
 
6033
                levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 
6034
 
 
6035
                s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
 
6036
                if (0 != s) {
 
6037
                        /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
 
6038
                         [Levels]\n", sizeof(struct hdspm_peak_rms), s);
 
6039
                         */
 
6040
                        return -EFAULT;
 
6041
                }
 
6042
                break;
 
6043
 
 
6044
        case SNDRV_HDSPM_IOCTL_GET_LTC:
 
6045
                ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
 
6046
                i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
 
6047
                if (i & HDSPM_TCO1_LTC_Input_valid) {
 
6048
                        switch (i & (HDSPM_TCO1_LTC_Format_LSB |
 
6049
                                HDSPM_TCO1_LTC_Format_MSB)) {
 
6050
                        case 0:
 
6051
                                ltc.format = fps_24;
 
6052
                                break;
 
6053
                        case HDSPM_TCO1_LTC_Format_LSB:
 
6054
                                ltc.format = fps_25;
 
6055
                                break;
 
6056
                        case HDSPM_TCO1_LTC_Format_MSB:
 
6057
                                ltc.format = fps_2997;
 
6058
                                break;
 
6059
                        default:
 
6060
                                ltc.format = 30;
 
6061
                                break;
 
6062
                        }
 
6063
                        if (i & HDSPM_TCO1_set_drop_frame_flag) {
 
6064
                                ltc.frame = drop_frame;
 
6065
                        } else {
 
6066
                                ltc.frame = full_frame;
 
6067
                        }
 
6068
                } else {
 
6069
                        ltc.format = format_invalid;
 
6070
                        ltc.frame = frame_invalid;
 
6071
                }
 
6072
                if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
 
6073
                        ltc.input_format = ntsc;
 
6074
                } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
 
6075
                        ltc.input_format = pal;
 
6076
                } else {
 
6077
                        ltc.input_format = no_video;
 
6078
                }
 
6079
 
 
6080
                s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
 
6081
                if (0 != s) {
 
6082
                        /*
 
6083
                         snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
 
6084
                        return -EFAULT;
 
6085
                }
 
6086
 
 
6087
                break;
 
6088
 
 
6089
        case SNDRV_HDSPM_IOCTL_GET_CONFIG:
4129
6090
 
4130
6091
                memset(&info, 0, sizeof(info));
4131
6092
                spin_lock_irq(&hdspm->lock);
4134
6095
 
4135
6096
                info.system_sample_rate = hdspm->system_sample_rate;
4136
6097
                info.autosync_sample_rate =
4137
 
                    hdspm_external_sample_rate(hdspm);
 
6098
                        hdspm_external_sample_rate(hdspm);
4138
6099
                info.system_clock_mode = hdspm_system_clock_mode(hdspm);
4139
6100
                info.clock_source = hdspm_clock_source(hdspm);
4140
6101
                info.autosync_ref = hdspm_autosync_ref(hdspm);
4145
6106
                        return -EFAULT;
4146
6107
                break;
4147
6108
 
 
6109
        case SNDRV_HDSPM_IOCTL_GET_STATUS:
 
6110
                status.card_type = hdspm->io_type;
 
6111
 
 
6112
                status.autosync_source = hdspm_autosync_ref(hdspm);
 
6113
 
 
6114
                status.card_clock = 110069313433624ULL;
 
6115
                status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
 
6116
 
 
6117
                switch (hdspm->io_type) {
 
6118
                case MADI:
 
6119
                case MADIface:
 
6120
                        status.card_specific.madi.sync_wc =
 
6121
                                hdspm_wc_sync_check(hdspm);
 
6122
                        status.card_specific.madi.sync_madi =
 
6123
                                hdspm_madi_sync_check(hdspm);
 
6124
                        status.card_specific.madi.sync_tco =
 
6125
                                hdspm_tco_sync_check(hdspm);
 
6126
                        status.card_specific.madi.sync_in =
 
6127
                                hdspm_sync_in_sync_check(hdspm);
 
6128
 
 
6129
                        statusregister =
 
6130
                                hdspm_read(hdspm, HDSPM_statusRegister);
 
6131
                        status.card_specific.madi.madi_input =
 
6132
                                (statusregister & HDSPM_AB_int) ? 1 : 0;
 
6133
                        status.card_specific.madi.channel_format =
 
6134
                                (statusregister & HDSPM_TX_64ch) ? 1 : 0;
 
6135
                        /* TODO: Mac driver sets it when f_s>48kHz */
 
6136
                        status.card_specific.madi.frame_format = 0;
 
6137
 
 
6138
                default:
 
6139
                        break;
 
6140
                }
 
6141
 
 
6142
                if (copy_to_user((void __user *) arg, &status, sizeof(status)))
 
6143
                        return -EFAULT;
 
6144
 
 
6145
 
 
6146
                break;
 
6147
 
4148
6148
        case SNDRV_HDSPM_IOCTL_GET_VERSION:
 
6149
                hdspm_version.card_type = hdspm->io_type;
 
6150
                strncpy(hdspm_version.cardname, hdspm->card_name,
 
6151
                                sizeof(hdspm_version.cardname));
 
6152
                hdspm_version.serial = (hdspm_read(hdspm,
 
6153
                                        HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
4149
6154
                hdspm_version.firmware_rev = hdspm->firmware_rev;
 
6155
                hdspm_version.addons = 0;
 
6156
                if (hdspm->tco)
 
6157
                        hdspm_version.addons |= HDSPM_ADDON_TCO;
 
6158
 
4150
6159
                if (copy_to_user((void __user *) arg, &hdspm_version,
4151
 
                                 sizeof(hdspm_version)))
 
6160
                                        sizeof(hdspm_version)))
4152
6161
                        return -EFAULT;
4153
6162
                break;
4154
6163
 
4156
6165
                if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
4157
6166
                        return -EFAULT;
4158
6167
                if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
4159
 
                                 sizeof(struct hdspm_mixer)))
 
6168
                                        sizeof(struct hdspm_mixer)))
4160
6169
                        return -EFAULT;
4161
6170
                break;
4162
6171
 
4175
6184
        .prepare = snd_hdspm_prepare,
4176
6185
        .trigger = snd_hdspm_trigger,
4177
6186
        .pointer = snd_hdspm_hw_pointer,
4178
 
        .copy = snd_hdspm_playback_copy,
4179
 
        .silence = snd_hdspm_hw_silence,
4180
6187
        .page = snd_pcm_sgbuf_ops_page,
4181
6188
};
4182
6189
 
4189
6196
        .prepare = snd_hdspm_prepare,
4190
6197
        .trigger = snd_hdspm_trigger,
4191
6198
        .pointer = snd_hdspm_hw_pointer,
4192
 
        .copy = snd_hdspm_capture_copy,
4193
6199
        .page = snd_pcm_sgbuf_ops_page,
4194
6200
};
4195
6201
 
4207
6213
        hw->private_data = hdspm;
4208
6214
        strcpy(hw->name, "HDSPM hwdep interface");
4209
6215
 
 
6216
        hw->ops.open = snd_hdspm_hwdep_dummy_op;
4210
6217
        hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
 
6218
        hw->ops.release = snd_hdspm_hwdep_dummy_op;
4211
6219
 
4212
6220
        return 0;
4213
6221
}
4214
6222
 
4215
6223
 
4216
6224
/*------------------------------------------------------------
4217
 
   memory interface 
 
6225
   memory interface
4218
6226
 ------------------------------------------------------------*/
4219
 
static int __devinit snd_hdspm_preallocate_memory(struct hdspm * hdspm)
 
6227
static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
4220
6228
{
4221
6229
        int err;
4222
6230
        struct snd_pcm *pcm;
4228
6236
 
4229
6237
        err =
4230
6238
             snd_pcm_lib_preallocate_pages_for_all(pcm,
4231
 
                                                   SNDRV_DMA_TYPE_DEV_SG,
 
6239
                                                   SNDRV_DMA_TYPE_DEV_SG,
4232
6240
                                                   snd_dma_pci_data(hdspm->pci),
4233
6241
                                                   wanted,
4234
6242
                                                   wanted);
4242
6250
        return 0;
4243
6251
}
4244
6252
 
4245
 
static void hdspm_set_sgbuf(struct hdspm * hdspm,
 
6253
 
 
6254
static void hdspm_set_sgbuf(struct hdspm *hdspm,
4246
6255
                            struct snd_pcm_substream *substream,
4247
6256
                             unsigned int reg, int channels)
4248
6257
{
4249
6258
        int i;
 
6259
 
 
6260
        /* continuous memory segment */
4250
6261
        for (i = 0; i < (channels * 16); i++)
4251
6262
                hdspm_write(hdspm, reg + 4 * i,
4252
 
                            snd_pcm_sgbuf_get_addr(substream, 4096 * i));
 
6263
                                snd_pcm_sgbuf_get_addr(substream, 4096 * i));
4253
6264
}
4254
6265
 
 
6266
 
4255
6267
/* ------------- ALSA Devices ---------------------------- */
4256
6268
static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
4257
 
                                          struct hdspm * hdspm)
 
6269
                                          struct hdspm *hdspm)
4258
6270
{
4259
6271
        struct snd_pcm *pcm;
4260
6272
        int err;
4283
6295
 
4284
6296
static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
4285
6297
{
4286
 
        snd_hdspm_flush_midi_input(hdspm, 0);
4287
 
        snd_hdspm_flush_midi_input(hdspm, 1);
 
6298
        int i;
 
6299
 
 
6300
        for (i = 0; i < hdspm->midiPorts; i++)
 
6301
                snd_hdspm_flush_midi_input(hdspm, i);
4288
6302
}
4289
6303
 
4290
6304
static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
4291
6305
                                                   struct hdspm * hdspm)
4292
6306
{
4293
 
        int err;
 
6307
        int err, i;
4294
6308
 
4295
6309
        snd_printdd("Create card...\n");
4296
6310
        err = snd_hdspm_create_pcm(card, hdspm);
4297
6311
        if (err < 0)
4298
6312
                return err;
4299
6313
 
4300
 
        err = snd_hdspm_create_midi(card, hdspm, 0);
4301
 
        if (err < 0)
4302
 
                return err;
4303
 
 
4304
 
        err = snd_hdspm_create_midi(card, hdspm, 1);
4305
 
        if (err < 0)
4306
 
                return err;
 
6314
        i = 0;
 
6315
        while (i < hdspm->midiPorts) {
 
6316
                err = snd_hdspm_create_midi(card, hdspm, i);
 
6317
                if (err < 0) {
 
6318
                        return err;
 
6319
                }
 
6320
                i++;
 
6321
        }
4307
6322
 
4308
6323
        err = snd_hdspm_create_controls(card, hdspm);
4309
6324
        if (err < 0)
4346
6361
}
4347
6362
 
4348
6363
static int __devinit snd_hdspm_create(struct snd_card *card,
4349
 
                                      struct hdspm *hdspm,
4350
 
                                      int precise_ptr, int enable_monitor)
4351
 
{
 
6364
                struct hdspm *hdspm) {
 
6365
 
4352
6366
        struct pci_dev *pci = hdspm->pci;
4353
6367
        int err;
4354
6368
        unsigned long io_extent;
4355
6369
 
4356
6370
        hdspm->irq = -1;
4357
 
 
4358
 
        spin_lock_init(&hdspm->midi[0].lock);
4359
 
        spin_lock_init(&hdspm->midi[1].lock);
4360
 
 
4361
6371
        hdspm->card = card;
4362
6372
 
4363
6373
        spin_lock_init(&hdspm->lock);
4364
6374
 
4365
 
        tasklet_init(&hdspm->midi_tasklet,
4366
 
                     hdspm_midi_tasklet, (unsigned long) hdspm);
4367
 
 
4368
6375
        pci_read_config_word(hdspm->pci,
4369
 
                             PCI_CLASS_REVISION, &hdspm->firmware_rev);
4370
 
 
4371
 
        hdspm->is_aes32 = (hdspm->firmware_rev >= HDSPM_AESREVISION);
 
6376
                        PCI_CLASS_REVISION, &hdspm->firmware_rev);
4372
6377
 
4373
6378
        strcpy(card->mixername, "Xilinx FPGA");
4374
 
        if (hdspm->is_aes32) {
4375
 
                strcpy(card->driver, "HDSPAES32");
4376
 
                hdspm->card_name = "RME HDSPM AES32";
4377
 
        } else {
4378
 
                strcpy(card->driver, "HDSPM");
4379
 
                hdspm->card_name = "RME HDSPM MADI";
 
6379
        strcpy(card->driver, "HDSPM");
 
6380
 
 
6381
        switch (hdspm->firmware_rev) {
 
6382
        case HDSPM_MADI_REV:
 
6383
        case HDSPM_MADI_OLD_REV:
 
6384
                hdspm->io_type = MADI;
 
6385
                hdspm->card_name = "RME MADI";
 
6386
                hdspm->midiPorts = 3;
 
6387
                break;
 
6388
        case HDSPM_RAYDAT_REV:
 
6389
                hdspm->io_type = RayDAT;
 
6390
                hdspm->card_name = "RME RayDAT";
 
6391
                hdspm->midiPorts = 2;
 
6392
                break;
 
6393
        case HDSPM_AIO_REV:
 
6394
                hdspm->io_type = AIO;
 
6395
                hdspm->card_name = "RME AIO";
 
6396
                hdspm->midiPorts = 1;
 
6397
                break;
 
6398
        case HDSPM_MADIFACE_REV:
 
6399
                hdspm->io_type = MADIface;
 
6400
                hdspm->card_name = "RME MADIface";
 
6401
                hdspm->midiPorts = 1;
 
6402
                break;
 
6403
        case HDSPM_AES_REV:
 
6404
        case HDSPM_AES32_REV:
 
6405
        case HDSPM_AES32_OLD_REV:
 
6406
                hdspm->io_type = AES32;
 
6407
                hdspm->card_name = "RME AES32";
 
6408
                hdspm->midiPorts = 2;
 
6409
                break;
 
6410
        default:
 
6411
                snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n",
 
6412
                                hdspm->firmware_rev);
 
6413
                return -ENODEV;
4380
6414
        }
4381
6415
 
4382
6416
        err = pci_enable_device(pci);
4393
6427
        io_extent = pci_resource_len(pci, 0);
4394
6428
 
4395
6429
        snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
4396
 
                   hdspm->port, hdspm->port + io_extent - 1);
4397
 
 
 
6430
                        hdspm->port, hdspm->port + io_extent - 1);
4398
6431
 
4399
6432
        hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
4400
6433
        if (!hdspm->iobase) {
4401
6434
                snd_printk(KERN_ERR "HDSPM: "
4402
 
                           "unable to remap region 0x%lx-0x%lx\n",
4403
 
                           hdspm->port, hdspm->port + io_extent - 1);
 
6435
                                "unable to remap region 0x%lx-0x%lx\n",
 
6436
                                hdspm->port, hdspm->port + io_extent - 1);
4404
6437
                return -EBUSY;
4405
6438
        }
4406
6439
        snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
4407
 
                   (unsigned long)hdspm->iobase, hdspm->port,
4408
 
                   hdspm->port + io_extent - 1);
 
6440
                        (unsigned long)hdspm->iobase, hdspm->port,
 
6441
                        hdspm->port + io_extent - 1);
4409
6442
 
4410
6443
        if (request_irq(pci->irq, snd_hdspm_interrupt,
4411
 
                        IRQF_SHARED, "hdspm", hdspm)) {
 
6444
                                IRQF_SHARED, "hdspm", hdspm)) {
4412
6445
                snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
4413
6446
                return -EBUSY;
4414
6447
        }
4416
6449
        snd_printdd("use IRQ %d\n", pci->irq);
4417
6450
 
4418
6451
        hdspm->irq = pci->irq;
4419
 
        hdspm->precise_ptr = precise_ptr;
4420
 
 
4421
 
        hdspm->monitor_outs = enable_monitor;
4422
6452
 
4423
6453
        snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
4424
 
                   sizeof(struct hdspm_mixer));
 
6454
                        sizeof(struct hdspm_mixer));
4425
6455
        hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
4426
6456
        if (!hdspm->mixer) {
4427
6457
                snd_printk(KERN_ERR "HDSPM: "
4428
 
                           "unable to kmalloc Mixer memory of %d Bytes\n",
4429
 
                           (int)sizeof(struct hdspm_mixer));
 
6458
                                "unable to kmalloc Mixer memory of %d Bytes\n",
 
6459
                                (int)sizeof(struct hdspm_mixer));
4430
6460
                return err;
4431
6461
        }
4432
6462
 
4433
 
        hdspm->ss_channels = MADI_SS_CHANNELS;
4434
 
        hdspm->ds_channels = MADI_DS_CHANNELS;
4435
 
        hdspm->qs_channels = MADI_QS_CHANNELS;
 
6463
        hdspm->port_names_in = NULL;
 
6464
        hdspm->port_names_out = NULL;
 
6465
 
 
6466
        switch (hdspm->io_type) {
 
6467
        case AES32:
 
6468
                hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
 
6469
                hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
 
6470
                hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
 
6471
 
 
6472
                hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
 
6473
                        channel_map_aes32;
 
6474
                hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
 
6475
                        channel_map_aes32;
 
6476
                hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
 
6477
                        channel_map_aes32;
 
6478
                hdspm->port_names_in_ss = hdspm->port_names_out_ss =
 
6479
                        texts_ports_aes32;
 
6480
                hdspm->port_names_in_ds = hdspm->port_names_out_ds =
 
6481
                        texts_ports_aes32;
 
6482
                hdspm->port_names_in_qs = hdspm->port_names_out_qs =
 
6483
                        texts_ports_aes32;
 
6484
 
 
6485
                hdspm->max_channels_out = hdspm->max_channels_in =
 
6486
                        AES32_CHANNELS;
 
6487
                hdspm->port_names_in = hdspm->port_names_out =
 
6488
                        texts_ports_aes32;
 
6489
                hdspm->channel_map_in = hdspm->channel_map_out =
 
6490
                        channel_map_aes32;
 
6491
 
 
6492
                break;
 
6493
 
 
6494
        case MADI:
 
6495
        case MADIface:
 
6496
                hdspm->ss_in_channels = hdspm->ss_out_channels =
 
6497
                        MADI_SS_CHANNELS;
 
6498
                hdspm->ds_in_channels = hdspm->ds_out_channels =
 
6499
                        MADI_DS_CHANNELS;
 
6500
                hdspm->qs_in_channels = hdspm->qs_out_channels =
 
6501
                        MADI_QS_CHANNELS;
 
6502
 
 
6503
                hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
 
6504
                        channel_map_unity_ss;
 
6505
                hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
 
6506
                        channel_map_unity_ss;
 
6507
                hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
 
6508
                        channel_map_unity_ss;
 
6509
 
 
6510
                hdspm->port_names_in_ss = hdspm->port_names_out_ss =
 
6511
                        texts_ports_madi;
 
6512
                hdspm->port_names_in_ds = hdspm->port_names_out_ds =
 
6513
                        texts_ports_madi;
 
6514
                hdspm->port_names_in_qs = hdspm->port_names_out_qs =
 
6515
                        texts_ports_madi;
 
6516
                break;
 
6517
 
 
6518
        case AIO:
 
6519
                if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
 
6520
                        snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
 
6521
                }
 
6522
 
 
6523
                hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
 
6524
                hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
 
6525
                hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
 
6526
                hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
 
6527
                hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
 
6528
                hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
 
6529
 
 
6530
                hdspm->channel_map_out_ss = channel_map_aio_out_ss;
 
6531
                hdspm->channel_map_out_ds = channel_map_aio_out_ds;
 
6532
                hdspm->channel_map_out_qs = channel_map_aio_out_qs;
 
6533
 
 
6534
                hdspm->channel_map_in_ss = channel_map_aio_in_ss;
 
6535
                hdspm->channel_map_in_ds = channel_map_aio_in_ds;
 
6536
                hdspm->channel_map_in_qs = channel_map_aio_in_qs;
 
6537
 
 
6538
                hdspm->port_names_in_ss = texts_ports_aio_in_ss;
 
6539
                hdspm->port_names_out_ss = texts_ports_aio_out_ss;
 
6540
                hdspm->port_names_in_ds = texts_ports_aio_in_ds;
 
6541
                hdspm->port_names_out_ds = texts_ports_aio_out_ds;
 
6542
                hdspm->port_names_in_qs = texts_ports_aio_in_qs;
 
6543
                hdspm->port_names_out_qs = texts_ports_aio_out_qs;
 
6544
 
 
6545
                break;
 
6546
 
 
6547
        case RayDAT:
 
6548
                hdspm->ss_in_channels = hdspm->ss_out_channels =
 
6549
                        RAYDAT_SS_CHANNELS;
 
6550
                hdspm->ds_in_channels = hdspm->ds_out_channels =
 
6551
                        RAYDAT_DS_CHANNELS;
 
6552
                hdspm->qs_in_channels = hdspm->qs_out_channels =
 
6553
                        RAYDAT_QS_CHANNELS;
 
6554
 
 
6555
                hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
 
6556
                hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
 
6557
 
 
6558
                hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
 
6559
                        channel_map_raydat_ss;
 
6560
                hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
 
6561
                        channel_map_raydat_ds;
 
6562
                hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
 
6563
                        channel_map_raydat_qs;
 
6564
                hdspm->channel_map_in = hdspm->channel_map_out =
 
6565
                        channel_map_raydat_ss;
 
6566
 
 
6567
                hdspm->port_names_in_ss = hdspm->port_names_out_ss =
 
6568
                        texts_ports_raydat_ss;
 
6569
                hdspm->port_names_in_ds = hdspm->port_names_out_ds =
 
6570
                        texts_ports_raydat_ds;
 
6571
                hdspm->port_names_in_qs = hdspm->port_names_out_qs =
 
6572
                        texts_ports_raydat_qs;
 
6573
 
 
6574
 
 
6575
                break;
 
6576
 
 
6577
        }
 
6578
 
 
6579
        /* TCO detection */
 
6580
        switch (hdspm->io_type) {
 
6581
        case AIO:
 
6582
        case RayDAT:
 
6583
                if (hdspm_read(hdspm, HDSPM_statusRegister2) &
 
6584
                                HDSPM_s2_tco_detect) {
 
6585
                        hdspm->midiPorts++;
 
6586
                        hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
 
6587
                                        GFP_KERNEL);
 
6588
                        if (NULL != hdspm->tco) {
 
6589
                                hdspm_tco_write(hdspm);
 
6590
                        }
 
6591
                        snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
 
6592
                } else {
 
6593
                        hdspm->tco = NULL;
 
6594
                }
 
6595
                break;
 
6596
 
 
6597
        case MADI:
 
6598
                if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
 
6599
                        hdspm->midiPorts++;
 
6600
                        hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
 
6601
                                        GFP_KERNEL);
 
6602
                        if (NULL != hdspm->tco) {
 
6603
                                hdspm_tco_write(hdspm);
 
6604
                        }
 
6605
                        snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
 
6606
                } else {
 
6607
                        hdspm->tco = NULL;
 
6608
                }
 
6609
                break;
 
6610
 
 
6611
        default:
 
6612
                hdspm->tco = NULL;
 
6613
        }
 
6614
 
 
6615
        /* texts */
 
6616
        switch (hdspm->io_type) {
 
6617
        case AES32:
 
6618
                if (hdspm->tco) {
 
6619
                        hdspm->texts_autosync = texts_autosync_aes_tco;
 
6620
                        hdspm->texts_autosync_items = 10;
 
6621
                } else {
 
6622
                        hdspm->texts_autosync = texts_autosync_aes;
 
6623
                        hdspm->texts_autosync_items = 9;
 
6624
                }
 
6625
                break;
 
6626
 
 
6627
        case MADI:
 
6628
                if (hdspm->tco) {
 
6629
                        hdspm->texts_autosync = texts_autosync_madi_tco;
 
6630
                        hdspm->texts_autosync_items = 4;
 
6631
                } else {
 
6632
                        hdspm->texts_autosync = texts_autosync_madi;
 
6633
                        hdspm->texts_autosync_items = 3;
 
6634
                }
 
6635
                break;
 
6636
 
 
6637
        case MADIface:
 
6638
 
 
6639
                break;
 
6640
 
 
6641
        case RayDAT:
 
6642
                if (hdspm->tco) {
 
6643
                        hdspm->texts_autosync = texts_autosync_raydat_tco;
 
6644
                        hdspm->texts_autosync_items = 9;
 
6645
                } else {
 
6646
                        hdspm->texts_autosync = texts_autosync_raydat;
 
6647
                        hdspm->texts_autosync_items = 8;
 
6648
                }
 
6649
                break;
 
6650
 
 
6651
        case AIO:
 
6652
                if (hdspm->tco) {
 
6653
                        hdspm->texts_autosync = texts_autosync_aio_tco;
 
6654
                        hdspm->texts_autosync_items = 6;
 
6655
                } else {
 
6656
                        hdspm->texts_autosync = texts_autosync_aio;
 
6657
                        hdspm->texts_autosync_items = 5;
 
6658
                }
 
6659
                break;
 
6660
 
 
6661
        }
 
6662
 
 
6663
        tasklet_init(&hdspm->midi_tasklet,
 
6664
                        hdspm_midi_tasklet, (unsigned long) hdspm);
4436
6665
 
4437
6666
        snd_printdd("create alsa devices.\n");
4438
6667
        err = snd_hdspm_create_alsa_devices(card, hdspm);
4444
6673
        return 0;
4445
6674
}
4446
6675
 
 
6676
 
4447
6677
static int snd_hdspm_free(struct hdspm * hdspm)
4448
6678
{
4449
6679
 
4452
6682
                /* stop th audio, and cancel all interrupts */
4453
6683
                hdspm->control_register &=
4454
6684
                    ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
4455
 
                      HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable);
 
6685
                      HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
 
6686
                      HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
4456
6687
                hdspm_write(hdspm, HDSPM_controlRegister,
4457
6688
                            hdspm->control_register);
4458
6689
        }
4472
6703
        return 0;
4473
6704
}
4474
6705
 
 
6706
 
4475
6707
static void snd_hdspm_card_free(struct snd_card *card)
4476
6708
{
4477
6709
        struct hdspm *hdspm = card->private_data;
4480
6712
                snd_hdspm_free(hdspm);
4481
6713
}
4482
6714
 
 
6715
 
4483
6716
static int __devinit snd_hdspm_probe(struct pci_dev *pci,
4484
6717
                                     const struct pci_device_id *pci_id)
4485
6718
{
4496
6729
        }
4497
6730
 
4498
6731
        err = snd_card_create(index[dev], id[dev],
4499
 
                              THIS_MODULE, sizeof(struct hdspm), &card);
 
6732
                        THIS_MODULE, sizeof(struct hdspm), &card);
4500
6733
        if (err < 0)
4501
6734
                return err;
4502
6735
 
4507
6740
 
4508
6741
        snd_card_set_dev(card, &pci->dev);
4509
6742
 
4510
 
        err = snd_hdspm_create(card, hdspm, precise_ptr[dev],
4511
 
                               enable_monitor[dev]);
 
6743
        err = snd_hdspm_create(card, hdspm);
4512
6744
        if (err < 0) {
4513
6745
                snd_card_free(card);
4514
6746
                return err;
4515
6747
        }
4516
6748
 
4517
 
        strcpy(card->shortname, "HDSPM MADI");
4518
 
        sprintf(card->longname, "%s at 0x%lx, irq %d", hdspm->card_name,
4519
 
                hdspm->port, hdspm->irq);
 
6749
        if (hdspm->io_type != MADIface) {
 
6750
                sprintf(card->shortname, "%s_%x",
 
6751
                        hdspm->card_name,
 
6752
                        (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
 
6753
                sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
 
6754
                        hdspm->card_name,
 
6755
                        (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
 
6756
                        hdspm->port, hdspm->irq);
 
6757
        } else {
 
6758
                sprintf(card->shortname, "%s", hdspm->card_name);
 
6759
                sprintf(card->longname, "%s at 0x%lx, irq %d",
 
6760
                                hdspm->card_name, hdspm->port, hdspm->irq);
 
6761
        }
4520
6762
 
4521
6763
        err = snd_card_register(card);
4522
6764
        if (err < 0) {