← Back to branch summary

~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise

« back to all changes in this revision

Viewing changes to drivers/staging/brcm80211/brcmfmac/dhd_sdio.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

Show diffs side-by-side

added added

removed removed

Lines of Context:
drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
15
15
 */
16
16
 
17
17
#include <linux/types.h>
18
 
#include <bcmdefs.h>
 
18
#include <linux/kernel.h>
 
19
#include <linux/printk.h>
 
20
#include <linux/pci_ids.h>
19
21
#include <linux/netdevice.h>
20
 
#include <osl.h>
 
22
#include <bcmdefs.h>
21
23
#include <bcmsdh.h>
22
24
 
23
25
#ifdef BCMEMBEDIMAGE
26
28
 
27
29
#include <bcmdefs.h>
28
30
#include <bcmutils.h>
29
 
#include <bcmendian.h>
30
31
#include <bcmdevs.h>
31
32
 
32
 
#include <siutils.h>
33
 
#include <hndpmu.h>
34
33
#include <hndsoc.h>
35
34
#ifdef DHD_DEBUG
36
35
#include <hndrte_armtrap.h>
44
43
#include <sbsdpcmdev.h>
45
44
#include <bcmsdpcm.h>
46
45
 
47
 
#include <proto/ethernet.h>
48
 
#include <proto/802.1d.h>
49
46
#include <proto/802.11.h>
50
47
 
51
48
#include <dngl_stats.h>
55
52
#include <dhd_dbg.h>
56
53
#include <dhdioctl.h>
57
54
#include <sdiovar.h>
58
 
#include <siutils_priv.h>
 
55
#include <bcmchip.h>
59
56
 
60
57
#ifndef DHDSDIO_MEM_DUMP_FNAME
61
58
#define DHDSDIO_MEM_DUMP_FNAME         "mem_dump"
62
59
#endif
63
60
 
64
 
#define QLEN            256     /* bulk rx and tx queue lengths */
65
 
#define FCHI            (QLEN - 10)
66
 
#define FCLOW           (FCHI / 2)
 
61
#define TXQLEN          2048    /* bulk tx queue length */
 
62
#define TXHI            (TXQLEN - 256)  /* turn on flow control above TXHI */
 
63
#define TXLOW           (TXHI - 256)    /* turn off flow control below TXLOW */
67
64
#define PRIOMASK        7
68
65
 
69
66
#define TXRETRIES       2       /* # of retries for tx frames */
140
137
/* Flags for SDH calls */
141
138
#define F2SYNC  (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
142
139
 
143
 
/* Packet free applicable unconditionally for sdio and sdspi.  Conditional if
144
 
 * bufpool was present for gspi bus.
 
140
/*
 
141
 * Conversion of 802.1D priority to precedence level
145
142
 */
146
 
#define PKTFREE2()              if ((bus->bus != SPI_BUS) || bus->usebufpool) \
147
 
                                                        pkt_buf_free_skb(bus->dhd->osh, pkt, false);
 
143
#define PRIO2PREC(prio) \
 
144
        (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
 
145
        ((prio^2)) : (prio))
 
146
 
148
147
DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
149
148
extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
150
149
                            uint len);
161
160
} dhd_console_t;
162
161
#endif                          /* DHD_DEBUG */
163
162
 
 
163
/* misc chip info needed by some of the routines */
 
164
struct chip_info {
 
165
        u32 chip;
 
166
        u32 chiprev;
 
167
        u32 cccorebase;
 
168
        u32 ccrev;
 
169
        u32 cccaps;
 
170
        u32 buscorebase;
 
171
        u32 buscorerev;
 
172
        u32 buscoretype;
 
173
        u32 ramcorebase;
 
174
        u32 armcorebase;
 
175
        u32 pmurev;
 
176
        u32 ramsize;
 
177
};
 
178
 
164
179
/* Private data for SDIO bus interaction */
165
180
typedef struct dhd_bus {
166
181
        dhd_pub_t *dhd;
167
182
 
168
183
        bcmsdh_info_t *sdh;     /* Handle for BCMSDH calls */
169
 
        si_t *sih;              /* Handle for SI calls */
 
184
        struct chip_info *ci;   /* Chip info struct */
170
185
        char *vars;             /* Variables (from CIS and/or other) */
171
186
        uint varsz;             /* Size of variables buffer */
172
187
        u32 sbaddr;             /* Current SB window pointer (-1, invalid) */
329
344
#define DONGLE_MIN_MEMSIZE (128 * 1024)
330
345
int dhd_dongle_memsize;
331
346
 
332
 
static bool dhd_doflow;
333
347
static bool dhd_alignctl;
334
348
 
335
349
static bool sd1idle;
357
371
#if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
358
372
#error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
359
373
#endif  /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
360
 
#define PKTALIGN(_osh, _p, _len, _align)                                \
 
374
#define PKTALIGN(_p, _len, _align)                              \
361
375
        do {                                                            \
362
376
                uint datalign;                                          \
363
377
                datalign = (unsigned long)((_p)->data);                 \
386
400
do { \
387
401
        retryvar = 0; \
388
402
        do { \
389
 
                regvar = R_REG(bus->dhd->osh, regaddr); \
 
403
                regvar = R_REG(regaddr); \
390
404
        } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
391
405
        if (retryvar) { \
392
406
                bus->regfails += (retryvar-1); \
402
416
do { \
403
417
        retryvar = 0; \
404
418
        do { \
405
 
                W_REG(bus->dhd->osh, regaddr, regval); \
 
419
                W_REG(regaddr, regval); \
406
420
        } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
407
421
        if (retryvar) { \
408
422
                bus->regfails += (retryvar-1); \
418
432
 
419
433
#define HOSTINTMASK             (I_HMB_SW_MASK | I_CHIPACTIVE)
420
434
 
421
 
#define GSPI_PR55150_BAILOUT
422
 
 
423
435
#ifdef SDTEST
424
436
static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
425
437
static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
431
443
#endif                          /* DHD_DEBUG  */
432
444
static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
433
445
 
434
 
static void dhdsdio_release(dhd_bus_t *bus, struct osl_info *osh);
435
 
static void dhdsdio_release_malloc(dhd_bus_t *bus, struct osl_info *osh);
 
446
static void dhdsdio_release(dhd_bus_t *bus);
 
447
static void dhdsdio_release_malloc(dhd_bus_t *bus);
436
448
static void dhdsdio_disconnect(void *ptr);
437
449
static bool dhdsdio_chipmatch(u16 chipid);
438
 
static bool dhdsdio_probe_attach(dhd_bus_t *bus, struct osl_info *osh,
439
 
                                 void *sdh, void *regsva, u16 devid);
440
 
static bool dhdsdio_probe_malloc(dhd_bus_t *bus, struct osl_info *osh,
441
 
                                 void *sdh);
442
 
static bool dhdsdio_probe_init(dhd_bus_t *bus, struct osl_info *osh, void *sdh);
443
 
static void dhdsdio_release_dongle(dhd_bus_t *bus, struct osl_info * osh);
 
450
static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
 
451
                                 void *regsva, u16 devid);
 
452
static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
 
453
static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
 
454
static void dhdsdio_release_dongle(dhd_bus_t *bus);
444
455
 
445
456
static uint process_nvram_vars(char *varbuf, uint len);
446
457
 
447
458
static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
448
 
static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
449
 
                               uint flags, u8 *buf, uint nbytes,
450
 
                               struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
451
 
                               void *handle);
452
459
static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
453
460
                               uint flags, u8 *buf, uint nbytes,
454
461
                               struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
455
462
                               void *handle);
456
463
 
457
 
static bool dhdsdio_download_firmware(struct dhd_bus *bus, struct osl_info *osh,
458
 
                                      void *sdh);
 
464
static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
459
465
static int _dhdsdio_download_firmware(struct dhd_bus *bus);
460
466
 
461
467
static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
463
469
#ifdef BCMEMBEDIMAGE
464
470
static int dhdsdio_download_code_array(struct dhd_bus *bus);
465
471
#endif
 
472
static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
 
473
static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
 
474
static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
 
475
static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
 
476
                                        u32 drivestrength);
 
477
static void dhdsdio_chip_detach(struct dhd_bus *bus);
 
478
 
 
479
/* Packet free applicable unconditionally for sdio and sdspi.
 
480
 * Conditional if bufpool was present for gspi bus.
 
481
 */
 
482
static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
 
483
{
 
484
        dhd_os_sdlock_rxq(bus->dhd);
 
485
        if ((bus->bus != SPI_BUS) || bus->usebufpool)
 
486
                bcm_pkt_buf_free_skb(pkt);
 
487
        dhd_os_sdunlock_rxq(bus->dhd);
 
488
}
466
489
 
467
490
static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
468
491
{
510
533
                clkreq =
511
534
                    bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
512
535
 
513
 
                if ((bus->sih->chip == BCM4329_CHIP_ID)
514
 
                    && (bus->sih->chiprev == 0))
 
536
                if ((bus->ci->chip == BCM4329_CHIP_ID)
 
537
                    && (bus->ci->chiprev == 0))
515
538
                        clkreq |= SBSDIO_FORCE_ALP;
516
539
 
517
540
                bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
519
542
                if (err) {
520
543
                        DHD_ERROR(("%s: HT Avail request error: %d\n",
521
544
                                   __func__, err));
522
 
                        return BCME_ERROR;
 
545
                        return -EBADE;
523
546
                }
524
547
 
525
 
                if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
526
 
                               && (bus->sih->buscorerev == 9))) {
 
548
                if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
 
549
                               && (bus->ci->buscorerev == 9))) {
527
550
                        u32 dummy, retries;
528
551
                        R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
529
552
                }
535
558
                if (err) {
536
559
                        DHD_ERROR(("%s: HT Avail read error: %d\n",
537
560
                                   __func__, err));
538
 
                        return BCME_ERROR;
 
561
                        return -EBADE;
539
562
                }
540
563
 
541
564
                /* Go to pending and await interrupt if appropriate */
547
570
                        if (err) {
548
571
                                DHD_ERROR(("%s: Devctl error setting CA: %d\n",
549
572
                                        __func__, err));
550
 
                                return BCME_ERROR;
 
573
                                return -EBADE;
551
574
                        }
552
575
 
553
576
                        devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
556
579
                        DHD_INFO(("CLKCTL: set PENDING\n"));
557
580
                        bus->clkstate = CLK_PENDING;
558
581
 
559
 
                        return BCME_OK;
 
582
                        return 0;
560
583
                } else if (bus->clkstate == CLK_PENDING) {
561
584
                        /* Cancel CA-only interrupt filter */
562
585
                        devctl =
580
603
                if (err) {
581
604
                        DHD_ERROR(("%s: HT Avail request error: %d\n",
582
605
                                   __func__, err));
583
 
                        return BCME_ERROR;
 
606
                        return -EBADE;
584
607
                }
585
608
                if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
586
609
                        DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
587
610
                                   __func__, PMU_MAX_TRANSITION_DLY, clkctl));
588
 
                        return BCME_ERROR;
 
611
                        return -EBADE;
589
612
                }
590
613
 
591
614
                /* Mark clock available */
629
652
                if (err) {
630
653
                        DHD_ERROR(("%s: Failed access turning clock off: %d\n",
631
654
                                   __func__, err));
632
 
                        return BCME_ERROR;
 
655
                        return -EBADE;
633
656
                }
634
657
        }
635
 
        return BCME_OK;
 
658
        return 0;
636
659
}
637
660
 
638
661
/* Change idle/active SD state */
652
675
                        if (err) {
653
676
                                DHD_ERROR(("%s: error enabling sd_clock: %d\n",
654
677
                                           __func__, err));
655
 
                                return BCME_ERROR;
 
678
                                return -EBADE;
656
679
                        }
657
680
 
658
681
                        iovalue = bus->sd_mode;
661
684
                        if (err) {
662
685
                                DHD_ERROR(("%s: error changing sd_mode: %d\n",
663
686
                                           __func__, err));
664
 
                                return BCME_ERROR;
 
687
                                return -EBADE;
665
688
                        }
666
689
                } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
667
690
                        /* Restore clock speed */
671
694
                        if (err) {
672
695
                                DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
673
696
                                        __func__, err));
674
 
                                return BCME_ERROR;
 
697
                                return -EBADE;
675
698
                        }
676
699
                }
677
700
                bus->clkstate = CLK_SDONLY;
680
703
                if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
681
704
                        DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
682
705
                                   __func__, bus->sd_divisor, bus->sd_mode));
683
 
                        return BCME_ERROR;
 
706
                        return -EBADE;
684
707
                }
685
708
                if (bus->idleclock == DHD_IDLE_STOP) {
686
709
                        if (sd1idle) {
693
716
                                if (err) {
694
717
                                        DHD_ERROR(("%s: error changing sd_clock: %d\n",
695
718
                                                __func__, err));
696
 
                                        return BCME_ERROR;
 
719
                                        return -EBADE;
697
720
                                }
698
721
                        }
699
722
 
703
726
                        if (err) {
704
727
                                DHD_ERROR(("%s: error disabling sd_clock: %d\n",
705
728
                                           __func__, err));
706
 
                                return BCME_ERROR;
 
729
                                return -EBADE;
707
730
                        }
708
731
                } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
709
732
                        /* Set divisor to idle value */
713
736
                        if (err) {
714
737
                                DHD_ERROR(("%s: error changing sd_divisor: %d\n",
715
738
                                        __func__, err));
716
 
                                return BCME_ERROR;
 
739
                                return -EBADE;
717
740
                        }
718
741
                }
719
742
                bus->clkstate = CLK_NONE;
720
743
        }
721
744
 
722
 
        return BCME_OK;
 
745
        return 0;
723
746
}
724
747
 
725
748
/* Transition SD and backplane clock readiness */
737
760
                        dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
738
761
                        bus->activity = true;
739
762
                }
740
 
                return BCME_OK;
 
763
                return 0;
741
764
        }
742
765
 
743
766
        switch (target) {
776
799
        DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
777
800
#endif                          /* DHD_DEBUG */
778
801
 
779
 
        return BCME_OK;
 
802
        return 0;
780
803
}
781
804
 
782
805
int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
791
814
 
792
815
        /* Done if we're already in the requested state */
793
816
        if (sleep == bus->sleeping)
794
 
                return BCME_OK;
 
817
                return 0;
795
818
 
796
819
        /* Going to sleep: set the alarm and turn off the lights... */
797
820
        if (sleep) {
798
821
                /* Don't sleep if something is pending */
799
822
                if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
800
 
                        return BCME_BUSY;
 
823
                        return -EBUSY;
801
824
 
802
825
                /* Disable SDIO interrupts (no longer interested) */
803
826
                bcmsdh_intr_disable(bus->sdh);
817
840
                                 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
818
841
 
819
842
                /* Isolate the bus */
820
 
                if (bus->sih->chip != BCM4329_CHIP_ID
821
 
                    && bus->sih->chip != BCM4319_CHIP_ID) {
 
843
                if (bus->ci->chip != BCM4329_CHIP_ID
 
844
                    && bus->ci->chip != BCM4319_CHIP_ID) {
822
845
                        bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
823
846
                                         SBSDIO_DEVCTL_PADS_ISO, NULL);
824
847
                }
834
857
 
835
858
                /* Force pad isolation off if possible
836
859
                         (in case power never toggled) */
837
 
                if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
838
 
                    && (bus->sih->buscorerev >= 10))
 
860
                if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
 
861
                    && (bus->ci->buscorerev >= 10))
839
862
                        bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
840
863
                                         NULL);
841
864
 
863
886
                }
864
887
        }
865
888
 
866
 
        return BCME_OK;
 
889
        return 0;
867
890
}
868
891
 
869
892
#if defined(OOB_INTR_ONLY)
908
931
                         bool free_pkt)
909
932
{
910
933
        int ret;
911
 
        struct osl_info *osh;
912
934
        u8 *frame;
913
935
        u16 len, pad = 0;
914
936
        u32 swheader;
920
942
        DHD_TRACE(("%s: Enter\n", __func__));
921
943
 
922
944
        sdh = bus->sdh;
923
 
        osh = bus->dhd->osh;
924
945
 
925
946
        if (bus->dhd->dongle_reset) {
926
 
                ret = BCME_NOTREADY;
 
947
                ret = -EPERM;
927
948
                goto done;
928
949
        }
929
950
 
936
957
                        DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
937
958
                                  __func__, skb_headroom(pkt), pad));
938
959
                        bus->dhd->tx_realloc++;
939
 
                        new = pkt_buf_get_skb(osh, (pkt->len + DHD_SDALIGN));
 
960
                        new = bcm_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
940
961
                        if (!new) {
941
962
                                DHD_ERROR(("%s: couldn't allocate new %d-byte "
942
963
                                        "packet\n",
943
964
                                        __func__, pkt->len + DHD_SDALIGN));
944
 
                                ret = BCME_NOMEM;
 
965
                                ret = -ENOMEM;
945
966
                                goto done;
946
967
                        }
947
968
 
948
 
                        PKTALIGN(osh, new, pkt->len, DHD_SDALIGN);
949
 
                        bcopy(pkt->data, new->data, pkt->len);
 
969
                        PKTALIGN(new, pkt->len, DHD_SDALIGN);
 
970
                        memcpy(new->data, pkt->data, pkt->len);
950
971
                        if (free_pkt)
951
 
                                pkt_buf_free_skb(osh, pkt, true);
 
972
                                bcm_pkt_buf_free_skb(pkt);
952
973
                        /* free the pkt if canned one is not used */
953
974
                        free_pkt = true;
954
975
                        pkt = new;
967
988
 
968
989
        /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
969
990
        len = (u16) (pkt->len);
970
 
        *(u16 *) frame = htol16(len);
971
 
        *(((u16 *) frame) + 1) = htol16(~len);
 
991
        *(u16 *) frame = cpu_to_le16(len);
 
992
        *(((u16 *) frame) + 1) = cpu_to_le16(~len);
972
993
 
973
994
        /* Software tag: channel, sequence number, data offset */
974
995
        swheader =
975
996
            ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
976
997
            (((pad +
977
998
               SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
978
 
        htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
979
 
        htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
 
999
 
 
1000
        put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
 
1001
        put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
980
1002
 
981
1003
#ifdef DHD_DEBUG
982
1004
        tx_packets[pkt->priority]++;
983
1005
        if (DHD_BYTES_ON() &&
984
1006
            (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
985
1007
              (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
986
 
                prhex("Tx Frame", frame, len);
 
1008
                printk(KERN_DEBUG "Tx Frame:\n");
 
1009
                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
987
1010
        } else if (DHD_HDRS_ON()) {
988
 
                prhex("TxHdr", frame, min_t(u16, len, 16));
 
1011
                printk(KERN_DEBUG "TxHdr:\n");
 
1012
                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
1013
                                     frame, min_t(u16, len, 16));
989
1014
        }
990
1015
#endif
991
1016
 
1019
1044
                    dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1020
1045
                                        F2SYNC, frame, len, pkt, NULL, NULL);
1021
1046
                bus->f2txdata++;
1022
 
                ASSERT(ret != BCME_PENDING);
 
1047
                ASSERT(ret != -BCME_PENDING);
1023
1048
 
1024
1049
                if (ret < 0) {
1025
1050
                        /* On failure, abort the command
1061
1086
        dhd_os_sdlock(bus->dhd);
1062
1087
 
1063
1088
        if (free_pkt)
1064
 
                pkt_buf_free_skb(osh, pkt, true);
 
1089
                bcm_pkt_buf_free_skb(pkt);
1065
1090
 
1066
1091
        return ret;
1067
1092
}
1068
1093
 
1069
1094
int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1070
1095
{
1071
 
        int ret = BCME_ERROR;
1072
 
        struct osl_info *osh;
 
1096
        int ret = -EBADE;
1073
1097
        uint datalen, prec;
1074
1098
 
1075
1099
        DHD_TRACE(("%s: Enter\n", __func__));
1076
1100
 
1077
 
        osh = bus->dhd->osh;
1078
1101
        datalen = pkt->len;
1079
1102
 
1080
1103
#ifdef SDTEST
1112
1135
                if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1113
1136
                        skb_pull(pkt, SDPCM_HDRLEN);
1114
1137
                        dhd_txcomplete(bus->dhd, pkt, false);
1115
 
                        pkt_buf_free_skb(osh, pkt, true);
 
1138
                        bcm_pkt_buf_free_skb(pkt);
1116
1139
                        DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1117
 
                        ret = BCME_NORESOURCE;
 
1140
                        ret = -ENOSR;
1118
1141
                } else {
1119
 
                        ret = BCME_OK;
 
1142
                        ret = 0;
1120
1143
                }
1121
1144
                dhd_os_sdunlock_txq(bus->dhd);
1122
1145
 
1123
 
                if ((pktq_len(&bus->txq) >= FCHI) && dhd_doflow)
 
1146
                if (pktq_len(&bus->txq) >= TXHI)
1124
1147
                        dhd_txflowcontrol(bus->dhd, 0, ON);
1125
1148
 
1126
1149
#ifdef DHD_DEBUG
1185
1208
        /* Send frames until the limit or some other event */
1186
1209
        for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1187
1210
                dhd_os_sdlock_txq(bus->dhd);
1188
 
                pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
 
1211
                pkt = bcm_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1189
1212
                if (pkt == NULL) {
1190
1213
                        dhd_os_sdunlock_txq(bus->dhd);
1191
1214
                        break;
1218
1241
        }
1219
1242
 
1220
1243
        /* Deflow-control stack if needed */
1221
 
        if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1222
 
            dhd->txoff && (pktq_len(&bus->txq) < FCLOW))
 
1244
        if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
 
1245
            dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1223
1246
                dhd_txflowcontrol(dhd, 0, OFF);
1224
1247
 
1225
1248
        return cnt;
1282
1305
        dhdsdio_clkctl(bus, CLK_AVAIL, false);
1283
1306
 
1284
1307
        /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1285
 
        *(u16 *) frame = htol16((u16) msglen);
1286
 
        *(((u16 *) frame) + 1) = htol16(~msglen);
 
1308
        *(u16 *) frame = cpu_to_le16((u16) msglen);
 
1309
        *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1287
1310
 
1288
1311
        /* Software tag: channel, sequence number, data offset */
1289
1312
        swheader =
1291
1314
             SDPCM_CHANNEL_MASK)
1292
1315
            | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1293
1316
                             SDPCM_DOFFSET_MASK);
1294
 
        htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1295
 
        htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
 
1317
        put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
 
1318
        put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1296
1319
 
1297
1320
        if (!DATAOK(bus)) {
1298
1321
                DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1315
1338
 
1316
1339
        if (ret == -1) {
1317
1340
#ifdef DHD_DEBUG
1318
 
                if (DHD_BYTES_ON() && DHD_CTL_ON())
1319
 
                        prhex("Tx Frame", frame, len);
1320
 
                else if (DHD_HDRS_ON())
1321
 
                        prhex("TxHdr", frame, min_t(u16, len, 16));
 
1341
                if (DHD_BYTES_ON() && DHD_CTL_ON()) {
 
1342
                        printk(KERN_DEBUG "Tx Frame:\n");
 
1343
                        print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
1344
                                             frame, len);
 
1345
                } else if (DHD_HDRS_ON()) {
 
1346
                        printk(KERN_DEBUG "TxHdr:\n");
 
1347
                        print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
1348
                                             frame, min_t(u16, len, 16));
 
1349
                }
1322
1350
#endif
1323
1351
 
1324
1352
                do {
1328
1356
                                                SDIO_FUNC_2, F2SYNC, frame, len,
1329
1357
                                                NULL, NULL, NULL);
1330
1358
 
1331
 
                        ASSERT(ret != BCME_PENDING);
 
1359
                        ASSERT(ret != -BCME_PENDING);
1332
1360
 
1333
1361
                        if (ret < 0) {
1334
1362
                                /* On failure, abort the command and
1396
1424
 
1397
1425
        dhd_os_sdlock(bus->dhd);
1398
1426
        rxlen = bus->rxlen;
1399
 
        bcopy(bus->rxctl, msg, min(msglen, rxlen));
 
1427
        memcpy(msg, bus->rxctl, min(msglen, rxlen));
1400
1428
        bus->rxlen = 0;
1401
1429
        dhd_os_sdunlock(bus->dhd);
1402
1430
 
1659
1687
        pktgen.mode = bus->pktgen_mode;
1660
1688
        pktgen.stop = bus->pktgen_stop;
1661
1689
 
1662
 
        bcopy(&pktgen, arg, sizeof(pktgen));
 
1690
        memcpy(arg, &pktgen, sizeof(pktgen));
1663
1691
 
1664
1692
        return 0;
1665
1693
}
1669
1697
        dhd_pktgen_t pktgen;
1670
1698
        uint oldcnt, oldmode;
1671
1699
 
1672
 
        bcopy(arg, &pktgen, sizeof(pktgen));
 
1700
        memcpy(&pktgen, arg, sizeof(pktgen));
1673
1701
        if (pktgen.version != DHD_PKTGEN_VERSION)
1674
 
                return BCME_BADARG;
 
1702
                return -EINVAL;
1675
1703
 
1676
1704
        oldcnt = bus->pktgen_count;
1677
1705
        oldmode = bus->pktgen_mode;
1769
1797
        if (rv < 0)
1770
1798
                return rv;
1771
1799
 
1772
 
        addr = ltoh32(addr);
 
1800
        addr = le32_to_cpu(addr);
1773
1801
 
1774
1802
        DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1775
1803
 
1780
1808
        if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1781
1809
                DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1782
1810
                           __func__, addr));
1783
 
                return BCME_ERROR;
 
1811
                return -EBADE;
1784
1812
        }
1785
1813
 
1786
1814
        /* Read hndrte_shared structure */
1790
1818
                return rv;
1791
1819
 
1792
1820
        /* Endianness */
1793
 
        sh->flags = ltoh32(sh->flags);
1794
 
        sh->trap_addr = ltoh32(sh->trap_addr);
1795
 
        sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
1796
 
        sh->assert_file_addr = ltoh32(sh->assert_file_addr);
1797
 
        sh->assert_line = ltoh32(sh->assert_line);
1798
 
        sh->console_addr = ltoh32(sh->console_addr);
1799
 
        sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
 
1821
        sh->flags = le32_to_cpu(sh->flags);
 
1822
        sh->trap_addr = le32_to_cpu(sh->trap_addr);
 
1823
        sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
 
1824
        sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
 
1825
        sh->assert_line = le32_to_cpu(sh->assert_line);
 
1826
        sh->console_addr = le32_to_cpu(sh->console_addr);
 
1827
        sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
1800
1828
 
1801
1829
        if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1802
1830
                DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1803
1831
                           "is different than sdpcm_shared version %d in dongle\n",
1804
1832
                           __func__, SDPCM_SHARED_VERSION,
1805
1833
                           sh->flags & SDPCM_SHARED_VERSION_MASK));
1806
 
                return BCME_ERROR;
 
1834
                return -EBADE;
1807
1835
        }
1808
1836
 
1809
 
        return BCME_OK;
 
1837
        return 0;
1810
1838
}
1811
1839
 
1812
1840
static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1832
1860
                if (mbuffer == NULL) {
1833
1861
                        DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1834
1862
                                   msize));
1835
 
                        bcmerror = BCME_NOMEM;
 
1863
                        bcmerror = -ENOMEM;
1836
1864
                        goto done;
1837
1865
                }
1838
1866
        }
1840
1868
        str = kmalloc(maxstrlen, GFP_ATOMIC);
1841
1869
        if (str == NULL) {
1842
1870
                DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1843
 
                bcmerror = BCME_NOMEM;
 
1871
                bcmerror = -ENOMEM;
1844
1872
                goto done;
1845
1873
        }
1846
1874
 
1932
1960
#endif                          /* DHD_DEBUG */
1933
1961
 
1934
1962
done:
1935
 
        if (mbuffer)
1936
 
                kfree(mbuffer);
1937
 
        if (str)
1938
 
                kfree(str);
 
1963
        kfree(mbuffer);
 
1964
        kfree(str);
1939
1965
 
1940
1966
        return bcmerror;
1941
1967
}
1952
1978
        size = bus->ramsize;
1953
1979
        buf = kmalloc(size, GFP_ATOMIC);
1954
1980
        if (!buf) {
1955
 
                printf("%s: Out of memory (%d bytes)\n", __func__, size);
 
1981
                DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
1956
1982
                return -1;
1957
1983
        }
1958
1984
 
1959
1985
        /* Read mem content */
1960
 
        printf("Dump dongle memory");
 
1986
        printk(KERN_DEBUG "Dump dongle memory");
1961
1987
        databuf = buf;
1962
1988
        while (size) {
1963
1989
                read_size = min(MEMBLOCK, size);
1964
1990
                ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
1965
1991
                if (ret) {
1966
 
                        printf("%s: Error membytes %d\n", __func__, ret);
1967
 
                        if (buf)
1968
 
                                kfree(buf);
 
1992
                        DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
 
1993
                        kfree(buf);
1969
1994
                        return -1;
1970
1995
                }
1971
 
                printf(".");
 
1996
                printk(".");
1972
1997
 
1973
1998
                /* Decrement size and increment start address */
1974
1999
                size -= read_size;
1975
2000
                start += read_size;
1976
2001
                databuf += read_size;
1977
2002
        }
1978
 
        printf("Done\n");
 
2003
        printk(KERN_DEBUG "Done\n");
1979
2004
 
1980
2005
        /* free buf before return !!! */
1981
2006
        if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1982
 
                printf("%s: Error writing to files\n", __func__);
 
2007
                DHD_ERROR(("%s: Error writing to files\n", __func__));
1983
2008
                return -1;
1984
2009
        }
1985
2010
 
2009
2034
 
2010
2035
        /* Allocate console buffer (one time only) */
2011
2036
        if (c->buf == NULL) {
2012
 
                c->bufsize = ltoh32(c->log.buf_size);
 
2037
                c->bufsize = le32_to_cpu(c->log.buf_size);
2013
2038
                c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2014
2039
                if (c->buf == NULL)
2015
 
                        return BCME_NOMEM;
 
2040
                        return -ENOMEM;
2016
2041
        }
2017
2042
 
2018
 
        idx = ltoh32(c->log.idx);
 
2043
        idx = le32_to_cpu(c->log.idx);
2019
2044
 
2020
2045
        /* Protect against corrupt value */
2021
2046
        if (idx > c->bufsize)
2022
 
                return BCME_ERROR;
 
2047
                return -EBADE;
2023
2048
 
2024
2049
        /* Skip reading the console buffer if the index pointer
2025
2050
         has not moved */
2026
2051
        if (idx == c->last)
2027
 
                return BCME_OK;
 
2052
                return 0;
2028
2053
 
2029
2054
        /* Read the console buffer */
2030
 
        addr = ltoh32(c->log.buf);
 
2055
        addr = le32_to_cpu(c->log.buf);
2031
2056
        rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2032
2057
        if (rv < 0)
2033
2058
                return rv;
2057
2082
                        if (line[n - 1] == '\r')
2058
2083
                                n--;
2059
2084
                        line[n] = 0;
2060
 
                        printf("CONSOLE: %s\n", line);
 
2085
                        printk(KERN_DEBUG "CONSOLE: %s\n", line);
2061
2086
                }
2062
2087
        }
2063
2088
break2:
2064
2089
 
2065
 
        return BCME_OK;
 
2090
        return 0;
2066
2091
}
2067
2092
#endif                          /* DHD_DEBUG */
2068
2093
 
2069
2094
int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2070
2095
{
2071
 
        int bcmerror = BCME_OK;
 
2096
        int bcmerror = 0;
2072
2097
 
2073
2098
        DHD_TRACE(("%s: Enter\n", __func__));
2074
2099
 
2075
2100
        /* Basic sanity checks */
2076
2101
        if (bus->dhd->up) {
2077
 
                bcmerror = BCME_NOTDOWN;
 
2102
                bcmerror = -EISCONN;
2078
2103
                goto err;
2079
2104
        }
2080
2105
        if (!len) {
2081
 
                bcmerror = BCME_BUFTOOSHORT;
 
2106
                bcmerror = -EOVERFLOW;
2082
2107
                goto err;
2083
2108
        }
2084
2109
 
2085
2110
        /* Free the old ones and replace with passed variables */
2086
 
        if (bus->vars)
2087
 
                kfree(bus->vars);
 
2111
        kfree(bus->vars);
2088
2112
 
2089
2113
        bus->vars = kmalloc(len, GFP_ATOMIC);
2090
2114
        bus->varsz = bus->vars ? len : 0;
2091
2115
        if (bus->vars == NULL) {
2092
 
                bcmerror = BCME_NOMEM;
 
2116
                bcmerror = -ENOMEM;
2093
2117
                goto err;
2094
2118
        }
2095
2119
 
2096
2120
        /* Copy the passed variables, which should include the
2097
2121
                 terminating double-null */
2098
 
        bcopy(arg, bus->vars, bus->varsz);
 
2122
        memcpy(bus->vars, arg, bus->varsz);
2099
2123
err:
2100
2124
        return bcmerror;
2101
2125
}
2118
2142
                goto exit;
2119
2143
 
2120
2144
        if (plen >= (int)sizeof(int_val))
2121
 
                bcopy(params, &int_val, sizeof(int_val));
 
2145
                memcpy(&int_val, params, sizeof(int_val));
2122
2146
 
2123
2147
        bool_val = (int_val != 0) ? true : false;
2124
2148
 
2128
2152
        /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2129
2153
        if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2130
2154
                                        actionid == IOV_GVAL(IOV_DEVRESET))) {
2131
 
                bcmerror = BCME_NOTREADY;
 
2155
                bcmerror = -EPERM;
2132
2156
                goto exit;
2133
2157
        }
2134
2158
 
2138
2162
                        bcmerror = dhdsdio_bussleep(bus, bool_val);
2139
2163
                } else {
2140
2164
                        int_val = (s32) bus->sleeping;
2141
 
                        bcopy(&int_val, arg, val_size);
 
2165
                        memcpy(arg, &int_val, val_size);
2142
2166
                }
2143
2167
                goto exit;
2144
2168
        }
2152
2176
        switch (actionid) {
2153
2177
        case IOV_GVAL(IOV_INTR):
2154
2178
                int_val = (s32) bus->intr;
2155
 
                bcopy(&int_val, arg, val_size);
 
2179
                memcpy(arg, &int_val, val_size);
2156
2180
                break;
2157
2181
 
2158
2182
        case IOV_SVAL(IOV_INTR):
2173
2197
 
2174
2198
        case IOV_GVAL(IOV_POLLRATE):
2175
2199
                int_val = (s32) bus->pollrate;
2176
 
                bcopy(&int_val, arg, val_size);
 
2200
                memcpy(arg, &int_val, val_size);
2177
2201
                break;
2178
2202
 
2179
2203
        case IOV_SVAL(IOV_POLLRATE):
2183
2207
 
2184
2208
        case IOV_GVAL(IOV_IDLETIME):
2185
2209
                int_val = bus->idletime;
2186
 
                bcopy(&int_val, arg, val_size);
 
2210
                memcpy(arg, &int_val, val_size);
2187
2211
                break;
2188
2212
 
2189
2213
        case IOV_SVAL(IOV_IDLETIME):
2190
2214
                if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2191
 
                        bcmerror = BCME_BADARG;
 
2215
                        bcmerror = -EINVAL;
2192
2216
                else
2193
2217
                        bus->idletime = int_val;
2194
2218
                break;
2195
2219
 
2196
2220
        case IOV_GVAL(IOV_IDLECLOCK):
2197
2221
                int_val = (s32) bus->idleclock;
2198
 
                bcopy(&int_val, arg, val_size);
 
2222
                memcpy(arg, &int_val, val_size);
2199
2223
                break;
2200
2224
 
2201
2225
        case IOV_SVAL(IOV_IDLECLOCK):
2204
2228
 
2205
2229
        case IOV_GVAL(IOV_SD1IDLE):
2206
2230
                int_val = (s32) sd1idle;
2207
 
                bcopy(&int_val, arg, val_size);
 
2231
                memcpy(arg, &int_val, val_size);
2208
2232
                break;
2209
2233
 
2210
2234
        case IOV_SVAL(IOV_SD1IDLE):
2223
2247
                        ASSERT(plen >= 2 * sizeof(int));
2224
2248
 
2225
2249
                        address = (u32) int_val;
2226
 
                        bcopy((char *)params + sizeof(int_val), &int_val,
2227
 
                              sizeof(int_val));
 
2250
                        memcpy(&int_val, (char *)params + sizeof(int_val),
 
2251
                               sizeof(int_val));
2228
2252
                        size = (uint) int_val;
2229
2253
 
2230
2254
                        /* Do some validation */
2234
2258
                                "0x%08x size %d dsize %d\n",
2235
2259
                                __func__, (set ? "set" : "get"),
2236
2260
                                address, size, dsize));
2237
 
                                bcmerror = BCME_BADARG;
 
2261
                                bcmerror = -EINVAL;
2238
2262
                                break;
2239
2263
                        }
2240
2264
 
2249
2273
                                DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2250
2274
                                "bytes at 0x%08x\n",
2251
2275
                                __func__, bus->orig_ramsize, size, address));
2252
 
                                bcmerror = BCME_BADARG;
 
2276
                                bcmerror = -EINVAL;
2253
2277
                                break;
2254
2278
                        }
2255
2279
 
2267
2291
 
2268
2292
        case IOV_GVAL(IOV_MEMSIZE):
2269
2293
                int_val = (s32) bus->ramsize;
2270
 
                bcopy(&int_val, arg, val_size);
 
2294
                memcpy(arg, &int_val, val_size);
2271
2295
                break;
2272
2296
 
2273
2297
        case IOV_GVAL(IOV_SDIOD_DRIVE):
2274
2298
                int_val = (s32) dhd_sdiod_drive_strength;
2275
 
                bcopy(&int_val, arg, val_size);
 
2299
                memcpy(arg, &int_val, val_size);
2276
2300
                break;
2277
2301
 
2278
2302
        case IOV_SVAL(IOV_SDIOD_DRIVE):
2279
2303
                dhd_sdiod_drive_strength = int_val;
2280
 
                si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh,
 
2304
                dhdsdio_sdiod_drive_strength_init(bus,
2281
2305
                                             dhd_sdiod_drive_strength);
2282
2306
                break;
2283
2307
 
2291
2315
 
2292
2316
        case IOV_GVAL(IOV_READAHEAD):
2293
2317
                int_val = (s32) dhd_readahead;
2294
 
                bcopy(&int_val, arg, val_size);
 
2318
                memcpy(arg, &int_val, val_size);
2295
2319
                break;
2296
2320
 
2297
2321
        case IOV_SVAL(IOV_READAHEAD):
2302
2326
 
2303
2327
        case IOV_GVAL(IOV_SDRXCHAIN):
2304
2328
                int_val = (s32) bus->use_rxchain;
2305
 
                bcopy(&int_val, arg, val_size);
 
2329
                memcpy(arg, &int_val, val_size);
2306
2330
                break;
2307
2331
 
2308
2332
        case IOV_SVAL(IOV_SDRXCHAIN):
2309
2333
                if (bool_val && !bus->sd_rxchain)
2310
 
                        bcmerror = BCME_UNSUPPORTED;
 
2334
                        bcmerror = -ENOTSUPP;
2311
2335
                else
2312
2336
                        bus->use_rxchain = bool_val;
2313
2337
                break;
2314
2338
        case IOV_GVAL(IOV_ALIGNCTL):
2315
2339
                int_val = (s32) dhd_alignctl;
2316
 
                bcopy(&int_val, arg, val_size);
 
2340
                memcpy(arg, &int_val, val_size);
2317
2341
                break;
2318
2342
 
2319
2343
        case IOV_SVAL(IOV_ALIGNCTL):
2322
2346
 
2323
2347
        case IOV_GVAL(IOV_SDALIGN):
2324
2348
                int_val = DHD_SDALIGN;
2325
 
                bcopy(&int_val, arg, val_size);
 
2349
                memcpy(arg, &int_val, val_size);
2326
2350
                break;
2327
2351
 
2328
2352
#ifdef DHD_DEBUG
2329
2353
        case IOV_GVAL(IOV_VARS):
2330
2354
                if (bus->varsz < (uint) len)
2331
 
                        bcopy(bus->vars, arg, bus->varsz);
 
2355
                        memcpy(arg, bus->vars, bus->varsz);
2332
2356
                else
2333
 
                        bcmerror = BCME_BUFTOOSHORT;
 
2357
                        bcmerror = -EOVERFLOW;
2334
2358
                break;
2335
2359
#endif                          /* DHD_DEBUG */
2336
2360
 
2346
2370
                        size = sd_ptr->func;
2347
2371
                        int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2348
2372
                        if (bcmsdh_regfail(bus->sdh))
2349
 
                                bcmerror = BCME_SDIO_ERROR;
2350
 
                        bcopy(&int_val, arg, sizeof(s32));
 
2373
                                bcmerror = -EIO;
 
2374
                        memcpy(arg, &int_val, sizeof(s32));
2351
2375
                        break;
2352
2376
                }
2353
2377
 
2362
2386
                        size = sd_ptr->func;
2363
2387
                        bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2364
2388
                        if (bcmsdh_regfail(bus->sdh))
2365
 
                                bcmerror = BCME_SDIO_ERROR;
 
2389
                                bcmerror = -EIO;
2366
2390
                        break;
2367
2391
                }
2368
2392
 
2373
2397
                        sdreg_t sdreg;
2374
2398
                        u32 addr, size;
2375
2399
 
2376
 
                        bcopy(params, &sdreg, sizeof(sdreg));
 
2400
                        memcpy(&sdreg, params, sizeof(sdreg));
2377
2401
 
2378
2402
                        addr = SI_ENUM_BASE + sdreg.offset;
2379
2403
                        size = sdreg.func;
2380
2404
                        int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2381
2405
                        if (bcmsdh_regfail(bus->sdh))
2382
 
                                bcmerror = BCME_SDIO_ERROR;
2383
 
                        bcopy(&int_val, arg, sizeof(s32));
 
2406
                                bcmerror = -EIO;
 
2407
                        memcpy(arg, &int_val, sizeof(s32));
2384
2408
                        break;
2385
2409
                }
2386
2410
 
2389
2413
                        sdreg_t sdreg;
2390
2414
                        u32 addr, size;
2391
2415
 
2392
 
                        bcopy(params, &sdreg, sizeof(sdreg));
 
2416
                        memcpy(&sdreg, params, sizeof(sdreg));
2393
2417
 
2394
2418
                        addr = SI_ENUM_BASE + sdreg.offset;
2395
2419
                        size = sdreg.func;
2396
2420
                        bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2397
2421
                        if (bcmsdh_regfail(bus->sdh))
2398
 
                                bcmerror = BCME_SDIO_ERROR;
 
2422
                                bcmerror = -EIO;
2399
2423
                        break;
2400
2424
                }
2401
2425
 
2420
2444
 
2421
2445
        case IOV_GVAL(IOV_FORCEEVEN):
2422
2446
                int_val = (s32) forcealign;
2423
 
                bcopy(&int_val, arg, val_size);
 
2447
                memcpy(arg, &int_val, val_size);
2424
2448
                break;
2425
2449
 
2426
2450
        case IOV_SVAL(IOV_FORCEEVEN):
2429
2453
 
2430
2454
        case IOV_GVAL(IOV_TXBOUND):
2431
2455
                int_val = (s32) dhd_txbound;
2432
 
                bcopy(&int_val, arg, val_size);
 
2456
                memcpy(arg, &int_val, val_size);
2433
2457
                break;
2434
2458
 
2435
2459
        case IOV_SVAL(IOV_TXBOUND):
2438
2462
 
2439
2463
        case IOV_GVAL(IOV_RXBOUND):
2440
2464
                int_val = (s32) dhd_rxbound;
2441
 
                bcopy(&int_val, arg, val_size);
 
2465
                memcpy(arg, &int_val, val_size);
2442
2466
                break;
2443
2467
 
2444
2468
        case IOV_SVAL(IOV_RXBOUND):
2447
2471
 
2448
2472
        case IOV_GVAL(IOV_TXMINMAX):
2449
2473
                int_val = (s32) dhd_txminmax;
2450
 
                bcopy(&int_val, arg, val_size);
 
2474
                memcpy(arg, &int_val, val_size);
2451
2475
                break;
2452
2476
 
2453
2477
        case IOV_SVAL(IOV_TXMINMAX):
2458
2482
#ifdef SDTEST
2459
2483
        case IOV_GVAL(IOV_EXTLOOP):
2460
2484
                int_val = (s32) bus->ext_loop;
2461
 
                bcopy(&int_val, arg, val_size);
 
2485
                memcpy(arg, &int_val, val_size);
2462
2486
                break;
2463
2487
 
2464
2488
        case IOV_SVAL(IOV_EXTLOOP):
2480
2504
                        __func__, bool_val, bus->dhd->dongle_reset,
2481
2505
                        bus->dhd->busstate));
2482
2506
 
2483
 
                ASSERT(bus->dhd->osh);
2484
 
                /* ASSERT(bus->cl_devid); */
2485
 
 
2486
2507
                dhd_bus_devreset(bus->dhd, (u8) bool_val);
2487
2508
 
2488
2509
                break;
2492
2513
 
2493
2514
                /* Get its status */
2494
2515
                int_val = (bool) bus->dhd->dongle_reset;
2495
 
                bcopy(&int_val, arg, val_size);
 
2516
                memcpy(arg, &int_val, val_size);
2496
2517
 
2497
2518
                break;
2498
2519
 
2499
2520
        default:
2500
 
                bcmerror = BCME_UNSUPPORTED;
 
2521
                bcmerror = -ENOTSUPP;
2501
2522
                break;
2502
2523
        }
2503
2524
 
2532
2553
        varaddr = (bus->ramsize - 4) - varsize;
2533
2554
 
2534
2555
        if (bus->vars) {
2535
 
                vbuffer = kmalloc(varsize, GFP_ATOMIC);
 
2556
                vbuffer = kzalloc(varsize, GFP_ATOMIC);
2536
2557
                if (!vbuffer)
2537
 
                        return BCME_NOMEM;
 
2558
                        return -ENOMEM;
2538
2559
 
2539
 
                memset(vbuffer, 0, varsize);
2540
 
                bcopy(bus->vars, vbuffer, bus->varsz);
 
2560
                memcpy(vbuffer, bus->vars, bus->varsz);
2541
2561
 
2542
2562
                /* Write the vars list */
2543
2563
                bcmerror =
2547
2567
                DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2548
2568
                nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2549
2569
                if (!nvram_ularray)
2550
 
                        return BCME_NOMEM;
 
2570
                        return -ENOMEM;
2551
2571
 
2552
2572
                /* Upload image to verify downloaded contents. */
2553
2573
                memset(nvram_ularray, 0xaa, varsize);
2590
2610
        } else {
2591
2611
                varsizew = varsize / 4;
2592
2612
                varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2593
 
                varsizew = htol32(varsizew);
 
2613
                varsizew = cpu_to_le32(varsizew);
2594
2614
        }
2595
2615
 
2596
2616
        DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2606
2626
static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2607
2627
{
2608
2628
        uint retries;
 
2629
        u32 regdata;
2609
2630
        int bcmerror = 0;
2610
2631
 
2611
2632
        /* To enter download state, disable ARM and reset SOCRAM.
2612
2633
         * To exit download state, simply reset ARM (default is RAM boot).
2613
2634
         */
2614
2635
        if (enter) {
2615
 
 
2616
2636
                bus->alp_only = true;
2617
2637
 
2618
 
                if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2619
 
                    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2620
 
                        DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2621
 
                        bcmerror = BCME_ERROR;
2622
 
                        goto fail;
2623
 
                }
2624
 
 
2625
 
                si_core_disable(bus->sih, 0);
2626
 
                if (bcmsdh_regfail(bus->sdh)) {
2627
 
                        bcmerror = BCME_SDIO_ERROR;
2628
 
                        goto fail;
2629
 
                }
2630
 
 
2631
 
                if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2632
 
                        DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2633
 
                                   __func__));
2634
 
                        bcmerror = BCME_ERROR;
2635
 
                        goto fail;
2636
 
                }
2637
 
 
2638
 
                si_core_reset(bus->sih, 0, 0);
2639
 
                if (bcmsdh_regfail(bus->sdh)) {
2640
 
                        DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2641
 
                                   __func__));
2642
 
                        bcmerror = BCME_SDIO_ERROR;
2643
 
                        goto fail;
2644
 
                }
 
2638
                dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
 
2639
 
 
2640
                dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2645
2641
 
2646
2642
                /* Clear the top bit of memory */
2647
2643
                if (bus->ramsize) {
2650
2646
                                         (u8 *)&zeros, 4);
2651
2647
                }
2652
2648
        } else {
2653
 
                if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2654
 
                        DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2655
 
                                   __func__));
2656
 
                        bcmerror = BCME_ERROR;
2657
 
                        goto fail;
2658
 
                }
2659
 
 
2660
 
                if (!si_iscoreup(bus->sih)) {
 
2649
                regdata = bcmsdh_reg_read(bus->sdh,
 
2650
                        CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
 
2651
                regdata &= (SBTML_RESET | SBTML_REJ_MASK |
 
2652
                        (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
 
2653
                if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2661
2654
                        DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2662
2655
                                   __func__));
2663
 
                        bcmerror = BCME_ERROR;
 
2656
                        bcmerror = -EBADE;
2664
2657
                        goto fail;
2665
2658
                }
2666
2659
 
2670
2663
                        bcmerror = 0;
2671
2664
                }
2672
2665
 
2673
 
                if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2674
 
                    !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2675
 
                        DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2676
 
                                   __func__));
2677
 
                        bcmerror = BCME_ERROR;
2678
 
                        goto fail;
2679
 
                }
2680
2666
                W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2681
2667
 
2682
 
                if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2683
 
                    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2684
 
                        DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2685
 
                        bcmerror = BCME_ERROR;
2686
 
                        goto fail;
2687
 
                }
2688
 
 
2689
 
                si_core_reset(bus->sih, 0, 0);
2690
 
                if (bcmsdh_regfail(bus->sdh)) {
2691
 
                        DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2692
 
                                   __func__));
2693
 
                        bcmerror = BCME_SDIO_ERROR;
2694
 
                        goto fail;
2695
 
                }
 
2668
                dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2696
2669
 
2697
2670
                /* Allow HT Clock now that the ARM is running. */
2698
2671
                bus->alp_only = false;
2699
2672
 
2700
2673
                bus->dhd->busstate = DHD_BUS_LOAD;
2701
2674
        }
2702
 
 
2703
2675
fail:
2704
 
        /* Always return to SDIOD core */
2705
 
        if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2706
 
                si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2707
 
 
2708
2676
        return bcmerror;
2709
2677
}
2710
2678
 
2749
2717
                if (set && strcmp(name, "sd_divisor") == 0) {
2750
2718
                        if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2751
2719
                                            &bus->sd_divisor, sizeof(s32),
2752
 
                                            false) != BCME_OK) {
 
2720
                                            false) != 0) {
2753
2721
                                bus->sd_divisor = -1;
2754
2722
                                DHD_ERROR(("%s: fail on %s get\n", __func__,
2755
2723
                                           name));
2762
2730
                if (set && strcmp(name, "sd_mode") == 0) {
2763
2731
                        if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2764
2732
                                            &bus->sd_mode, sizeof(s32),
2765
 
                                            false) != BCME_OK) {
 
2733
                                            false) != 0) {
2766
2734
                                bus->sd_mode = -1;
2767
2735
                                DHD_ERROR(("%s: fail on %s get\n", __func__,
2768
2736
                                           name));
2777
2745
                        if (bcmsdh_iovar_op
2778
2746
                            (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2779
2747
                             &bus->blocksize, sizeof(s32),
2780
 
                             false) != BCME_OK) {
 
2748
                             false) != 0) {
2781
2749
                                bus->blocksize = 0;
2782
2750
                                DHD_ERROR(("%s: fail on %s get\n", __func__,
2783
2751
                                           "sd_blocksize"));
2828
2796
 
2829
2797
void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2830
2798
{
2831
 
        struct osl_info *osh = bus->dhd->osh;
2832
2799
        u32 local_hostintmask;
2833
2800
        u8 saveclk;
2834
2801
        uint retries;
2878
2845
        dhdsdio_clkctl(bus, CLK_SDONLY, false);
2879
2846
 
2880
2847
        /* Clear the data packet queues */
2881
 
        pktq_flush(osh, &bus->txq, true);
 
2848
        bcm_pktq_flush(&bus->txq, true, NULL, NULL);
2882
2849
 
2883
2850
        /* Clear any held glomming stuff */
2884
2851
        if (bus->glomd)
2885
 
                pkt_buf_free_skb(osh, bus->glomd, false);
 
2852
                bcm_pkt_buf_free_skb(bus->glomd);
2886
2853
 
2887
2854
        if (bus->glom)
2888
 
                pkt_buf_free_skb(osh, bus->glom, false);
 
2855
                bcm_pkt_buf_free_skb(bus->glom);
2889
2856
 
2890
2857
        bus->glom = bus->glomd = NULL;
2891
2858
 
2959
2926
 
2960
2927
        /* If F2 successfully enabled, set core and enable interrupts */
2961
2928
        if (ready == enable) {
2962
 
                /* Make sure we're talking to the core. */
2963
 
                bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2964
 
                if (!(bus->regs))
2965
 
                        bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2966
 
 
2967
2929
                /* Set up the interrupt mask and enable interrupts */
2968
2930
                bus->hostintmask = HOSTINTMASK;
2969
 
                W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
 
2931
                W_SDREG(bus->hostintmask,
 
2932
                        (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
 
2933
                        hostintmask), retries);
2970
2934
 
2971
2935
                bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2972
2936
                                 (u8) watermark, &err);
3100
3064
        ASSERT(bus->rxctl >= bus->rxbuf);
3101
3065
 
3102
3066
        /* Copy the already-read portion over */
3103
 
        bcopy(hdr, bus->rxctl, firstread);
 
3067
        memcpy(bus->rxctl, hdr, firstread);
3104
3068
        if (len <= firstread)
3105
3069
                goto gotpkt;
3106
3070
 
3107
3071
        /* Copy the full data pkt in gSPI case and process ioctl. */
3108
3072
        if (bus->bus == SPI_BUS) {
3109
 
                bcopy(hdr, bus->rxctl, len);
 
3073
                memcpy(bus->rxctl, hdr, len);
3110
3074
                goto gotpkt;
3111
3075
        }
3112
3076
 
3145
3109
        }
3146
3110
 
3147
3111
        /* Read remainder of frame body into the rxctl buffer */
3148
 
        sdret =
3149
 
            dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3150
 
                                (bus->rxctl + firstread), rdlen, NULL, NULL,
3151
 
                                NULL);
 
3112
        sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
 
3113
                                F2SYNC, (bus->rxctl + firstread), rdlen,
 
3114
                                NULL, NULL, NULL);
3152
3115
        bus->f2rxdata++;
3153
 
        ASSERT(sdret != BCME_PENDING);
 
3116
        ASSERT(sdret != -BCME_PENDING);
3154
3117
 
3155
3118
        /* Control frame failures need retransmission */
3156
3119
        if (sdret < 0) {
3164
3127
gotpkt:
3165
3128
 
3166
3129
#ifdef DHD_DEBUG
3167
 
        if (DHD_BYTES_ON() && DHD_CTL_ON())
3168
 
                prhex("RxCtrl", bus->rxctl, len);
 
3130
        if (DHD_BYTES_ON() && DHD_CTL_ON()) {
 
3131
                printk(KERN_DEBUG "RxCtrl:\n");
 
3132
                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
 
3133
        }
3169
3134
#endif
3170
3135
 
3171
3136
        /* Point to valid data and indicate its length */
3184
3149
 
3185
3150
        u16 sublen, check;
3186
3151
        struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3187
 
        struct osl_info *osh = bus->dhd->osh;
3188
3152
 
3189
3153
        int errcode;
3190
3154
        u8 chan, seq, doff, sfdoff;
3214
3178
 
3215
3179
                for (totlen = num = 0; dlen; num++) {
3216
3180
                        /* Get (and move past) next length */
3217
 
                        sublen = ltoh16_ua(dptr);
 
3181
                        sublen = get_unaligned_le16(dptr);
3218
3182
                        dlen -= sizeof(u16);
3219
3183
                        dptr += sizeof(u16);
3220
3184
                        if ((sublen < SDPCM_HDRLEN) ||
3240
3204
                        }
3241
3205
 
3242
3206
                        /* Allocate/chain packet for next subframe */
3243
 
                        pnext = pkt_buf_get_skb(osh, sublen + DHD_SDALIGN);
 
3207
                        pnext = bcm_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3244
3208
                        if (pnext == NULL) {
3245
 
                                DHD_ERROR(("%s: pkt_buf_get_skb failed, num %d len %d\n",
3246
 
                                           __func__, num, sublen));
 
3209
                                DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
 
3210
                                        "num %d len %d\n", __func__,
 
3211
                                        num, sublen));
3247
3212
                                break;
3248
3213
                        }
3249
3214
                        ASSERT(!(pnext->prev));
3257
3222
                        }
3258
3223
 
3259
3224
                        /* Adhere to start alignment requirements */
3260
 
                        PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
 
3225
                        PKTALIGN(pnext, sublen, DHD_SDALIGN);
3261
3226
                }
3262
3227
 
3263
3228
                /* If all allocations succeeded, save packet chain
3276
3241
                        pfirst = pnext = NULL;
3277
3242
                } else {
3278
3243
                        if (pfirst)
3279
 
                                pkt_buf_free_skb(osh, pfirst, false);
 
3244
                                bcm_pkt_buf_free_skb(pfirst);
3280
3245
                        bus->glom = NULL;
3281
3246
                        num = 0;
3282
3247
                }
3283
3248
 
3284
3249
                /* Done with descriptor packet */
3285
 
                pkt_buf_free_skb(osh, bus->glomd, false);
 
3250
                bcm_pkt_buf_free_skb(bus->glomd);
3286
3251
                bus->glomd = NULL;
3287
3252
                bus->nextlen = 0;
3288
3253
 
3303
3268
                }
3304
3269
 
3305
3270
                pfirst = bus->glom;
3306
 
                dlen = (u16) pkttotlen(osh, pfirst);
 
3271
                dlen = (u16) bcm_pkttotlen(pfirst);
3307
3272
 
3308
3273
                /* Do an SDIO read for the superframe.  Configurable iovar to
3309
3274
                 * read directly into the chained packet, or allocate a large
3310
3275
                 * packet and and copy into the chain.
3311
3276
                 */
3312
3277
                if (usechain) {
3313
 
                        errcode = dhd_bcmsdh_recv_buf(bus,
3314
 
                                                      bcmsdh_cur_sbwad
3315
 
                                                      (bus->sdh), SDIO_FUNC_2,
3316
 
                                                      F2SYNC,
3317
 
                                                      (u8 *) pfirst->data,
3318
 
                                                      dlen, pfirst, NULL, NULL);
 
3278
                        errcode = bcmsdh_recv_buf(bus,
 
3279
                                        bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
 
3280
                                        F2SYNC, (u8 *) pfirst->data, dlen,
 
3281
                                        pfirst, NULL, NULL);
3319
3282
                } else if (bus->dataptr) {
3320
 
                        errcode = dhd_bcmsdh_recv_buf(bus,
3321
 
                                                      bcmsdh_cur_sbwad
3322
 
                                                      (bus->sdh), SDIO_FUNC_2,
3323
 
                                                      F2SYNC, bus->dataptr,
3324
 
                                                      dlen, NULL, NULL, NULL);
3325
 
                        sublen =
3326
 
                            (u16) pktfrombuf(osh, pfirst, 0, dlen,
 
3283
                        errcode = bcmsdh_recv_buf(bus,
 
3284
                                        bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
 
3285
                                        F2SYNC, bus->dataptr, dlen,
 
3286
                                        NULL, NULL, NULL);
 
3287
                        sublen = (u16) bcm_pktfrombuf(pfirst, 0, dlen,
3327
3288
                                                bus->dataptr);
3328
3289
                        if (sublen != dlen) {
3329
3290
                                DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3337
3298
                        errcode = -1;
3338
3299
                }
3339
3300
                bus->f2rxdata++;
3340
 
                ASSERT(errcode != BCME_PENDING);
 
3301
                ASSERT(errcode != -BCME_PENDING);
3341
3302
 
3342
3303
                /* On failure, kill the superframe, allow a couple retries */
3343
3304
                if (errcode < 0) {
3351
3312
                                bus->glomerr = 0;
3352
3313
                                dhdsdio_rxfail(bus, true, false);
3353
3314
                                dhd_os_sdlock_rxq(bus->dhd);
3354
 
                                pkt_buf_free_skb(osh, bus->glom, false);
 
3315
                                bcm_pkt_buf_free_skb(bus->glom);
3355
3316
                                dhd_os_sdunlock_rxq(bus->dhd);
3356
3317
                                bus->rxglomfail++;
3357
3318
                                bus->glom = NULL;
3360
3321
                }
3361
3322
#ifdef DHD_DEBUG
3362
3323
                if (DHD_GLOM_ON()) {
3363
 
                        prhex("SUPERFRAME", pfirst->data,
3364
 
                              min_t(int, pfirst->len, 48));
 
3324
                        printk(KERN_DEBUG "SUPERFRAME:\n");
 
3325
                        print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
3326
                                pfirst->data, min_t(int, pfirst->len, 48));
3365
3327
                }
3366
3328
#endif
3367
3329
 
3368
3330
                /* Validate the superframe header */
3369
3331
                dptr = (u8 *) (pfirst->data);
3370
 
                sublen = ltoh16_ua(dptr);
3371
 
                check = ltoh16_ua(dptr + sizeof(u16));
 
3332
                sublen = get_unaligned_le16(dptr);
 
3333
                check = get_unaligned_le16(dptr + sizeof(u16));
3372
3334
 
3373
3335
                chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3374
3336
                seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3437
3399
                     num++, pnext = pnext->next) {
3438
3400
                        dptr = (u8 *) (pnext->data);
3439
3401
                        dlen = (u16) (pnext->len);
3440
 
                        sublen = ltoh16_ua(dptr);
3441
 
                        check = ltoh16_ua(dptr + sizeof(u16));
 
3402
                        sublen = get_unaligned_le16(dptr);
 
3403
                        check = get_unaligned_le16(dptr + sizeof(u16));
3442
3404
                        chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3443
3405
                        doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3444
3406
#ifdef DHD_DEBUG
3445
 
                        if (DHD_GLOM_ON())
3446
 
                                prhex("subframe", dptr, 32);
 
3407
                        if (DHD_GLOM_ON()) {
 
3408
                                printk(KERN_DEBUG "subframe:\n");
 
3409
                                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
3410
                                                     dptr, 32);
 
3411
                        }
3447
3412
#endif
3448
3413
 
3449
3414
                        if ((u16)~(sublen ^ check)) {
3480
3445
                                bus->glomerr = 0;
3481
3446
                                dhdsdio_rxfail(bus, true, false);
3482
3447
                                dhd_os_sdlock_rxq(bus->dhd);
3483
 
                                pkt_buf_free_skb(osh, bus->glom, false);
 
3448
                                bcm_pkt_buf_free_skb(bus->glom);
3484
3449
                                dhd_os_sdunlock_rxq(bus->dhd);
3485
3450
                                bus->rxglomfail++;
3486
3451
                                bus->glom = NULL;
3500
3465
                        pfirst->next = NULL;
3501
3466
 
3502
3467
                        dptr = (u8 *) (pfirst->data);
3503
 
                        sublen = ltoh16_ua(dptr);
 
3468
                        sublen = get_unaligned_le16(dptr);
3504
3469
                        chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3505
3470
                        seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3506
3471
                        doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3520
3485
                                rxseq = seq;
3521
3486
                        }
3522
3487
#ifdef DHD_DEBUG
3523
 
                        if (DHD_BYTES_ON() && DHD_DATA_ON())
3524
 
                                prhex("Rx Subframe Data", dptr, dlen);
 
3488
                        if (DHD_BYTES_ON() && DHD_DATA_ON()) {
 
3489
                                printk(KERN_DEBUG "Rx Subframe Data:\n");
 
3490
                                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
3491
                                                     dptr, dlen);
 
3492
                        }
3525
3493
#endif
3526
3494
 
3527
3495
                        __skb_trim(pfirst, sublen);
3528
3496
                        skb_pull(pfirst, doff);
3529
3497
 
3530
3498
                        if (pfirst->len == 0) {
3531
 
                                pkt_buf_free_skb(bus->dhd->osh, pfirst, false);
 
3499
                                bcm_pkt_buf_free_skb(pfirst);
3532
3500
                                if (plast) {
3533
3501
                                        plast->next = pnext;
3534
3502
                                } else {
3541
3509
                                DHD_ERROR(("%s: rx protocol error\n",
3542
3510
                                           __func__));
3543
3511
                                bus->dhd->rx_errors++;
3544
 
                                pkt_buf_free_skb(osh, pfirst, false);
 
3512
                                bcm_pkt_buf_free_skb(pfirst);
3545
3513
                                if (plast) {
3546
3514
                                        plast->next = pnext;
3547
3515
                                } else {
3564
3532
                                __func__, num, pfirst, pfirst->data,
3565
3533
                                pfirst->len, pfirst->next,
3566
3534
                                pfirst->prev));
3567
 
                                prhex("", (u8 *) pfirst->data,
3568
 
                                      min_t(int, pfirst->len, 32));
 
3535
                                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
3536
                                                pfirst->data,
 
3537
                                                min_t(int, pfirst->len, 32));
3569
3538
                        }
3570
3539
#endif                          /* DHD_DEBUG */
3571
3540
                }
3585
3554
/* Return true if there may be more frames to read */
3586
3555
static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3587
3556
{
3588
 
        struct osl_info *osh = bus->dhd->osh;
3589
3557
        bcmsdh_info_t *sdh = bus->sdh;
3590
3558
 
3591
3559
        u16 len, check; /* Extracted hardware header fields */
3592
3560
        u8 chan, seq, doff;     /* Extracted software header fields */
3593
3561
        u8 fcbits;              /* Extracted fcbits from software header */
3594
 
        u8 delta;
3595
3562
 
3596
3563
        struct sk_buff *pkt;            /* Packet for event or data frames */
3597
3564
        u16 pad;                /* Number of pad bytes to read */
3672
3639
                         * control pkt receives.
3673
3640
                         * Later we use buffer-poll for data as well
3674
3641
                         * as control packets.
3675
 
                         * This is required becuase dhd receives full
 
3642
                         * This is required because dhd receives full
3676
3643
                         * frame in gSPI unlike SDIO.
3677
3644
                         * After the frame is received we have to
3678
3645
                         * distinguish whether it is data
3680
3647
                         */
3681
3648
                        /* Allocate a packet buffer */
3682
3649
                        dhd_os_sdlock_rxq(bus->dhd);
3683
 
                        pkt = pkt_buf_get_skb(osh, rdlen + DHD_SDALIGN);
 
3650
                        pkt = bcm_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3684
3651
                        if (!pkt) {
3685
3652
                                if (bus->bus == SPI_BUS) {
3686
3653
                                        bus->usebufpool = false;
3697
3664
                                        ASSERT(bus->rxctl >= bus->rxbuf);
3698
3665
                                        rxbuf = bus->rxctl;
3699
3666
                                        /* Read the entire frame */
3700
 
                                        sdret = dhd_bcmsdh_recv_buf(bus,
3701
 
                                                    bcmsdh_cur_sbwad
3702
 
                                                    (sdh),
3703
 
                                                    SDIO_FUNC_2,
3704
 
                                                    F2SYNC,
3705
 
                                                    rxbuf,
3706
 
                                                    rdlen, NULL,
3707
 
                                                    NULL, NULL);
 
3667
                                        sdret = bcmsdh_recv_buf(bus,
 
3668
                                                    bcmsdh_cur_sbwad(sdh),
 
3669
                                                    SDIO_FUNC_2, F2SYNC,
 
3670
                                                    rxbuf, rdlen,
 
3671
                                                    NULL, NULL, NULL);
3708
3672
                                        bus->f2rxdata++;
3709
 
                                        ASSERT(sdret != BCME_PENDING);
 
3673
                                        ASSERT(sdret != -BCME_PENDING);
3710
3674
 
3711
3675
                                        /* Control frame failures need
3712
3676
                                         retransmission */
3726
3690
                                } else {
3727
3691
                                        /* Give up on data,
3728
3692
                                        request rtx of events */
3729
 
                                        DHD_ERROR(("%s (nextlen): pkt_buf_get_skb failed: len %d rdlen %d " "expected rxseq %d\n",
3730
 
                                                __func__, len, rdlen, rxseq));
 
3693
                                        DHD_ERROR(("%s (nextlen): "
 
3694
                                                   "bcm_pkt_buf_get_skb failed:"
 
3695
                                                   " len %d rdlen %d expected"
 
3696
                                                   " rxseq %d\n", __func__,
 
3697
                                                   len, rdlen, rxseq));
3731
3698
                                        /* Just go try again w/normal
3732
3699
                                        header read */
3733
3700
                                        dhd_os_sdunlock_rxq(bus->dhd);
3738
3705
                                        bus->usebufpool = true;
3739
3706
 
3740
3707
                                ASSERT(!(pkt->prev));
3741
 
                                PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
 
3708
                                PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3742
3709
                                rxbuf = (u8 *) (pkt->data);
3743
3710
                                /* Read the entire frame */
3744
 
                                sdret =
3745
 
                                    dhd_bcmsdh_recv_buf(bus,
 
3711
                                sdret = bcmsdh_recv_buf(bus,
3746
3712
                                                bcmsdh_cur_sbwad(sdh),
3747
3713
                                                SDIO_FUNC_2, F2SYNC,
3748
 
                                                rxbuf, rdlen, pkt, NULL,
3749
 
                                                NULL);
 
3714
                                                rxbuf, rdlen,
 
3715
                                                pkt, NULL, NULL);
3750
3716
                                bus->f2rxdata++;
3751
 
                                ASSERT(sdret != BCME_PENDING);
 
3717
                                ASSERT(sdret != -BCME_PENDING);
3752
3718
 
3753
3719
                                if (sdret < 0) {
3754
3720
                                        DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3755
3721
                                                __func__, rdlen, sdret));
3756
 
                                        pkt_buf_free_skb(bus->dhd->osh, pkt, false);
 
3722
                                        bcm_pkt_buf_free_skb(pkt);
3757
3723
                                        bus->dhd->rx_errors++;
3758
3724
                                        dhd_os_sdunlock_rxq(bus->dhd);
3759
3725
                                        /* Force retry w/normal header read.
3760
 
                                         * Don't attemp NAK for
 
3726
                                         * Don't attempt NAK for
3761
3727
                                         * gSPI
3762
3728
                                         */
3763
3729
                                        dhdsdio_rxfail(bus, true,
3770
3736
                        dhd_os_sdunlock_rxq(bus->dhd);
3771
3737
 
3772
3738
                        /* Now check the header */
3773
 
                        bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
 
3739
                        memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3774
3740
 
3775
3741
                        /* Extract hardware header fields */
3776
 
                        len = ltoh16_ua(bus->rxhdr);
3777
 
                        check = ltoh16_ua(bus->rxhdr + sizeof(u16));
 
3742
                        len = get_unaligned_le16(bus->rxhdr);
 
3743
                        check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3778
3744
 
3779
3745
                        /* All zeros means readahead info was bad */
3780
3746
                        if (!(len | check)) {
3781
3747
                                DHD_INFO(("%s (nextlen): read zeros in HW "
3782
3748
                                        "header???\n", __func__));
3783
 
                                dhd_os_sdlock_rxq(bus->dhd);
3784
 
                                PKTFREE2();
3785
 
                                dhd_os_sdunlock_rxq(bus->dhd);
3786
 
                                GSPI_PR55150_BAILOUT;
 
3749
                                dhdsdio_pktfree2(bus, pkt);
3787
3750
                                continue;
3788
3751
                        }
3789
3752
 
3790
3753
                        /* Validate check bytes */
3791
3754
                        if ((u16)~(len ^ check)) {
3792
 
                                DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
 
3755
                                DHD_ERROR(("%s (nextlen): HW hdr error:"
 
3756
                                        " nextlen/len/check"
 
3757
                                        " 0x%04x/0x%04x/0x%04x\n",
3793
3758
                                        __func__, nextlen, len, check));
3794
 
                                dhd_os_sdlock_rxq(bus->dhd);
3795
 
                                PKTFREE2();
3796
 
                                dhd_os_sdunlock_rxq(bus->dhd);
3797
3759
                                bus->rx_badhdr++;
3798
3760
                                dhdsdio_rxfail(bus, false, false);
3799
 
                                GSPI_PR55150_BAILOUT;
 
3761
                                dhdsdio_pktfree2(bus, pkt);
3800
3762
                                continue;
3801
3763
                        }
3802
3764
 
3804
3766
                        if (len < SDPCM_HDRLEN) {
3805
3767
                                DHD_ERROR(("%s (nextlen): HW hdr length "
3806
3768
                                        "invalid: %d\n", __func__, len));
3807
 
                                dhd_os_sdlock_rxq(bus->dhd);
3808
 
                                PKTFREE2();
3809
 
                                dhd_os_sdunlock_rxq(bus->dhd);
3810
 
                                GSPI_PR55150_BAILOUT;
 
3769
                                dhdsdio_pktfree2(bus, pkt);
3811
3770
                                continue;
3812
3771
                        }
3813
3772
 
3816
3775
                        if (len_consistent) {
3817
3776
                                /* Mismatch, force retry w/normal
3818
3777
                                        header (may be >4K) */
3819
 
                                DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
 
3778
                                DHD_ERROR(("%s (nextlen): mismatch, "
 
3779
                                        "nextlen %d len %d rnd %d; "
 
3780
                                        "expected rxseq %d\n",
3820
3781
                                        __func__, nextlen,
3821
3782
                                        len, roundup(len, 16), rxseq));
3822
 
                                dhd_os_sdlock_rxq(bus->dhd);
3823
 
                                PKTFREE2();
3824
 
                                dhd_os_sdunlock_rxq(bus->dhd);
3825
 
                                dhdsdio_rxfail(bus, true,
3826
 
                                               (bus->bus ==
3827
 
                                                SPI_BUS) ? false : true);
3828
 
                                GSPI_PR55150_BAILOUT;
 
3783
                                dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
 
3784
                                dhdsdio_pktfree2(bus, pkt);
3829
3785
                                continue;
3830
3786
                        }
3831
3787
 
3832
3788
                        /* Extract software header fields */
3833
 
                        chan =
3834
 
                            SDPCM_PACKET_CHANNEL(&bus->rxhdr
3835
 
                                                 [SDPCM_FRAMETAG_LEN]);
3836
 
                        seq =
3837
 
                            SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3838
 
                                                  [SDPCM_FRAMETAG_LEN]);
3839
 
                        doff =
3840
 
                            SDPCM_DOFFSET_VALUE(&bus->rxhdr
3841
 
                                                [SDPCM_FRAMETAG_LEN]);
3842
 
                        txmax =
3843
 
                            SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
 
3789
                        chan = SDPCM_PACKET_CHANNEL(
 
3790
                                        &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
 
3791
                        seq = SDPCM_PACKET_SEQUENCE(
 
3792
                                        &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
 
3793
                        doff = SDPCM_DOFFSET_VALUE(
 
3794
                                        &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
 
3795
                        txmax = SDPCM_WINDOW_VALUE(
 
3796
                                        &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3844
3797
 
3845
3798
                        bus->nextlen =
3846
3799
                            bus->rxhdr[SDPCM_FRAMETAG_LEN +
3852
3805
                        }
3853
3806
 
3854
3807
                        bus->dhd->rx_readahead_cnt++;
 
3808
 
3855
3809
                        /* Handle Flow Control */
3856
 
                        fcbits =
3857
 
                            SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3858
 
 
3859
 
                        delta = 0;
3860
 
                        if (~bus->flowcontrol & fcbits) {
3861
 
                                bus->fc_xoff++;
3862
 
                                delta = 1;
3863
 
                        }
3864
 
                        if (bus->flowcontrol & ~fcbits) {
3865
 
                                bus->fc_xon++;
3866
 
                                delta = 1;
3867
 
                        }
3868
 
 
3869
 
                        if (delta) {
 
3810
                        fcbits = SDPCM_FCMASK_VALUE(
 
3811
                                        &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
 
3812
 
 
3813
                        if (bus->flowcontrol != fcbits) {
 
3814
                                if (~bus->flowcontrol & fcbits)
 
3815
                                        bus->fc_xoff++;
 
3816
 
 
3817
                                if (bus->flowcontrol & ~fcbits)
 
3818
                                        bus->fc_xon++;
 
3819
 
3870
3820
                                bus->fc_rcvd++;
3871
3821
                                bus->flowcontrol = fcbits;
3872
3822
                        }
3889
3839
                        bus->tx_max = txmax;
3890
3840
 
3891
3841
#ifdef DHD_DEBUG
3892
 
                        if (DHD_BYTES_ON() && DHD_DATA_ON())
3893
 
                                prhex("Rx Data", rxbuf, len);
3894
 
                        else if (DHD_HDRS_ON())
3895
 
                                prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
 
3842
                        if (DHD_BYTES_ON() && DHD_DATA_ON()) {
 
3843
                                printk(KERN_DEBUG "Rx Data:\n");
 
3844
                                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
3845
                                                     rxbuf, len);
 
3846
                        } else if (DHD_HDRS_ON()) {
 
3847
                                printk(KERN_DEBUG "RxHdr:\n");
 
3848
                                print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
3849
                                                     bus->rxhdr, SDPCM_HDRLEN);
 
3850
                        }
3896
3851
#endif
3897
3852
 
3898
3853
                        if (chan == SDPCM_CONTROL_CHANNEL) {
3899
3854
                                if (bus->bus == SPI_BUS) {
3900
3855
                                        dhdsdio_read_control(bus, rxbuf, len,
3901
3856
                                                             doff);
3902
 
                                        if (bus->usebufpool) {
3903
 
                                                dhd_os_sdlock_rxq(bus->dhd);
3904
 
                                                pkt_buf_free_skb(bus->dhd->osh, pkt,
3905
 
                                                        false);
3906
 
                                                dhd_os_sdunlock_rxq(bus->dhd);
3907
 
                                        }
3908
 
                                        continue;
3909
3857
                                } else {
3910
3858
                                        DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3911
3859
                                                __func__, seq));
3912
3860
                                        /* Force retry w/normal header read */
3913
3861
                                        bus->nextlen = 0;
3914
3862
                                        dhdsdio_rxfail(bus, false, true);
3915
 
                                        dhd_os_sdlock_rxq(bus->dhd);
3916
 
                                        PKTFREE2();
3917
 
                                        dhd_os_sdunlock_rxq(bus->dhd);
3918
 
                                        continue;
3919
3863
                                }
 
3864
                                dhdsdio_pktfree2(bus, pkt);
 
3865
                                continue;
3920
3866
                        }
3921
3867
 
3922
3868
                        if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3929
3875
                        if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3930
3876
                                DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3931
3877
                                        __func__, doff, len, SDPCM_HDRLEN));
3932
 
                                dhd_os_sdlock_rxq(bus->dhd);
3933
 
                                PKTFREE2();
3934
 
                                dhd_os_sdunlock_rxq(bus->dhd);
3935
 
                                ASSERT(0);
3936
3878
                                dhdsdio_rxfail(bus, false, false);
 
3879
                                dhdsdio_pktfree2(bus, pkt);
3937
3880
                                continue;
3938
3881
                        }
3939
3882
 
3945
3888
                        break;
3946
3889
 
3947
3890
                /* Read frame header (hardware and software) */
3948
 
                sdret =
3949
 
                    dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3950
 
                                        F2SYNC, bus->rxhdr, firstread, NULL,
3951
 
                                        NULL, NULL);
 
3891
                sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
 
3892
                                SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
 
3893
                                NULL, NULL, NULL);
3952
3894
                bus->f2rxhdrs++;
3953
 
                ASSERT(sdret != BCME_PENDING);
 
3895
                ASSERT(sdret != -BCME_PENDING);
3954
3896
 
3955
3897
                if (sdret < 0) {
3956
3898
                        DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3960
3902
                        continue;
3961
3903
                }
3962
3904
#ifdef DHD_DEBUG
3963
 
                if (DHD_BYTES_ON() || DHD_HDRS_ON())
3964
 
                        prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
 
3905
                if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
 
3906
                        printk(KERN_DEBUG "RxHdr:\n");
 
3907
                        print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
3908
                                             bus->rxhdr, SDPCM_HDRLEN);
 
3909
                }
3965
3910
#endif
3966
3911
 
3967
3912
                /* Extract hardware header fields */
3968
 
                len = ltoh16_ua(bus->rxhdr);
3969
 
                check = ltoh16_ua(bus->rxhdr + sizeof(u16));
 
3913
                len = get_unaligned_le16(bus->rxhdr);
 
3914
                check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3970
3915
 
3971
3916
                /* All zeros means no more frames */
3972
3917
                if (!(len | check)) {
4020
3965
                /* Handle Flow Control */
4021
3966
                fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4022
3967
 
4023
 
                delta = 0;
4024
 
                if (~bus->flowcontrol & fcbits) {
4025
 
                        bus->fc_xoff++;
4026
 
                        delta = 1;
4027
 
                }
4028
 
                if (bus->flowcontrol & ~fcbits) {
4029
 
                        bus->fc_xon++;
4030
 
                        delta = 1;
4031
 
                }
4032
 
 
4033
 
                if (delta) {
 
3968
                if (bus->flowcontrol != fcbits) {
 
3969
                        if (~bus->flowcontrol & fcbits)
 
3970
                                bus->fc_xoff++;
 
3971
 
 
3972
                        if (bus->flowcontrol & ~fcbits)
 
3973
                                bus->fc_xon++;
 
3974
 
4034
3975
                        bus->fc_rcvd++;
4035
3976
                        bus->flowcontrol = fcbits;
4036
3977
                }
4091
4032
                }
4092
4033
 
4093
4034
                dhd_os_sdlock_rxq(bus->dhd);
4094
 
                pkt = pkt_buf_get_skb(osh, (rdlen + firstread + DHD_SDALIGN));
 
4035
                pkt = bcm_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4095
4036
                if (!pkt) {
4096
4037
                        /* Give up on data, request rtx of events */
4097
 
                        DHD_ERROR(("%s: pkt_buf_get_skb failed: rdlen %d chan %d\n",
4098
 
                                   __func__, rdlen, chan));
 
4038
                        DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed: rdlen %d "
 
4039
                                "chan %d\n", __func__, rdlen, chan));
4099
4040
                        bus->dhd->rx_dropped++;
4100
4041
                        dhd_os_sdunlock_rxq(bus->dhd);
4101
4042
                        dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4108
4049
                /* Leave room for what we already read, and align remainder */
4109
4050
                ASSERT(firstread < pkt->len);
4110
4051
                skb_pull(pkt, firstread);
4111
 
                PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
 
4052
                PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4112
4053
 
4113
4054
                /* Read the remaining frame data */
4114
 
                sdret =
4115
 
                    dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
 
4055
                sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4116
4056
                                        F2SYNC, ((u8 *) (pkt->data)), rdlen,
4117
4057
                                        pkt, NULL, NULL);
4118
4058
                bus->f2rxdata++;
4119
 
                ASSERT(sdret != BCME_PENDING);
 
4059
                ASSERT(sdret != -BCME_PENDING);
4120
4060
 
4121
4061
                if (sdret < 0) {
4122
4062
                        DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4127
4067
                                       ? "data" : "test")),
4128
4068
                                   sdret));
4129
4069
                        dhd_os_sdlock_rxq(bus->dhd);
4130
 
                        pkt_buf_free_skb(bus->dhd->osh, pkt, false);
 
4070
                        bcm_pkt_buf_free_skb(pkt);
4131
4071
                        dhd_os_sdunlock_rxq(bus->dhd);
4132
4072
                        bus->dhd->rx_errors++;
4133
4073
                        dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4136
4076
 
4137
4077
                /* Copy the already-read portion */
4138
4078
                skb_push(pkt, firstread);
4139
 
                bcopy(bus->rxhdr, pkt->data, firstread);
 
4079
                memcpy(pkt->data, bus->rxhdr, firstread);
4140
4080
 
4141
4081
#ifdef DHD_DEBUG
4142
 
                if (DHD_BYTES_ON() && DHD_DATA_ON())
4143
 
                        prhex("Rx Data", pkt->data, len);
 
4082
                if (DHD_BYTES_ON() && DHD_DATA_ON()) {
 
4083
                        printk(KERN_DEBUG "Rx Data:\n");
 
4084
                        print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
 
4085
                                             pkt->data, len);
 
4086
                }
4144
4087
#endif
4145
4088
 
4146
4089
deliver:
4151
4094
                                        __func__, len));
4152
4095
#ifdef DHD_DEBUG
4153
4096
                                if (DHD_GLOM_ON()) {
4154
 
                                        prhex("Glom Data", pkt->data, len);
 
4097
                                        printk(KERN_DEBUG "Glom Data:\n");
 
4098
                                        print_hex_dump_bytes("",
 
4099
                                                             DUMP_PREFIX_OFFSET,
 
4100
                                                             pkt->data, len);
4155
4101
                                }
4156
4102
#endif
4157
4103
                                __skb_trim(pkt, len);
4180
4126
 
4181
4127
                if (pkt->len == 0) {
4182
4128
                        dhd_os_sdlock_rxq(bus->dhd);
4183
 
                        pkt_buf_free_skb(bus->dhd->osh, pkt, false);
 
4129
                        bcm_pkt_buf_free_skb(pkt);
4184
4130
                        dhd_os_sdunlock_rxq(bus->dhd);
4185
4131
                        continue;
4186
4132
                } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4187
4133
                        DHD_ERROR(("%s: rx protocol error\n", __func__));
4188
4134
                        dhd_os_sdlock_rxq(bus->dhd);
4189
 
                        pkt_buf_free_skb(bus->dhd->osh, pkt, false);
 
4135
                        bcm_pkt_buf_free_skb(pkt);
4190
4136
                        dhd_os_sdunlock_rxq(bus->dhd);
4191
4137
                        bus->dhd->rx_errors++;
4192
4138
                        continue;
4259
4205
 
4260
4206
        /*
4261
4207
         * Flow Control has been moved into the RX headers and this out of band
4262
 
         * method isn't used any more.  Leae this here for possibly
4263
 
         * remaining backward
4264
 
         * compatible with older dongles
 
4208
         * method isn't used any more.
 
4209
         * remaining backward compatible with older dongles.
4265
4210
         */
4266
4211
        if (hmb_data & HMB_DATA_FC) {
4267
 
                fcbits =
4268
 
                    (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
 
4212
                fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
 
4213
                                                        HMB_DATA_FCDATA_SHIFT;
4269
4214
 
4270
4215
                if (fcbits & ~bus->flowcontrol)
4271
4216
                        bus->fc_xoff++;
 
4217
 
4272
4218
                if (bus->flowcontrol & ~fcbits)
4273
4219
                        bus->fc_xon++;
4274
4220
 
4468
4414
                                        F2SYNC, (u8 *) bus->ctrl_frame_buf,
4469
4415
                                        (u32) bus->ctrl_frame_len, NULL,
4470
4416
                                        NULL, NULL);
4471
 
                ASSERT(ret != BCME_PENDING);
 
4417
                ASSERT(ret != -BCME_PENDING);
4472
4418
 
4473
4419
                if (ret < 0) {
4474
4420
                        /* On failure, abort the command and
4501
4447
                if (ret == 0)
4502
4448
                        bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4503
4449
 
4504
 
                printf("Return_dpc value is : %d\n", ret);
 
4450
                DHD_INFO(("Return_dpc value is : %d\n", ret));
4505
4451
                bus->ctrl_frame_stat = false;
4506
4452
                dhd_wait_event_wakeup(bus->dhd);
4507
4453
        }
4508
4454
        /* Send queued frames (limit 1 if rx may still be pending) */
4509
4455
        else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4510
 
                 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
 
4456
                 bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4511
4457
                 && DATAOK(bus)) {
4512
4458
                framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4513
4459
                framecnt = dhdsdio_sendfromq(bus, framecnt);
4528
4474
                        "I_CHIPACTIVE interrupt\n", __func__));
4529
4475
                resched = true;
4530
4476
        } else if (bus->intstatus || bus->ipend ||
4531
 
                (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
 
4477
                (!bus->fcstate && bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4532
4478
                        DATAOK(bus)) || PKT_AVAILABLE()) {
4533
4479
                resched = true;
4534
4480
        }
4635
4581
        u8 *data;
4636
4582
        uint pktcount;
4637
4583
        uint fillbyte;
4638
 
        struct osl_info *osh = bus->dhd->osh;
4639
4584
        u16 len;
4640
4585
 
4641
4586
        /* Display current count if appropriate */
4642
4587
        if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4643
4588
                bus->pktgen_ptick = 0;
4644
 
                printf("%s: send attempts %d rcvd %d\n",
 
4589
                printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4645
4590
                       __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4646
4591
        }
4647
4592
 
4663
4608
 
4664
4609
                /* Allocate an appropriate-sized packet */
4665
4610
                len = bus->pktgen_len;
4666
 
                pkt = pkt_buf_get_skb(osh,
 
4611
                pkt = bcm_pkt_buf_get_skb(
4667
4612
                        (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4668
4613
                        true);
4669
4614
                if (!pkt) {
4670
 
                        DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
 
4615
                        DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n",
 
4616
                                __func__));
4671
4617
                        break;
4672
4618
                }
4673
 
                PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
 
4619
                PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4674
4620
                         DHD_SDALIGN);
4675
4621
                data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4676
4622
 
4694
4640
                default:
4695
4641
                        DHD_ERROR(("Unrecognized pktgen mode %d\n",
4696
4642
                                   bus->pktgen_mode));
4697
 
                        pkt_buf_free_skb(osh, pkt, true);
 
4643
                        bcm_pkt_buf_free_skb(pkt, true);
4698
4644
                        bus->pktgen_count = 0;
4699
4645
                        return;
4700
4646
                }
4712
4658
#ifdef DHD_DEBUG
4713
4659
                if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4714
4660
                        data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4715
 
                        prhex("dhdsdio_pktgen: Tx Data", data,
4716
 
                              pkt->len - SDPCM_HDRLEN);
 
4661
                        printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
 
4662
                        print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
 
4663
                                             pkt->len - SDPCM_HDRLEN);
4717
4664
                }
4718
4665
#endif
4719
4666
 
4740
4687
{
4741
4688
        struct sk_buff *pkt;
4742
4689
        u8 *data;
4743
 
        struct osl_info *osh = bus->dhd->osh;
4744
4690
 
4745
4691
        /* Allocate the packet */
4746
 
        pkt = pkt_buf_get_skb(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4747
 
                        true);
 
4692
        pkt = bcm_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
 
4693
                DHD_SDALIGN, true);
4748
4694
        if (!pkt) {
4749
 
                DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
 
4695
                DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n", __func__));
4750
4696
                return;
4751
4697
        }
4752
 
        PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
 
4698
        PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4753
4699
        data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4754
4700
 
4755
4701
        /* Fill in the test header */
4765
4711
 
4766
4712
static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4767
4713
{
4768
 
        struct osl_info *osh = bus->dhd->osh;
4769
4714
        u8 *data;
4770
4715
        uint pktlen;
4771
4716
 
4779
4724
        if (pktlen < SDPCM_TEST_HDRLEN) {
4780
4725
                DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4781
4726
                           pktlen));
4782
 
                pkt_buf_free_skb(osh, pkt, false);
 
4727
                bcm_pkt_buf_free_skb(pkt, false);
4783
4728
                return;
4784
4729
        }
4785
4730
 
4797
4742
                        DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4798
4743
                                "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4799
4744
                                pktlen, seq, cmd, extra, len));
4800
 
                        pkt_buf_free_skb(osh, pkt, false);
 
4745
                        bcm_pkt_buf_free_skb(pkt, false);
4801
4746
                        return;
4802
4747
                }
4803
4748
        }
4812
4757
                        bus->pktgen_sent++;
4813
4758
                } else {
4814
4759
                        bus->pktgen_fail++;
4815
 
                        pkt_buf_free_skb(osh, pkt, false);
 
4760
                        bcm_pkt_buf_free_skb(pkt, false);
4816
4761
                }
4817
4762
                bus->pktgen_rcvd++;
4818
4763
                break;
4819
4764
 
4820
4765
        case SDPCM_TEST_ECHORSP:
4821
4766
                if (bus->ext_loop) {
4822
 
                        pkt_buf_free_skb(osh, pkt, false);
 
4767
                        bcm_pkt_buf_free_skb(pkt, false);
4823
4768
                        bus->pktgen_rcvd++;
4824
4769
                        break;
4825
4770
                }
4832
4777
                                break;
4833
4778
                        }
4834
4779
                }
4835
 
                pkt_buf_free_skb(osh, pkt, false);
 
4780
                bcm_pkt_buf_free_skb(pkt, false);
4836
4781
                bus->pktgen_rcvd++;
4837
4782
                break;
4838
4783
 
4839
4784
        case SDPCM_TEST_DISCARD:
4840
 
                pkt_buf_free_skb(osh, pkt, false);
 
4785
                bcm_pkt_buf_free_skb(pkt, false);
4841
4786
                bus->pktgen_rcvd++;
4842
4787
                break;
4843
4788
 
4847
4792
                DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4848
4793
                        "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4849
4794
                        pktlen, seq, cmd, extra, len));
4850
 
                pkt_buf_free_skb(osh, pkt, false);
 
4795
                bcm_pkt_buf_free_skb(pkt, false);
4851
4796
                break;
4852
4797
        }
4853
4798
 
4969
4914
 
4970
4915
        /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4971
4916
        if (bus->console_addr == 0)
4972
 
                return BCME_UNSUPPORTED;
 
4917
                return -ENOTSUPP;
4973
4918
 
4974
4919
        /* Exclusive bus access */
4975
4920
        dhd_os_sdlock(bus->dhd);
4977
4922
        /* Don't allow input if dongle is in reset */
4978
4923
        if (bus->dhd->dongle_reset) {
4979
4924
                dhd_os_sdunlock(bus->dhd);
4980
 
                return BCME_NOTREADY;
 
4925
                return -EPERM;
4981
4926
        }
4982
4927
 
4983
4928
        /* Request clock to allow SDIO accesses */
4987
4932
 
4988
4933
        /* Zero cbuf_index */
4989
4934
        addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf_idx);
4990
 
        val = htol32(0);
 
4935
        val = cpu_to_le32(0);
4991
4936
        rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4992
4937
        if (rv < 0)
4993
4938
                goto done;
5000
4945
 
5001
4946
        /* Write length into vcons_in */
5002
4947
        addr = bus->console_addr + offsetof(hndrte_cons_t, vcons_in);
5003
 
        val = htol32(msglen);
 
4948
        val = cpu_to_le32(msglen);
5004
4949
        rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5005
4950
        if (rv < 0)
5006
4951
                goto done;
5008
4953
        /* Bump dongle by sending an empty event pkt.
5009
4954
         * sdpcm_sendup (RX) checks for virtual console input.
5010
4955
         */
5011
 
        pkt = pkt_buf_get_skb(bus->dhd->osh, 4 + SDPCM_RESERVE);
 
4956
        pkt = bcm_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5012
4957
        if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5013
4958
                dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5014
4959
 
5066
5011
 
5067
5012
static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5068
5013
                           u16 slot, u16 func, uint bustype, void *regsva,
5069
 
                           struct osl_info *osh, void *sdh)
 
5014
                           void *sdh)
5070
5015
{
5071
5016
        int ret;
5072
5017
        dhd_bus_t *bus;
5085
5030
        sd1idle = true;
5086
5031
        dhd_readahead = true;
5087
5032
        retrydata = false;
5088
 
        dhd_doflow = false;
5089
5033
        dhd_dongle_memsize = 0;
5090
5034
        dhd_txminmax = DHD_TXMINMAX;
5091
5035
 
5107
5051
        /* Check the Vendor ID */
5108
5052
        switch (venid) {
5109
5053
        case 0x0000:
5110
 
        case VENDOR_BROADCOM:
 
5054
        case PCI_VENDOR_ID_BROADCOM:
5111
5055
                break;
5112
5056
        default:
5113
5057
                DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5143
5087
                return NULL;
5144
5088
        }
5145
5089
 
5146
 
        if (osh == NULL) {
5147
 
                /* Ask the OS interface part for an OSL handle */
5148
 
                osh = dhd_osl_attach(sdh, DHD_BUS);
5149
 
                if (!osh) {
5150
 
                        DHD_ERROR(("%s: osl_attach failed!\n", __func__));
5151
 
                        return NULL;
5152
 
                }
5153
 
        }
5154
 
 
5155
5090
        /* Allocate private bus interface state */
5156
5091
        bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5157
5092
        if (!bus) {
5166
5101
                                         else use locally malloced rxbuf */
5167
5102
 
5168
5103
        /* attempt to attach to the dongle */
5169
 
        if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
 
5104
        if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5170
5105
                DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5171
5106
                goto fail;
5172
5107
        }
5173
5108
 
5174
5109
        /* Attach to the dhd/OS/network interface */
5175
 
        bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE);
 
5110
        bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5176
5111
        if (!bus->dhd) {
5177
5112
                DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5178
5113
                goto fail;
5179
5114
        }
5180
5115
 
5181
5116
        /* Allocate buffers */
5182
 
        if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
 
5117
        if (!(dhdsdio_probe_malloc(bus, sdh))) {
5183
5118
                DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5184
5119
                goto fail;
5185
5120
        }
5186
5121
 
5187
 
        if (!(dhdsdio_probe_init(bus, osh, sdh))) {
 
5122
        if (!(dhdsdio_probe_init(bus, sdh))) {
5188
5123
                DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5189
5124
                goto fail;
5190
5125
        }
5206
5141
        /* if firmware path present try to download and bring up bus */
5207
5142
        ret = dhd_bus_start(bus->dhd);
5208
5143
        if (ret != 0) {
5209
 
                if (ret == BCME_NOTUP) {
 
5144
                if (ret == -ENOLINK) {
5210
5145
                        DHD_ERROR(("%s: dongle is not responding\n", __func__));
5211
5146
                        goto fail;
5212
5147
                }
5220
5155
        return bus;
5221
5156
 
5222
5157
fail:
5223
 
        dhdsdio_release(bus, osh);
 
5158
        dhdsdio_release(bus);
5224
5159
        return NULL;
5225
5160
}
5226
5161
 
5227
5162
static bool
5228
 
dhdsdio_probe_attach(struct dhd_bus *bus, struct osl_info *osh, void *sdh,
5229
 
                        void *regsva, u16 devid)
 
5163
dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5230
5164
{
5231
5165
        u8 clkctl = 0;
5232
5166
        int err = 0;
5238
5172
                DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5239
5173
 
5240
5174
#ifdef DHD_DEBUG
5241
 
        printf("F1 signature read @0x18000000=0x%4x\n",
 
5175
        printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5242
5176
               bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5243
5177
 
5244
5178
#endif                          /* DHD_DEBUG */
5245
5179
 
5246
 
        /* Force PLL off until si_attach() programs PLL control regs */
 
5180
        /*
 
5181
         * Force PLL off until dhdsdio_chip_attach()
 
5182
         * programs PLL control regs
 
5183
         */
5247
5184
 
5248
5185
        bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5249
5186
                         DHD_INIT_CLKCTL1, &err);
5279
5216
                udelay(65);
5280
5217
 
5281
5218
                for (fn = 0; fn <= numfn; fn++) {
5282
 
                        cis[fn] = kmalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
 
5219
                        cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5283
5220
                        if (!cis[fn]) {
5284
5221
                                DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5285
5222
                                        "failed\n", fn));
5286
5223
                                break;
5287
5224
                        }
5288
 
                        memset(cis[fn], 0, SBSDIO_CIS_SIZE_LIMIT);
5289
5225
 
5290
5226
                        err = bcmsdh_cis_read(sdh, fn, cis[fn],
5291
5227
                                                SBSDIO_CIS_SIZE_LIMIT);
5310
5246
        }
5311
5247
#endif                          /* DHD_DEBUG */
5312
5248
 
5313
 
        /* si_attach() will provide an SI handle and scan the backplane */
5314
 
        bus->sih = si_attach((uint) devid, osh, regsva, DHD_BUS, sdh,
5315
 
                                   &bus->vars, &bus->varsz);
5316
 
        if (!(bus->sih)) {
5317
 
                DHD_ERROR(("%s: si_attach failed!\n", __func__));
 
5249
        if (dhdsdio_chip_attach(bus, regsva)) {
 
5250
                DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5318
5251
                goto fail;
5319
5252
        }
5320
5253
 
5321
 
        bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
 
5254
        bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5322
5255
 
5323
 
        if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
 
5256
        if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5324
5257
                DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5325
 
                           __func__, bus->sih->chip));
 
5258
                           __func__, bus->ci->chip));
5326
5259
                goto fail;
5327
5260
        }
5328
5261
 
5329
 
        si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
 
5262
        dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5330
5263
 
5331
5264
        /* Get info on the ARM and SOCRAM cores... */
5332
5265
        if (!DHD_NOPMU(bus)) {
5333
 
                if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5334
 
                    (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5335
 
                        bus->armrev = si_corerev(bus->sih);
5336
 
                } else {
5337
 
                        DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5338
 
                        goto fail;
5339
 
                }
5340
 
                bus->orig_ramsize = si_socram_size(bus->sih);
 
5266
                bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
 
5267
                        CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
 
5268
                bus->orig_ramsize = bus->ci->ramsize;
5341
5269
                if (!(bus->orig_ramsize)) {
5342
5270
                        DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5343
5271
                                   __func__));
5351
5279
                           bus->ramsize, bus->orig_ramsize));
5352
5280
        }
5353
5281
 
5354
 
        /* ...but normally deal with the SDPCMDEV core */
5355
 
        bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5356
 
        if (!bus->regs) {
5357
 
                bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5358
 
                if (!bus->regs) {
5359
 
                        DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5360
 
                                        __func__));
5361
 
                        goto fail;
5362
 
                }
5363
 
        }
5364
 
        bus->sdpcmrev = si_corerev(bus->sih);
 
5282
        bus->regs = (void *)bus->ci->buscorebase;
5365
5283
 
5366
5284
        /* Set core control so an SDIO reset does a backplane reset */
5367
 
        OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
 
5285
        OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5368
5286
 
5369
 
        pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
 
5287
        bcm_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5370
5288
 
5371
5289
        /* Locate an appropriately-aligned portion of hdrbuf */
5372
5290
        bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5383
5301
        return false;
5384
5302
}
5385
5303
 
5386
 
static bool dhdsdio_probe_malloc(dhd_bus_t *bus, struct osl_info *osh,
5387
 
                                 void *sdh)
 
5304
static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5388
5305
{
5389
5306
        DHD_TRACE(("%s: Enter\n", __func__));
5390
5307
 
5425
5342
        return false;
5426
5343
}
5427
5344
 
5428
 
static bool dhdsdio_probe_init(dhd_bus_t *bus, struct osl_info *osh, void *sdh)
 
5345
static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5429
5346
{
5430
5347
        s32 fnum;
5431
5348
 
5455
5372
        /* Query the SD clock speed */
5456
5373
        if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5457
5374
                            &bus->sd_divisor, sizeof(s32),
5458
 
                            false) != BCME_OK) {
 
5375
                            false) != 0) {
5459
5376
                DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5460
5377
                bus->sd_divisor = -1;
5461
5378
        } else {
5465
5382
 
5466
5383
        /* Query the SD bus mode */
5467
5384
        if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5468
 
                            &bus->sd_mode, sizeof(s32), false) != BCME_OK) {
 
5385
                            &bus->sd_mode, sizeof(s32), false) != 0) {
5469
5386
                DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5470
5387
                bus->sd_mode = -1;
5471
5388
        } else {
5476
5393
        /* Query the F2 block size, set roundup accordingly */
5477
5394
        fnum = 2;
5478
5395
        if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5479
 
                            &bus->blocksize, sizeof(s32), false) != BCME_OK) {
 
5396
                            &bus->blocksize, sizeof(s32), false) != 0) {
5480
5397
                bus->blocksize = 0;
5481
5398
                DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5482
5399
        } else {
5489
5406
                 default to use if supported */
5490
5407
        if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5491
5408
                            &bus->sd_rxchain, sizeof(s32),
5492
 
                            false) != BCME_OK) {
 
5409
                            false) != 0) {
5493
5410
                bus->sd_rxchain = false;
5494
5411
        } else {
5495
5412
                DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5502
5419
}
5503
5420
 
5504
5421
bool
5505
 
dhd_bus_download_firmware(struct dhd_bus *bus, struct osl_info *osh,
5506
 
                          char *fw_path, char *nv_path)
 
5422
dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5507
5423
{
5508
5424
        bool ret;
5509
5425
        bus->fw_path = fw_path;
5510
5426
        bus->nv_path = nv_path;
5511
5427
 
5512
 
        ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
 
5428
        ret = dhdsdio_download_firmware(bus, bus->sdh);
5513
5429
 
5514
5430
        return ret;
5515
5431
}
5516
5432
 
5517
5433
static bool
5518
 
dhdsdio_download_firmware(struct dhd_bus *bus, struct osl_info *osh, void *sdh)
 
5434
dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5519
5435
{
5520
5436
        bool ret;
5521
5437
 
5530
5446
}
5531
5447
 
5532
5448
/* Detach and free everything */
5533
 
static void dhdsdio_release(dhd_bus_t *bus, struct osl_info *osh)
 
5449
static void dhdsdio_release(dhd_bus_t *bus)
5534
5450
{
5535
5451
        DHD_TRACE(("%s: Enter\n", __func__));
5536
5452
 
5537
5453
        if (bus) {
5538
 
                ASSERT(osh);
5539
 
 
5540
5454
                /* De-register interrupt handler */
5541
5455
                bcmsdh_intr_disable(bus->sdh);
5542
5456
                bcmsdh_intr_dereg(bus->sdh);
5543
5457
 
5544
5458
                if (bus->dhd) {
5545
 
 
5546
 
                        dhdsdio_release_dongle(bus, osh);
5547
 
 
5548
5459
                        dhd_detach(bus->dhd);
 
5460
                        dhdsdio_release_dongle(bus);
5549
5461
                        bus->dhd = NULL;
5550
5462
                }
5551
5463
 
5552
 
                dhdsdio_release_malloc(bus, osh);
 
5464
                dhdsdio_release_malloc(bus);
5553
5465
 
5554
5466
                kfree(bus);
5555
5467
        }
5556
5468
 
5557
 
        if (osh)
5558
 
                dhd_osl_detach(osh);
5559
 
 
5560
5469
        DHD_TRACE(("%s: Disconnected\n", __func__));
5561
5470
}
5562
5471
 
5563
 
static void dhdsdio_release_malloc(dhd_bus_t *bus, struct osl_info *osh)
 
5472
static void dhdsdio_release_malloc(dhd_bus_t *bus)
5564
5473
{
5565
5474
        DHD_TRACE(("%s: Enter\n", __func__));
5566
5475
 
5573
5482
                bus->rxlen = 0;
5574
5483
        }
5575
5484
 
5576
 
        if (bus->databuf) {
5577
 
                kfree(bus->databuf);
5578
 
                bus->databuf = NULL;
5579
 
        }
 
5485
        kfree(bus->databuf);
 
5486
        bus->databuf = NULL;
5580
5487
}
5581
5488
 
5582
 
static void dhdsdio_release_dongle(dhd_bus_t *bus, struct osl_info *osh)
 
5489
static void dhdsdio_release_dongle(dhd_bus_t *bus)
5583
5490
{
5584
5491
        DHD_TRACE(("%s: Enter\n", __func__));
5585
5492
 
5586
5493
        if (bus->dhd && bus->dhd->dongle_reset)
5587
5494
                return;
5588
5495
 
5589
 
        if (bus->sih) {
 
5496
        if (bus->ci) {
5590
5497
                dhdsdio_clkctl(bus, CLK_AVAIL, false);
5591
 
#if !defined(BCMLXSDMMC)
5592
 
                si_watchdog(bus->sih, 4);
5593
 
#endif                          /* !defined(BCMLXSDMMC) */
5594
5498
                dhdsdio_clkctl(bus, CLK_NONE, false);
5595
 
                si_detach(bus->sih);
 
5499
                dhdsdio_chip_detach(bus);
5596
5500
                if (bus->vars && bus->varsz)
5597
5501
                        kfree(bus->vars);
5598
5502
                bus->vars = NULL;
5609
5513
 
5610
5514
        if (bus) {
5611
5515
                ASSERT(bus->dhd);
5612
 
                dhdsdio_release(bus, bus->dhd->osh);
 
5516
                dhdsdio_release(bus);
5613
5517
        }
5614
5518
 
5615
5519
        DHD_TRACE(("%s: Disconnected\n", __func__));
5679
5583
                unsigned char *ularray;
5680
5584
 
5681
5585
                ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
 
5586
                if (!ularray) {
 
5587
                        bcmerror = -ENOMEM;
 
5588
                        goto err;
 
5589
                }
5682
5590
                /* Upload image to verify downloaded contents. */
5683
5591
                offset = 0;
5684
5592
                memset(ularray, 0xaa, bus->ramsize);
5690
5598
                                DHD_ERROR(("%s: error %d on reading %d membytes"
5691
5599
                                        " at 0x%08x\n",
5692
5600
                                        __func__, bcmerror, MEMBLOCK, offset));
5693
 
                                goto err;
 
5601
                                goto free;
5694
5602
                        }
5695
5603
 
5696
5604
                        offset += MEMBLOCK;
5704
5612
                                DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5705
5613
                                __func__, bcmerror,
5706
5614
                                sizeof(dlarray) - offset, offset));
5707
 
                                goto err;
 
5615
                                goto free;
5708
5616
                        }
5709
5617
                }
5710
5618
 
5712
5620
                        DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5713
5621
                                   __func__));
5714
5622
                        ASSERT(0);
5715
 
                        goto err;
 
5623
                        goto free;
5716
5624
                } else
5717
5625
                        DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5718
5626
                                __func__));
5719
 
 
 
5627
free:
5720
5628
                kfree(ularray);
5721
5629
        }
5722
5630
#endif                          /* DHD_DEBUG */
5764
5672
        }
5765
5673
 
5766
5674
err:
5767
 
        if (memblock)
5768
 
                kfree(memblock);
 
5675
        kfree(memblock);
5769
5676
 
5770
5677
        if (image)
5771
5678
                dhd_os_close_image(image);
5900
5807
        } else {
5901
5808
                DHD_ERROR(("%s: error reading nvram file: %d\n",
5902
5809
                           __func__, len));
5903
 
                bcmerror = BCME_SDIO_ERROR;
 
5810
                bcmerror = -EIO;
5904
5811
        }
5905
5812
 
5906
5813
err:
5907
 
        if (memblock)
5908
 
                kfree(memblock);
 
5814
        kfree(memblock);
5909
5815
 
5910
5816
        if (image)
5911
5817
                dhd_os_close_image(image);
5990
5896
        return bcmerror;
5991
5897
}
5992
5898
 
5993
 
static int
5994
 
dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5995
 
                    u8 *buf, uint nbytes, struct sk_buff *pkt,
5996
 
                    bcmsdh_cmplt_fn_t complete, void *handle)
5997
 
{
5998
 
        int status;
5999
 
 
6000
 
        /* 4329: GSPI check */
6001
 
        status =
6002
 
            bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
6003
 
                            complete, handle);
6004
 
        return status;
6005
 
}
6006
5899
 
6007
5900
static int
6008
5901
dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
6016
5909
 
6017
5910
uint dhd_bus_chip(struct dhd_bus *bus)
6018
5911
{
6019
 
        ASSERT(bus->sih != NULL);
6020
 
        return bus->sih->chip;
 
5912
        ASSERT(bus->ci != NULL);
 
5913
        return bus->ci->chip;
6021
5914
}
6022
5915
 
6023
5916
void *dhd_bus_pub(struct dhd_bus *bus)
6051
5944
 
6052
5945
                        /* Clean tx/rx buffer pointers,
6053
5946
                         detach from the dongle */
6054
 
                        dhdsdio_release_dongle(bus, bus->dhd->osh);
 
5947
                        dhdsdio_release_dongle(bus);
6055
5948
 
6056
5949
                        bus->dhd->dongle_reset = true;
6057
5950
                        bus->dhd->up = false;
6059
5952
                        DHD_TRACE(("%s:  WLAN OFF DONE\n", __func__));
6060
5953
                        /* App can now remove power from device */
6061
5954
                } else
6062
 
                        bcmerror = BCME_SDIO_ERROR;
 
5955
                        bcmerror = -EIO;
6063
5956
        } else {
6064
5957
                /* App must have restored power to device before calling */
6065
5958
 
6071
5964
                        bcmsdh_reset(bus->sdh);
6072
5965
 
6073
5966
                        /* Attempt to re-attach & download */
6074
 
                        if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
 
5967
                        if (dhdsdio_probe_attach(bus, bus->sdh,
6075
5968
                                                 (u32 *) SI_ENUM_BASE,
6076
5969
                                                 bus->cl_devid)) {
6077
5970
                                /* Attempt to download binary to the dongle */
6078
5971
                                if (dhdsdio_probe_init
6079
 
                                    (bus, bus->dhd->osh, bus->sdh)
 
5972
                                    (bus, bus->sdh)
6080
5973
                                    && dhdsdio_download_firmware(bus,
6081
 
                                                                 bus->dhd->osh,
6082
5974
                                                                 bus->sdh)) {
6083
5975
 
6084
5976
                                        /* Re-init bus, enable F2 transfer */
6095
5987
                                        DHD_TRACE(("%s: WLAN ON DONE\n",
6096
5988
                                                   __func__));
6097
5989
                                } else
6098
 
                                        bcmerror = BCME_SDIO_ERROR;
 
5990
                                        bcmerror = -EIO;
6099
5991
                        } else
6100
 
                                bcmerror = BCME_SDIO_ERROR;
 
5992
                                bcmerror = -EIO;
6101
5993
                } else {
6102
 
                        bcmerror = BCME_NOTDOWN;
 
5994
                        bcmerror = -EISCONN;
6103
5995
                        DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6104
5996
                                "is on\n", __func__));
6105
 
                        bcmerror = BCME_SDIO_ERROR;
 
5997
                        bcmerror = -EIO;
6106
5998
                }
6107
5999
        }
6108
6000
        return bcmerror;
6109
6001
}
 
6002
 
 
6003
static int
 
6004
dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
 
6005
{
 
6006
        u32 regdata;
 
6007
 
 
6008
        /*
 
6009
         * Get CC core rev
 
6010
         * Chipid is assume to be at offset 0 from regs arg
 
6011
         * For different chiptypes or old sdio hosts w/o chipcommon,
 
6012
         * other ways of recognition should be added here.
 
6013
         */
 
6014
        ci->cccorebase = (u32)regs;
 
6015
        regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
 
6016
        ci->chip = regdata & CID_ID_MASK;
 
6017
        ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
 
6018
 
 
6019
        DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
 
6020
                __func__, ci->chip, ci->chiprev));
 
6021
 
 
6022
        /* Address of cores for new chips should be added here */
 
6023
        switch (ci->chip) {
 
6024
        case BCM4329_CHIP_ID:
 
6025
                ci->buscorebase = BCM4329_CORE_BUS_BASE;
 
6026
                ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
 
6027
                ci->armcorebase = BCM4329_CORE_ARM_BASE;
 
6028
                ci->ramsize = BCM4329_RAMSIZE;
 
6029
                break;
 
6030
        default:
 
6031
                DHD_ERROR(("%s: chipid 0x%x is not supported\n",
 
6032
                        __func__, ci->chip));
 
6033
                return -ENODEV;
 
6034
        }
 
6035
 
 
6036
        regdata = bcmsdh_reg_read(sdh,
 
6037
                CORE_SB(ci->cccorebase, sbidhigh), 4);
 
6038
        ci->ccrev = SBCOREREV(regdata);
 
6039
 
 
6040
        regdata = bcmsdh_reg_read(sdh,
 
6041
                CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
 
6042
        ci->pmurev = regdata & PCAP_REV_MASK;
 
6043
 
 
6044
        regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
 
6045
        ci->buscorerev = SBCOREREV(regdata);
 
6046
        ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
 
6047
 
 
6048
        DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
 
6049
                __func__, ci->ccrev, ci->pmurev,
 
6050
                ci->buscorerev, ci->buscoretype));
 
6051
 
 
6052
        /* get chipcommon capabilites */
 
6053
        ci->cccaps = bcmsdh_reg_read(sdh,
 
6054
                CORE_CC_REG(ci->cccorebase, capabilities), 4);
 
6055
 
 
6056
        return 0;
 
6057
}
 
6058
 
 
6059
static void
 
6060
dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
 
6061
{
 
6062
        u32 regdata;
 
6063
 
 
6064
        regdata = bcmsdh_reg_read(sdh,
 
6065
                CORE_SB(corebase, sbtmstatelow), 4);
 
6066
        if (regdata & SBTML_RESET)
 
6067
                return;
 
6068
 
 
6069
        regdata = bcmsdh_reg_read(sdh,
 
6070
                CORE_SB(corebase, sbtmstatelow), 4);
 
6071
        if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
 
6072
                /*
 
6073
                 * set target reject and spin until busy is clear
 
6074
                 * (preserve core-specific bits)
 
6075
                 */
 
6076
                regdata = bcmsdh_reg_read(sdh,
 
6077
                        CORE_SB(corebase, sbtmstatelow), 4);
 
6078
                bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
 
6079
                        regdata | SBTML_REJ);
 
6080
 
 
6081
                regdata = bcmsdh_reg_read(sdh,
 
6082
                        CORE_SB(corebase, sbtmstatelow), 4);
 
6083
                udelay(1);
 
6084
                SPINWAIT((bcmsdh_reg_read(sdh,
 
6085
                        CORE_SB(corebase, sbtmstatehigh), 4) &
 
6086
                        SBTMH_BUSY), 100000);
 
6087
 
 
6088
                regdata = bcmsdh_reg_read(sdh,
 
6089
                        CORE_SB(corebase, sbtmstatehigh), 4);
 
6090
                if (regdata & SBTMH_BUSY)
 
6091
                        DHD_ERROR(("%s: ARM core still busy\n", __func__));
 
6092
 
 
6093
                regdata = bcmsdh_reg_read(sdh,
 
6094
                        CORE_SB(corebase, sbidlow), 4);
 
6095
                if (regdata & SBIDL_INIT) {
 
6096
                        regdata = bcmsdh_reg_read(sdh,
 
6097
                                CORE_SB(corebase, sbimstate), 4) |
 
6098
                                SBIM_RJ;
 
6099
                        bcmsdh_reg_write(sdh,
 
6100
                                CORE_SB(corebase, sbimstate), 4,
 
6101
                                regdata);
 
6102
                        regdata = bcmsdh_reg_read(sdh,
 
6103
                                CORE_SB(corebase, sbimstate), 4);
 
6104
                        udelay(1);
 
6105
                        SPINWAIT((bcmsdh_reg_read(sdh,
 
6106
                                CORE_SB(corebase, sbimstate), 4) &
 
6107
                                SBIM_BY), 100000);
 
6108
                }
 
6109
 
 
6110
                /* set reset and reject while enabling the clocks */
 
6111
                bcmsdh_reg_write(sdh,
 
6112
                        CORE_SB(corebase, sbtmstatelow), 4,
 
6113
                        (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
 
6114
                        SBTML_REJ | SBTML_RESET));
 
6115
                regdata = bcmsdh_reg_read(sdh,
 
6116
                        CORE_SB(corebase, sbtmstatelow), 4);
 
6117
                udelay(10);
 
6118
 
 
6119
                /* clear the initiator reject bit */
 
6120
                regdata = bcmsdh_reg_read(sdh,
 
6121
                        CORE_SB(corebase, sbidlow), 4);
 
6122
                if (regdata & SBIDL_INIT) {
 
6123
                        regdata = bcmsdh_reg_read(sdh,
 
6124
                                CORE_SB(corebase, sbimstate), 4) &
 
6125
                                ~SBIM_RJ;
 
6126
                        bcmsdh_reg_write(sdh,
 
6127
                                CORE_SB(corebase, sbimstate), 4,
 
6128
                                regdata);
 
6129
                }
 
6130
        }
 
6131
 
 
6132
        /* leave reset and reject asserted */
 
6133
        bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
 
6134
                (SBTML_REJ | SBTML_RESET));
 
6135
        udelay(1);
 
6136
}
 
6137
 
 
6138
static int
 
6139
dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
 
6140
{
 
6141
        struct chip_info *ci;
 
6142
        int err;
 
6143
        u8 clkval, clkset;
 
6144
 
 
6145
        DHD_TRACE(("%s: Enter\n", __func__));
 
6146
 
 
6147
        /* alloc chip_info_t */
 
6148
        ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
 
6149
        if (NULL == ci) {
 
6150
                DHD_ERROR(("%s: malloc failed!\n", __func__));
 
6151
                return -ENOMEM;
 
6152
        }
 
6153
 
 
6154
        memset((unsigned char *)ci, 0, sizeof(struct chip_info));
 
6155
 
 
6156
        /* bus/core/clk setup for register access */
 
6157
        /* Try forcing SDIO core to do ALPAvail request only */
 
6158
        clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
 
6159
        bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 
6160
                        clkset, &err);
 
6161
        if (err) {
 
6162
                DHD_ERROR(("%s: error writing for HT off\n", __func__));
 
6163
                goto fail;
 
6164
        }
 
6165
 
 
6166
        /* If register supported, wait for ALPAvail and then force ALP */
 
6167
        /* This may take up to 15 milliseconds */
 
6168
        clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
 
6169
                        SBSDIO_FUNC1_CHIPCLKCSR, NULL);
 
6170
        if ((clkval & ~SBSDIO_AVBITS) == clkset) {
 
6171
                SPINWAIT(((clkval =
 
6172
                                bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
 
6173
                                                SBSDIO_FUNC1_CHIPCLKCSR,
 
6174
                                                NULL)),
 
6175
                                !SBSDIO_ALPAV(clkval)),
 
6176
                                PMU_MAX_TRANSITION_DLY);
 
6177
                if (!SBSDIO_ALPAV(clkval)) {
 
6178
                        DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
 
6179
                                __func__, clkval));
 
6180
                        err = -EBUSY;
 
6181
                        goto fail;
 
6182
                }
 
6183
                clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
 
6184
                                SBSDIO_FORCE_ALP;
 
6185
                bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
 
6186
                                SBSDIO_FUNC1_CHIPCLKCSR,
 
6187
                                clkset, &err);
 
6188
                udelay(65);
 
6189
        } else {
 
6190
                DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
 
6191
                        __func__, clkset, clkval));
 
6192
                err = -EACCES;
 
6193
                goto fail;
 
6194
        }
 
6195
 
 
6196
        /* Also, disable the extra SDIO pull-ups */
 
6197
        bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
 
6198
                         NULL);
 
6199
 
 
6200
        err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
 
6201
        if (err)
 
6202
                goto fail;
 
6203
 
 
6204
        /*
 
6205
         * Make sure any on-chip ARM is off (in case strapping is wrong),
 
6206
         * or downloaded code was already running.
 
6207
         */
 
6208
        dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
 
6209
 
 
6210
        bcmsdh_reg_write(bus->sdh,
 
6211
                CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
 
6212
        bcmsdh_reg_write(bus->sdh,
 
6213
                CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
 
6214
 
 
6215
        /* Disable F2 to clear any intermediate frame state on the dongle */
 
6216
        bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
 
6217
                SDIO_FUNC_ENABLE_1, NULL);
 
6218
 
 
6219
        /* WAR: cmd52 backplane read so core HW will drop ALPReq */
 
6220
        clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
 
6221
                        0, NULL);
 
6222
 
 
6223
        /* Done with backplane-dependent accesses, can drop clock... */
 
6224
        bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
 
6225
                         NULL);
 
6226
 
 
6227
        bus->ci = ci;
 
6228
        return 0;
 
6229
fail:
 
6230
        bus->ci = NULL;
 
6231
        kfree(ci);
 
6232
        return err;
 
6233
}
 
6234
 
 
6235
static void
 
6236
dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
 
6237
{
 
6238
        u32 regdata;
 
6239
 
 
6240
        /*
 
6241
         * Must do the disable sequence first to work for
 
6242
         * arbitrary current core state.
 
6243
         */
 
6244
        dhdsdio_chip_disablecore(sdh, corebase);
 
6245
 
 
6246
        /*
 
6247
         * Now do the initialization sequence.
 
6248
         * set reset while enabling the clock and
 
6249
         * forcing them on throughout the core
 
6250
         */
 
6251
        bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
 
6252
                ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
 
6253
                SBTML_RESET);
 
6254
        udelay(1);
 
6255
 
 
6256
        regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
 
6257
        if (regdata & SBTMH_SERR)
 
6258
                bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
 
6259
 
 
6260
        regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
 
6261
        if (regdata & (SBIM_IBE | SBIM_TO))
 
6262
                bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
 
6263
                        regdata & ~(SBIM_IBE | SBIM_TO));
 
6264
 
 
6265
        /* clear reset and allow it to propagate throughout the core */
 
6266
        bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
 
6267
                (SICF_FGC << SBTML_SICF_SHIFT) |
 
6268
                (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
 
6269
        udelay(1);
 
6270
 
 
6271
        /* leave clock enabled */
 
6272
        bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
 
6273
                (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
 
6274
        udelay(1);
 
6275
}
 
6276
 
 
6277
/* SDIO Pad drive strength to select value mappings */
 
6278
struct sdiod_drive_str {
 
6279
        u8 strength;    /* Pad Drive Strength in mA */
 
6280
        u8 sel;         /* Chip-specific select value */
 
6281
};
 
6282
 
 
6283
/* SDIO Drive Strength to sel value table for PMU Rev 1 */
 
6284
static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
 
6285
        {
 
6286
        4, 0x2}, {
 
6287
        2, 0x3}, {
 
6288
        1, 0x0}, {
 
6289
        0, 0x0}
 
6290
        };
 
6291
 
 
6292
/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
 
6293
static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
 
6294
        {
 
6295
        12, 0x7}, {
 
6296
        10, 0x6}, {
 
6297
        8, 0x5}, {
 
6298
        6, 0x4}, {
 
6299
        4, 0x2}, {
 
6300
        2, 0x1}, {
 
6301
        0, 0x0}
 
6302
        };
 
6303
 
 
6304
/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
 
6305
static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
 
6306
        {
 
6307
        32, 0x7}, {
 
6308
        26, 0x6}, {
 
6309
        22, 0x5}, {
 
6310
        16, 0x4}, {
 
6311
        12, 0x3}, {
 
6312
        8, 0x2}, {
 
6313
        4, 0x1}, {
 
6314
        0, 0x0}
 
6315
        };
 
6316
 
 
6317
#define SDIOD_DRVSTR_KEY(chip, pmu)     (((chip) << 16) | (pmu))
 
6318
 
 
6319
static void
 
6320
dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
 
6321
        struct sdiod_drive_str *str_tab = NULL;
 
6322
        u32 str_mask = 0;
 
6323
        u32 str_shift = 0;
 
6324
        char chn[8];
 
6325
 
 
6326
        if (!(bus->ci->cccaps & CC_CAP_PMU))
 
6327
                return;
 
6328
 
 
6329
        switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
 
6330
        case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
 
6331
                str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
 
6332
                str_mask = 0x30000000;
 
6333
                str_shift = 28;
 
6334
                break;
 
6335
        case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
 
6336
        case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
 
6337
                str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
 
6338
                str_mask = 0x00003800;
 
6339
                str_shift = 11;
 
6340
                break;
 
6341
        case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
 
6342
                str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
 
6343
                str_mask = 0x00003800;
 
6344
                str_shift = 11;
 
6345
                break;
 
6346
        default:
 
6347
                DHD_ERROR(("No SDIO Drive strength init"
 
6348
                        "done for chip %s rev %d pmurev %d\n",
 
6349
                        bcm_chipname(bus->ci->chip, chn, 8),
 
6350
                        bus->ci->chiprev, bus->ci->pmurev));
 
6351
                break;
 
6352
        }
 
6353
 
 
6354
        if (str_tab != NULL) {
 
6355
                u32 drivestrength_sel = 0;
 
6356
                u32 cc_data_temp;
 
6357
                int i;
 
6358
 
 
6359
                for (i = 0; str_tab[i].strength != 0; i++) {
 
6360
                        if (drivestrength >= str_tab[i].strength) {
 
6361
                                drivestrength_sel = str_tab[i].sel;
 
6362
                                break;
 
6363
                        }
 
6364
                }
 
6365
 
 
6366
                bcmsdh_reg_write(bus->sdh,
 
6367
                        CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
 
6368
                        4, 1);
 
6369
                cc_data_temp = bcmsdh_reg_read(bus->sdh,
 
6370
                        CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
 
6371
                cc_data_temp &= ~str_mask;
 
6372
                drivestrength_sel <<= str_shift;
 
6373
                cc_data_temp |= drivestrength_sel;
 
6374
                bcmsdh_reg_write(bus->sdh,
 
6375
                        CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
 
6376
                        4, cc_data_temp);
 
6377
 
 
6378
                DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
 
6379
                        drivestrength, cc_data_temp));
 
6380
        }
 
6381
}
 
6382
 
 
6383
static void
 
6384
dhdsdio_chip_detach(struct dhd_bus *bus)
 
6385
{
 
6386
        DHD_TRACE(("%s: Enter\n", __func__));
 
6387
 
 
6388
        kfree(bus->ci);
 
6389
        bus->ci = NULL;
 
6390
}