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Viewing changes to sound/soc/omap/abe/abe_sm_addr.h

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
sound/soc/omap/abe/abe_sm_addr.h
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/*
2
 
 * ALSA SoC OMAP ABE driver
3
 
*
4
 
 * Author:          Laurent Le Faucheur <l-le-faucheur@ti.com>
5
 
 *
6
 
 * This program is free software; you can redistribute it and/or
7
 
 * modify it under the terms of the GNU General Public License
8
 
 * version 2 as published by the Free Software Foundation.
9
 
 *
10
 
 * This program is distributed in the hope that it will be useful, but
11
 
 * WITHOUT ANY WARRANTY; without even the implied warranty of
12
 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
 
 * General Public License for more details.
14
 
 *
15
 
 * You should have received a copy of the GNU General Public License
16
 
 * along with this program; if not, write to the Free Software
17
 
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18
 
 * 02110-1301 USA
19
 
 *
20
 
 */
21
 
#ifndef _ABE_SM_ADDR_H_
22
 
#define _ABE_SM_ADDR_H_
23
 
#define init_SM_ADDR                                        0
24
 
#define init_SM_ADDR_END                                    309
25
 
#define init_SM_sizeof                                      310
26
 
#define S_Data0_ADDR                                        310
27
 
#define S_Data0_ADDR_END                                    310
28
 
#define S_Data0_sizeof                                      1
29
 
#define S_Temp_ADDR                                         311
30
 
#define S_Temp_ADDR_END                                     311
31
 
#define S_Temp_sizeof                                       1
32
 
#define S_PhoenixOffset_ADDR                                312
33
 
#define S_PhoenixOffset_ADDR_END                            312
34
 
#define S_PhoenixOffset_sizeof                              1
35
 
#define S_GTarget1_ADDR                                     313
36
 
#define S_GTarget1_ADDR_END                                 319
37
 
#define S_GTarget1_sizeof                                   7
38
 
#define S_Gtarget_DL1_ADDR                                  320
39
 
#define S_Gtarget_DL1_ADDR_END                              321
40
 
#define S_Gtarget_DL1_sizeof                                2
41
 
#define S_Gtarget_DL2_ADDR                                  322
42
 
#define S_Gtarget_DL2_ADDR_END                              323
43
 
#define S_Gtarget_DL2_sizeof                                2
44
 
#define S_Gtarget_Echo_ADDR                                 324
45
 
#define S_Gtarget_Echo_ADDR_END                             324
46
 
#define S_Gtarget_Echo_sizeof                               1
47
 
#define S_Gtarget_SDT_ADDR                                  325
48
 
#define S_Gtarget_SDT_ADDR_END                              325
49
 
#define S_Gtarget_SDT_sizeof                                1
50
 
#define S_Gtarget_VxRec_ADDR                                326
51
 
#define S_Gtarget_VxRec_ADDR_END                            327
52
 
#define S_Gtarget_VxRec_sizeof                              2
53
 
#define S_Gtarget_UL_ADDR                                   328
54
 
#define S_Gtarget_UL_ADDR_END                               329
55
 
#define S_Gtarget_UL_sizeof                                 2
56
 
#define S_Gtarget_unused_ADDR                               330
57
 
#define S_Gtarget_unused_ADDR_END                           330
58
 
#define S_Gtarget_unused_sizeof                             1
59
 
#define S_GCurrent_ADDR                                     331
60
 
#define S_GCurrent_ADDR_END                                 348
61
 
#define S_GCurrent_sizeof                                   18
62
 
#define S_GAIN_ONE_ADDR                                     349
63
 
#define S_GAIN_ONE_ADDR_END                                 349
64
 
#define S_GAIN_ONE_sizeof                                   1
65
 
#define S_Tones_ADDR                                        350
66
 
#define S_Tones_ADDR_END                                    361
67
 
#define S_Tones_sizeof                                      12
68
 
#define S_VX_DL_ADDR                                        362
69
 
#define S_VX_DL_ADDR_END                                    373
70
 
#define S_VX_DL_sizeof                                      12
71
 
#define S_MM_UL2_ADDR                                       374
72
 
#define S_MM_UL2_ADDR_END                                   385
73
 
#define S_MM_UL2_sizeof                                     12
74
 
#define S_MM_DL_ADDR                                        386
75
 
#define S_MM_DL_ADDR_END                                    397
76
 
#define S_MM_DL_sizeof                                      12
77
 
#define S_DL1_M_Out_ADDR                                    398
78
 
#define S_DL1_M_Out_ADDR_END                                409
79
 
#define S_DL1_M_Out_sizeof                                  12
80
 
#define S_DL2_M_Out_ADDR                                    410
81
 
#define S_DL2_M_Out_ADDR_END                                421
82
 
#define S_DL2_M_Out_sizeof                                  12
83
 
#define S_Echo_M_Out_ADDR                                   422
84
 
#define S_Echo_M_Out_ADDR_END                               433
85
 
#define S_Echo_M_Out_sizeof                                 12
86
 
#define S_SDT_M_Out_ADDR                                    434
87
 
#define S_SDT_M_Out_ADDR_END                                445
88
 
#define S_SDT_M_Out_sizeof                                  12
89
 
#define S_VX_UL_ADDR                                        446
90
 
#define S_VX_UL_ADDR_END                                    457
91
 
#define S_VX_UL_sizeof                                      12
92
 
#define S_VX_UL_M_ADDR                                      458
93
 
#define S_VX_UL_M_ADDR_END                                  469
94
 
#define S_VX_UL_M_sizeof                                    12
95
 
#define S_BT_DL_ADDR                                        470
96
 
#define S_BT_DL_ADDR_END                                    481
97
 
#define S_BT_DL_sizeof                                      12
98
 
#define S_BT_UL_ADDR                                        482
99
 
#define S_BT_UL_ADDR_END                                    493
100
 
#define S_BT_UL_sizeof                                      12
101
 
#define S_BT_DL_8k_ADDR                                     494
102
 
#define S_BT_DL_8k_ADDR_END                                 496
103
 
#define S_BT_DL_8k_sizeof                                   3
104
 
#define S_BT_DL_16k_ADDR                                    497
105
 
#define S_BT_DL_16k_ADDR_END                                501
106
 
#define S_BT_DL_16k_sizeof                                  5
107
 
#define S_BT_UL_8k_ADDR                                     502
108
 
#define S_BT_UL_8k_ADDR_END                                 503
109
 
#define S_BT_UL_8k_sizeof                                   2
110
 
#define S_BT_UL_16k_ADDR                                    504
111
 
#define S_BT_UL_16k_ADDR_END                                507
112
 
#define S_BT_UL_16k_sizeof                                  4
113
 
#define S_SDT_F_ADDR                                        508
114
 
#define S_SDT_F_ADDR_END                                    519
115
 
#define S_SDT_F_sizeof                                      12
116
 
#define S_SDT_F_data_ADDR                                   520
117
 
#define S_SDT_F_data_ADDR_END                               528
118
 
#define S_SDT_F_data_sizeof                                 9
119
 
#define S_MM_DL_OSR_ADDR                                    529
120
 
#define S_MM_DL_OSR_ADDR_END                                552
121
 
#define S_MM_DL_OSR_sizeof                                  24
122
 
#define S_24_zeros_ADDR                                     553
123
 
#define S_24_zeros_ADDR_END                                 576
124
 
#define S_24_zeros_sizeof                                   24
125
 
#define S_DMIC1_ADDR                                        577
126
 
#define S_DMIC1_ADDR_END                                    588
127
 
#define S_DMIC1_sizeof                                      12
128
 
#define S_DMIC2_ADDR                                        589
129
 
#define S_DMIC2_ADDR_END                                    600
130
 
#define S_DMIC2_sizeof                                      12
131
 
#define S_DMIC3_ADDR                                        601
132
 
#define S_DMIC3_ADDR_END                                    612
133
 
#define S_DMIC3_sizeof                                      12
134
 
#define S_AMIC_ADDR                                         613
135
 
#define S_AMIC_ADDR_END                                     624
136
 
#define S_AMIC_sizeof                                       12
137
 
#define S_DMIC1_L_ADDR                                      625
138
 
#define S_DMIC1_L_ADDR_END                                  636
139
 
#define S_DMIC1_L_sizeof                                    12
140
 
#define S_DMIC1_R_ADDR                                      637
141
 
#define S_DMIC1_R_ADDR_END                                  648
142
 
#define S_DMIC1_R_sizeof                                    12
143
 
#define S_DMIC2_L_ADDR                                      649
144
 
#define S_DMIC2_L_ADDR_END                                  660
145
 
#define S_DMIC2_L_sizeof                                    12
146
 
#define S_DMIC2_R_ADDR                                      661
147
 
#define S_DMIC2_R_ADDR_END                                  672
148
 
#define S_DMIC2_R_sizeof                                    12
149
 
#define S_DMIC3_L_ADDR                                      673
150
 
#define S_DMIC3_L_ADDR_END                                  684
151
 
#define S_DMIC3_L_sizeof                                    12
152
 
#define S_DMIC3_R_ADDR                                      685
153
 
#define S_DMIC3_R_ADDR_END                                  696
154
 
#define S_DMIC3_R_sizeof                                    12
155
 
#define S_BT_UL_L_ADDR                                      697
156
 
#define S_BT_UL_L_ADDR_END                                  708
157
 
#define S_BT_UL_L_sizeof                                    12
158
 
#define S_BT_UL_R_ADDR                                      709
159
 
#define S_BT_UL_R_ADDR_END                                  720
160
 
#define S_BT_UL_R_sizeof                                    12
161
 
#define S_AMIC_L_ADDR                                       721
162
 
#define S_AMIC_L_ADDR_END                                   732
163
 
#define S_AMIC_L_sizeof                                     12
164
 
#define S_AMIC_R_ADDR                                       733
165
 
#define S_AMIC_R_ADDR_END                                   744
166
 
#define S_AMIC_R_sizeof                                     12
167
 
#define S_EchoRef_L_ADDR                                    745
168
 
#define S_EchoRef_L_ADDR_END                                756
169
 
#define S_EchoRef_L_sizeof                                  12
170
 
#define S_EchoRef_R_ADDR                                    757
171
 
#define S_EchoRef_R_ADDR_END                                768
172
 
#define S_EchoRef_R_sizeof                                  12
173
 
#define S_MM_DL_L_ADDR                                      769
174
 
#define S_MM_DL_L_ADDR_END                                  780
175
 
#define S_MM_DL_L_sizeof                                    12
176
 
#define S_MM_DL_R_ADDR                                      781
177
 
#define S_MM_DL_R_ADDR_END                                  792
178
 
#define S_MM_DL_R_sizeof                                    12
179
 
#define S_MM_UL_ADDR                                        793
180
 
#define S_MM_UL_ADDR_END                                    912
181
 
#define S_MM_UL_sizeof                                      120
182
 
#define S_AMIC_96k_ADDR                                     913
183
 
#define S_AMIC_96k_ADDR_END                                 936
184
 
#define S_AMIC_96k_sizeof                                   24
185
 
#define S_DMIC0_96k_ADDR                                    937
186
 
#define S_DMIC0_96k_ADDR_END                                960
187
 
#define S_DMIC0_96k_sizeof                                  24
188
 
#define S_DMIC1_96k_ADDR                                    961
189
 
#define S_DMIC1_96k_ADDR_END                                984
190
 
#define S_DMIC1_96k_sizeof                                  24
191
 
#define S_DMIC2_96k_ADDR                                    985
192
 
#define S_DMIC2_96k_ADDR_END                                1008
193
 
#define S_DMIC2_96k_sizeof                                  24
194
 
#define S_UL_VX_UL_48_8K_ADDR                               1009
195
 
#define S_UL_VX_UL_48_8K_ADDR_END                           1020
196
 
#define S_UL_VX_UL_48_8K_sizeof                             12
197
 
#define S_UL_VX_UL_48_16K_ADDR                              1021
198
 
#define S_UL_VX_UL_48_16K_ADDR_END                          1032
199
 
#define S_UL_VX_UL_48_16K_sizeof                            12
200
 
#define S_UL_MIC_48K_ADDR                                   1033
201
 
#define S_UL_MIC_48K_ADDR_END                               1044
202
 
#define S_UL_MIC_48K_sizeof                                 12
203
 
#define S_Voice_8k_UL_ADDR                                  1045
204
 
#define S_Voice_8k_UL_ADDR_END                              1047
205
 
#define S_Voice_8k_UL_sizeof                                3
206
 
#define S_Voice_8k_DL_ADDR                                  1048
207
 
#define S_Voice_8k_DL_ADDR_END                              1049
208
 
#define S_Voice_8k_DL_sizeof                                2
209
 
#define S_McPDM_Out1_ADDR                                   1050
210
 
#define S_McPDM_Out1_ADDR_END                               1073
211
 
#define S_McPDM_Out1_sizeof                                 24
212
 
#define S_McPDM_Out2_ADDR                                   1074
213
 
#define S_McPDM_Out2_ADDR_END                               1097
214
 
#define S_McPDM_Out2_sizeof                                 24
215
 
#define S_McPDM_Out3_ADDR                                   1098
216
 
#define S_McPDM_Out3_ADDR_END                               1121
217
 
#define S_McPDM_Out3_sizeof                                 24
218
 
#define S_Voice_16k_UL_ADDR                                 1122
219
 
#define S_Voice_16k_UL_ADDR_END                             1126
220
 
#define S_Voice_16k_UL_sizeof                               5
221
 
#define S_Voice_16k_DL_ADDR                                 1127
222
 
#define S_Voice_16k_DL_ADDR_END                             1130
223
 
#define S_Voice_16k_DL_sizeof                               4
224
 
#define S_XinASRC_DL_VX_ADDR                                1131
225
 
#define S_XinASRC_DL_VX_ADDR_END                            1170
226
 
#define S_XinASRC_DL_VX_sizeof                              40
227
 
#define S_XinASRC_UL_VX_ADDR                                1171
228
 
#define S_XinASRC_UL_VX_ADDR_END                            1210
229
 
#define S_XinASRC_UL_VX_sizeof                              40
230
 
#define S_XinASRC_MM_EXT_IN_ADDR                            1211
231
 
#define S_XinASRC_MM_EXT_IN_ADDR_END                        1250
232
 
#define S_XinASRC_MM_EXT_IN_sizeof                          40
233
 
#define S_VX_REC_ADDR                                       1251
234
 
#define S_VX_REC_ADDR_END                                   1262
235
 
#define S_VX_REC_sizeof                                     12
236
 
#define S_VX_REC_L_ADDR                                     1263
237
 
#define S_VX_REC_L_ADDR_END                                 1274
238
 
#define S_VX_REC_L_sizeof                                   12
239
 
#define S_VX_REC_R_ADDR                                     1275
240
 
#define S_VX_REC_R_ADDR_END                                 1286
241
 
#define S_VX_REC_R_sizeof                                   12
242
 
#define S_DL2_M_L_ADDR                                      1287
243
 
#define S_DL2_M_L_ADDR_END                                  1298
244
 
#define S_DL2_M_L_sizeof                                    12
245
 
#define S_DL2_M_R_ADDR                                      1299
246
 
#define S_DL2_M_R_ADDR_END                                  1310
247
 
#define S_DL2_M_R_sizeof                                    12
248
 
#define S_DL2_M_LR_EQ_data_ADDR                             1311
249
 
#define S_DL2_M_LR_EQ_data_ADDR_END                         1335
250
 
#define S_DL2_M_LR_EQ_data_sizeof                           25
251
 
#define S_DL1_M_EQ_data_ADDR                                1336
252
 
#define S_DL1_M_EQ_data_ADDR_END                            1360
253
 
#define S_DL1_M_EQ_data_sizeof                              25
254
 
#define S_EARP_48_96_LP_data_ADDR                           1361
255
 
#define S_EARP_48_96_LP_data_ADDR_END                       1375
256
 
#define S_EARP_48_96_LP_data_sizeof                         15
257
 
#define S_IHF_48_96_LP_data_ADDR                            1376
258
 
#define S_IHF_48_96_LP_data_ADDR_END                        1390
259
 
#define S_IHF_48_96_LP_data_sizeof                          15
260
 
#define S_VX_UL_8_TEMP_ADDR                                 1391
261
 
#define S_VX_UL_8_TEMP_ADDR_END                             1392
262
 
#define S_VX_UL_8_TEMP_sizeof                               2
263
 
#define S_VX_UL_16_TEMP_ADDR                                1393
264
 
#define S_VX_UL_16_TEMP_ADDR_END                            1396
265
 
#define S_VX_UL_16_TEMP_sizeof                              4
266
 
#define S_VX_DL_8_48_LP_data_ADDR                           1397
267
 
#define S_VX_DL_8_48_LP_data_ADDR_END                       1407
268
 
#define S_VX_DL_8_48_LP_data_sizeof                         11
269
 
#define S_VX_DL_8_48_HP_data_ADDR                           1408
270
 
#define S_VX_DL_8_48_HP_data_ADDR_END                       1414
271
 
#define S_VX_DL_8_48_HP_data_sizeof                         7
272
 
#define S_VX_DL_16_48_LP_data_ADDR                          1415
273
 
#define S_VX_DL_16_48_LP_data_ADDR_END                      1425
274
 
#define S_VX_DL_16_48_LP_data_sizeof                        11
275
 
#define S_VX_DL_16_48_HP_data_ADDR                          1426
276
 
#define S_VX_DL_16_48_HP_data_ADDR_END                      1430
277
 
#define S_VX_DL_16_48_HP_data_sizeof                        5
278
 
#define S_VX_UL_48_8_LP_data_ADDR                           1431
279
 
#define S_VX_UL_48_8_LP_data_ADDR_END                       1441
280
 
#define S_VX_UL_48_8_LP_data_sizeof                         11
281
 
#define S_VX_UL_48_8_HP_data_ADDR                           1442
282
 
#define S_VX_UL_48_8_HP_data_ADDR_END                       1448
283
 
#define S_VX_UL_48_8_HP_data_sizeof                         7
284
 
#define S_VX_UL_48_16_LP_data_ADDR                          1449
285
 
#define S_VX_UL_48_16_LP_data_ADDR_END                      1459
286
 
#define S_VX_UL_48_16_LP_data_sizeof                        11
287
 
#define S_VX_UL_48_16_HP_data_ADDR                          1460
288
 
#define S_VX_UL_48_16_HP_data_ADDR_END                      1466
289
 
#define S_VX_UL_48_16_HP_data_sizeof                        7
290
 
#define S_BT_UL_8_48_LP_data_ADDR                           1467
291
 
#define S_BT_UL_8_48_LP_data_ADDR_END                       1477
292
 
#define S_BT_UL_8_48_LP_data_sizeof                         11
293
 
#define S_BT_UL_8_48_HP_data_ADDR                           1478
294
 
#define S_BT_UL_8_48_HP_data_ADDR_END                       1484
295
 
#define S_BT_UL_8_48_HP_data_sizeof                         7
296
 
#define S_BT_UL_16_48_LP_data_ADDR                          1485
297
 
#define S_BT_UL_16_48_LP_data_ADDR_END                      1495
298
 
#define S_BT_UL_16_48_LP_data_sizeof                        11
299
 
#define S_BT_UL_16_48_HP_data_ADDR                          1496
300
 
#define S_BT_UL_16_48_HP_data_ADDR_END                      1500
301
 
#define S_BT_UL_16_48_HP_data_sizeof                        5
302
 
#define S_BT_DL_48_8_LP_data_ADDR                           1501
303
 
#define S_BT_DL_48_8_LP_data_ADDR_END                       1511
304
 
#define S_BT_DL_48_8_LP_data_sizeof                         11
305
 
#define S_BT_DL_48_8_HP_data_ADDR                           1512
306
 
#define S_BT_DL_48_8_HP_data_ADDR_END                       1518
307
 
#define S_BT_DL_48_8_HP_data_sizeof                         7
308
 
#define S_BT_DL_48_16_LP_data_ADDR                          1519
309
 
#define S_BT_DL_48_16_LP_data_ADDR_END                      1529
310
 
#define S_BT_DL_48_16_LP_data_sizeof                        11
311
 
#define S_BT_DL_48_16_HP_data_ADDR                          1530
312
 
#define S_BT_DL_48_16_HP_data_ADDR_END                      1534
313
 
#define S_BT_DL_48_16_HP_data_sizeof                        5
314
 
#define S_ECHO_REF_48_8_LP_data_ADDR                        1535
315
 
#define S_ECHO_REF_48_8_LP_data_ADDR_END                    1545
316
 
#define S_ECHO_REF_48_8_LP_data_sizeof                      11
317
 
#define S_ECHO_REF_48_8_HP_data_ADDR                        1546
318
 
#define S_ECHO_REF_48_8_HP_data_ADDR_END                    1552
319
 
#define S_ECHO_REF_48_8_HP_data_sizeof                      7
320
 
#define S_ECHO_REF_48_16_LP_data_ADDR                       1553
321
 
#define S_ECHO_REF_48_16_LP_data_ADDR_END                   1563
322
 
#define S_ECHO_REF_48_16_LP_data_sizeof                     11
323
 
#define S_ECHO_REF_48_16_HP_data_ADDR                       1564
324
 
#define S_ECHO_REF_48_16_HP_data_ADDR_END                   1568
325
 
#define S_ECHO_REF_48_16_HP_data_sizeof                     5
326
 
#define S_APS_IIRmem1_ADDR                                  1569
327
 
#define S_APS_IIRmem1_ADDR_END                              1577
328
 
#define S_APS_IIRmem1_sizeof                                9
329
 
#define S_APS_M_IIRmem2_ADDR                                1578
330
 
#define S_APS_M_IIRmem2_ADDR_END                            1580
331
 
#define S_APS_M_IIRmem2_sizeof                              3
332
 
#define S_APS_C_IIRmem2_ADDR                                1581
333
 
#define S_APS_C_IIRmem2_ADDR_END                            1583
334
 
#define S_APS_C_IIRmem2_sizeof                              3
335
 
#define S_APS_DL1_OutSamples_ADDR                           1584
336
 
#define S_APS_DL1_OutSamples_ADDR_END                       1585
337
 
#define S_APS_DL1_OutSamples_sizeof                         2
338
 
#define S_APS_DL1_COIL_OutSamples_ADDR                      1586
339
 
#define S_APS_DL1_COIL_OutSamples_ADDR_END                  1587
340
 
#define S_APS_DL1_COIL_OutSamples_sizeof                    2
341
 
#define S_APS_DL2_L_OutSamples_ADDR                         1588
342
 
#define S_APS_DL2_L_OutSamples_ADDR_END                     1589
343
 
#define S_APS_DL2_L_OutSamples_sizeof                       2
344
 
#define S_APS_DL2_L_COIL_OutSamples_ADDR                    1590
345
 
#define S_APS_DL2_L_COIL_OutSamples_ADDR_END                1591
346
 
#define S_APS_DL2_L_COIL_OutSamples_sizeof                  2
347
 
#define S_APS_DL2_R_OutSamples_ADDR                         1592
348
 
#define S_APS_DL2_R_OutSamples_ADDR_END                     1593
349
 
#define S_APS_DL2_R_OutSamples_sizeof                       2
350
 
#define S_APS_DL2_R_COIL_OutSamples_ADDR                    1594
351
 
#define S_APS_DL2_R_COIL_OutSamples_ADDR_END                1595
352
 
#define S_APS_DL2_R_COIL_OutSamples_sizeof                  2
353
 
#define S_XinASRC_ECHO_REF_ADDR                             1596
354
 
#define S_XinASRC_ECHO_REF_ADDR_END                         1635
355
 
#define S_XinASRC_ECHO_REF_sizeof                           40
356
 
#define S_ECHO_REF_16K_ADDR                                 1636
357
 
#define S_ECHO_REF_16K_ADDR_END                             1640
358
 
#define S_ECHO_REF_16K_sizeof                               5
359
 
#define S_ECHO_REF_8K_ADDR                                  1641
360
 
#define S_ECHO_REF_8K_ADDR_END                              1643
361
 
#define S_ECHO_REF_8K_sizeof                                3
362
 
#define S_DL1_EQ_ADDR                                       1644
363
 
#define S_DL1_EQ_ADDR_END                                   1655
364
 
#define S_DL1_EQ_sizeof                                     12
365
 
#define S_DL2_EQ_ADDR                                       1656
366
 
#define S_DL2_EQ_ADDR_END                                   1667
367
 
#define S_DL2_EQ_sizeof                                     12
368
 
#define S_DL1_GAIN_out_ADDR                                 1668
369
 
#define S_DL1_GAIN_out_ADDR_END                             1679
370
 
#define S_DL1_GAIN_out_sizeof                               12
371
 
#define S_DL2_GAIN_out_ADDR                                 1680
372
 
#define S_DL2_GAIN_out_ADDR_END                             1691
373
 
#define S_DL2_GAIN_out_sizeof                               12
374
 
#define S_APS_DL2_L_IIRmem1_ADDR                            1692
375
 
#define S_APS_DL2_L_IIRmem1_ADDR_END                        1700
376
 
#define S_APS_DL2_L_IIRmem1_sizeof                          9
377
 
#define S_APS_DL2_R_IIRmem1_ADDR                            1701
378
 
#define S_APS_DL2_R_IIRmem1_ADDR_END                        1709
379
 
#define S_APS_DL2_R_IIRmem1_sizeof                          9
380
 
#define S_APS_DL2_L_M_IIRmem2_ADDR                          1710
381
 
#define S_APS_DL2_L_M_IIRmem2_ADDR_END                      1712
382
 
#define S_APS_DL2_L_M_IIRmem2_sizeof                        3
383
 
#define S_APS_DL2_R_M_IIRmem2_ADDR                          1713
384
 
#define S_APS_DL2_R_M_IIRmem2_ADDR_END                      1715
385
 
#define S_APS_DL2_R_M_IIRmem2_sizeof                        3
386
 
#define S_APS_DL2_L_C_IIRmem2_ADDR                          1716
387
 
#define S_APS_DL2_L_C_IIRmem2_ADDR_END                      1718
388
 
#define S_APS_DL2_L_C_IIRmem2_sizeof                        3
389
 
#define S_APS_DL2_R_C_IIRmem2_ADDR                          1719
390
 
#define S_APS_DL2_R_C_IIRmem2_ADDR_END                      1721
391
 
#define S_APS_DL2_R_C_IIRmem2_sizeof                        3
392
 
#define S_DL1_APS_ADDR                                      1722
393
 
#define S_DL1_APS_ADDR_END                                  1733
394
 
#define S_DL1_APS_sizeof                                    12
395
 
#define S_DL2_L_APS_ADDR                                    1734
396
 
#define S_DL2_L_APS_ADDR_END                                1745
397
 
#define S_DL2_L_APS_sizeof                                  12
398
 
#define S_DL2_R_APS_ADDR                                    1746
399
 
#define S_DL2_R_APS_ADDR_END                                1757
400
 
#define S_DL2_R_APS_sizeof                                  12
401
 
#define S_APS_DL1_EQ_data_ADDR                              1758
402
 
#define S_APS_DL1_EQ_data_ADDR_END                          1766
403
 
#define S_APS_DL1_EQ_data_sizeof                            9
404
 
#define S_APS_DL2_EQ_data_ADDR                              1767
405
 
#define S_APS_DL2_EQ_data_ADDR_END                          1775
406
 
#define S_APS_DL2_EQ_data_sizeof                            9
407
 
#define S_DC_DCvalue_ADDR                                   1776
408
 
#define S_DC_DCvalue_ADDR_END                               1776
409
 
#define S_DC_DCvalue_sizeof                                 1
410
 
#define S_VIBRA_ADDR                                        1777
411
 
#define S_VIBRA_ADDR_END                                    1782
412
 
#define S_VIBRA_sizeof                                      6
413
 
#define S_Vibra2_in_ADDR                                    1783
414
 
#define S_Vibra2_in_ADDR_END                                1788
415
 
#define S_Vibra2_in_sizeof                                  6
416
 
#define S_Vibra2_addr_ADDR                                  1789
417
 
#define S_Vibra2_addr_ADDR_END                              1789
418
 
#define S_Vibra2_addr_sizeof                                1
419
 
#define S_VibraCtrl_forRightSM_ADDR                         1790
420
 
#define S_VibraCtrl_forRightSM_ADDR_END                     1813
421
 
#define S_VibraCtrl_forRightSM_sizeof                       24
422
 
#define S_Rnoise_mem_ADDR                                   1814
423
 
#define S_Rnoise_mem_ADDR_END                               1814
424
 
#define S_Rnoise_mem_sizeof                                 1
425
 
#define S_Ctrl_ADDR                                         1815
426
 
#define S_Ctrl_ADDR_END                                     1832
427
 
#define S_Ctrl_sizeof                                       18
428
 
#define S_Vibra1_in_ADDR                                    1833
429
 
#define S_Vibra1_in_ADDR_END                                1838
430
 
#define S_Vibra1_in_sizeof                                  6
431
 
#define S_Vibra1_temp_ADDR                                  1839
432
 
#define S_Vibra1_temp_ADDR_END                              1862
433
 
#define S_Vibra1_temp_sizeof                                24
434
 
#define S_VibraCtrl_forLeftSM_ADDR                          1863
435
 
#define S_VibraCtrl_forLeftSM_ADDR_END                      1886
436
 
#define S_VibraCtrl_forLeftSM_sizeof                        24
437
 
#define S_Vibra1_mem_ADDR                                   1887
438
 
#define S_Vibra1_mem_ADDR_END                               1897
439
 
#define S_Vibra1_mem_sizeof                                 11
440
 
#define S_VibraCtrl_Stereo_ADDR                             1898
441
 
#define S_VibraCtrl_Stereo_ADDR_END                         1921
442
 
#define S_VibraCtrl_Stereo_sizeof                           24
443
 
#define S_AMIC_96_48_data_ADDR                              1922
444
 
#define S_AMIC_96_48_data_ADDR_END                          1940
445
 
#define S_AMIC_96_48_data_sizeof                            19
446
 
#define S_DMIC0_96_48_data_ADDR                             1941
447
 
#define S_DMIC0_96_48_data_ADDR_END                         1959
448
 
#define S_DMIC0_96_48_data_sizeof                           19
449
 
#define S_DMIC1_96_48_data_ADDR                             1960
450
 
#define S_DMIC1_96_48_data_ADDR_END                         1978
451
 
#define S_DMIC1_96_48_data_sizeof                           19
452
 
#define S_DMIC2_96_48_data_ADDR                             1979
453
 
#define S_DMIC2_96_48_data_ADDR_END                         1997
454
 
#define S_DMIC2_96_48_data_sizeof                           19
455
 
#define S_DBG_8K_PATTERN_ADDR                               1998
456
 
#define S_DBG_8K_PATTERN_ADDR_END                           1999
457
 
#define S_DBG_8K_PATTERN_sizeof                             2
458
 
#define S_DBG_16K_PATTERN_ADDR                              2000
459
 
#define S_DBG_16K_PATTERN_ADDR_END                          2003
460
 
#define S_DBG_16K_PATTERN_sizeof                            4
461
 
#define S_DBG_24K_PATTERN_ADDR                              2004
462
 
#define S_DBG_24K_PATTERN_ADDR_END                          2009
463
 
#define S_DBG_24K_PATTERN_sizeof                            6
464
 
#define S_DBG_48K_PATTERN_ADDR                              2010
465
 
#define S_DBG_48K_PATTERN_ADDR_END                          2021
466
 
#define S_DBG_48K_PATTERN_sizeof                            12
467
 
#define S_DBG_96K_PATTERN_ADDR                              2022
468
 
#define S_DBG_96K_PATTERN_ADDR_END                          2045
469
 
#define S_DBG_96K_PATTERN_sizeof                            24
470
 
#define S_MM_EXT_IN_ADDR                                    2046
471
 
#define S_MM_EXT_IN_ADDR_END                                2057
472
 
#define S_MM_EXT_IN_sizeof                                  12
473
 
#define S_MM_EXT_IN_L_ADDR                                  2058
474
 
#define S_MM_EXT_IN_L_ADDR_END                              2069
475
 
#define S_MM_EXT_IN_L_sizeof                                12
476
 
#define S_MM_EXT_IN_R_ADDR                                  2070
477
 
#define S_MM_EXT_IN_R_ADDR_END                              2081
478
 
#define S_MM_EXT_IN_R_sizeof                                12
479
 
#define S_MIC4_ADDR                                         2082
480
 
#define S_MIC4_ADDR_END                                     2093
481
 
#define S_MIC4_sizeof                                       12
482
 
#define S_MIC4_L_ADDR                                       2094
483
 
#define S_MIC4_L_ADDR_END                                   2105
484
 
#define S_MIC4_L_sizeof                                     12
485
 
#define S_MIC4_R_ADDR                                       2106
486
 
#define S_MIC4_R_ADDR_END                                   2117
487
 
#define S_MIC4_R_sizeof                                     12
488
 
#define S_HW_TEST_ADDR                                      2118
489
 
#define S_HW_TEST_ADDR_END                                  2118
490
 
#define S_HW_TEST_sizeof                                    1
491
 
#define S_XinASRC_BT_UL_ADDR                                2119
492
 
#define S_XinASRC_BT_UL_ADDR_END                            2158
493
 
#define S_XinASRC_BT_UL_sizeof                              40
494
 
#define S_XinASRC_BT_DL_ADDR                                2159
495
 
#define S_XinASRC_BT_DL_ADDR_END                            2198
496
 
#define S_XinASRC_BT_DL_sizeof                              40
497
 
#define S_BT_DL_8k_TEMP_ADDR                                2199
498
 
#define S_BT_DL_8k_TEMP_ADDR_END                            2200
499
 
#define S_BT_DL_8k_TEMP_sizeof                              2
500
 
#define S_BT_DL_16k_TEMP_ADDR                               2201
501
 
#define S_BT_DL_16k_TEMP_ADDR_END                           2204
502
 
#define S_BT_DL_16k_TEMP_sizeof                             4
503
 
#endif/* _ABESM_ADDR_H_ */
 
2
 
 
3
  This file is provided under a dual BSD/GPLv2 license.  When using or
 
4
  redistributing this file, you may do so under either license.
 
5
 
 
6
  GPL LICENSE SUMMARY
 
7
 
 
8
  Copyright(c) 2010-2011 Texas Instruments Incorporated,
 
9
  All rights reserved.
 
10
 
 
11
  This program is free software; you can redistribute it and/or modify
 
12
  it under the terms of version 2 of the GNU General Public License as
 
13
  published by the Free Software Foundation.
 
14
 
 
15
  This program is distributed in the hope that it will be useful, but
 
16
  WITHOUT ANY WARRANTY; without even the implied warranty of
 
17
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
18
  General Public License for more details.
 
19
 
 
20
  You should have received a copy of the GNU General Public License
 
21
  along with this program; if not, write to the Free Software
 
22
  Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 
23
  The full GNU General Public License is included in this distribution
 
24
  in the file called LICENSE.GPL.
 
25
 
 
26
  BSD LICENSE
 
27
 
 
28
  Copyright(c) 2010-2011 Texas Instruments Incorporated,
 
29
  All rights reserved.
 
30
 
 
31
  Redistribution and use in source and binary forms, with or without
 
32
  modification, are permitted provided that the following conditions
 
33
  are met:
 
34
 
 
35
    * Redistributions of source code must retain the above copyright
 
36
      notice, this list of conditions and the following disclaimer.
 
37
    * Redistributions in binary form must reproduce the above copyright
 
38
      notice, this list of conditions and the following disclaimer in
 
39
      the documentation and/or other materials provided with the
 
40
      distribution.
 
41
    * Neither the name of Texas Instruments Incorporated nor the names of
 
42
      its contributors may be used to endorse or promote products derived
 
43
      from this software without specific prior written permission.
 
44
 
 
45
  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 
46
  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 
47
  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 
48
  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 
49
  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 
50
  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 
51
  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 
52
  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 
53
  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
54
  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 
55
  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
56
 
 
57
*/
 
58
 
 
59
#define OMAP_ABE_INIT_SM_ADDR                         0x0
 
60
#define OMAP_ABE_INIT_SM_SIZE                         0x9B8
 
61
 
 
62
#define OMAP_ABE_S_DATA0_ADDR                         0x9B8
 
63
#define OMAP_ABE_S_DATA0_SIZE                         0x8
 
64
 
 
65
#define OMAP_ABE_S_TEMP_ADDR                          0x9C0
 
66
#define OMAP_ABE_S_TEMP_SIZE                          0x8
 
67
 
 
68
#define OMAP_ABE_S_PHOENIXOFFSET_ADDR                 0x9C8
 
69
#define OMAP_ABE_S_PHOENIXOFFSET_SIZE                 0x8
 
70
 
 
71
#define OMAP_ABE_S_GTARGET1_ADDR                      0x9D0
 
72
#define OMAP_ABE_S_GTARGET1_SIZE                      0x38
 
73
 
 
74
#define OMAP_ABE_S_GTARGET_DL1_ADDR                   0xA08
 
75
#define OMAP_ABE_S_GTARGET_DL1_SIZE                   0x10
 
76
 
 
77
#define OMAP_ABE_S_GTARGET_DL2_ADDR                   0xA18
 
78
#define OMAP_ABE_S_GTARGET_DL2_SIZE                   0x10
 
79
 
 
80
#define OMAP_ABE_S_GTARGET_ECHO_ADDR                  0xA28
 
81
#define OMAP_ABE_S_GTARGET_ECHO_SIZE                  0x8
 
82
 
 
83
#define OMAP_ABE_S_GTARGET_SDT_ADDR                   0xA30
 
84
#define OMAP_ABE_S_GTARGET_SDT_SIZE                   0x8
 
85
 
 
86
#define OMAP_ABE_S_GTARGET_VXREC_ADDR                 0xA38
 
87
#define OMAP_ABE_S_GTARGET_VXREC_SIZE                 0x10
 
88
 
 
89
#define OMAP_ABE_S_GTARGET_UL_ADDR                    0xA48
 
90
#define OMAP_ABE_S_GTARGET_UL_SIZE                    0x10
 
91
 
 
92
#define OMAP_ABE_S_GTARGET_BTUL_ADDR                  0xA58
 
93
#define OMAP_ABE_S_GTARGET_BTUL_SIZE                  0x8
 
94
 
 
95
#define OMAP_ABE_S_GCURRENT_ADDR                      0xA60
 
96
#define OMAP_ABE_S_GCURRENT_SIZE                      0x90
 
97
 
 
98
#define OMAP_ABE_S_GAIN_ONE_ADDR                      0xAF0
 
99
#define OMAP_ABE_S_GAIN_ONE_SIZE                      0x8
 
100
 
 
101
#define OMAP_ABE_S_TONES_ADDR                         0xAF8
 
102
#define OMAP_ABE_S_TONES_SIZE                         0x60
 
103
 
 
104
#define OMAP_ABE_S_VX_DL_ADDR                         0xB58
 
105
#define OMAP_ABE_S_VX_DL_SIZE                         0x60
 
106
 
 
107
#define OMAP_ABE_S_MM_UL2_ADDR                        0xBB8
 
108
#define OMAP_ABE_S_MM_UL2_SIZE                        0x60
 
109
 
 
110
#define OMAP_ABE_S_MM_DL_ADDR                         0xC18
 
111
#define OMAP_ABE_S_MM_DL_SIZE                         0x60
 
112
 
 
113
#define OMAP_ABE_S_DL1_M_OUT_ADDR                     0xC78
 
114
#define OMAP_ABE_S_DL1_M_OUT_SIZE                     0x60
 
115
 
 
116
#define OMAP_ABE_S_DL2_M_OUT_ADDR                     0xCD8
 
117
#define OMAP_ABE_S_DL2_M_OUT_SIZE                     0x60
 
118
 
 
119
#define OMAP_ABE_S_ECHO_M_OUT_ADDR                    0xD38
 
120
#define OMAP_ABE_S_ECHO_M_OUT_SIZE                    0x60
 
121
 
 
122
#define OMAP_ABE_S_SDT_M_OUT_ADDR                     0xD98
 
123
#define OMAP_ABE_S_SDT_M_OUT_SIZE                     0x60
 
124
 
 
125
#define OMAP_ABE_S_VX_UL_ADDR                         0xDF8
 
126
#define OMAP_ABE_S_VX_UL_SIZE                         0x60
 
127
 
 
128
#define OMAP_ABE_S_VX_UL_M_ADDR                       0xE58
 
129
#define OMAP_ABE_S_VX_UL_M_SIZE                       0x60
 
130
 
 
131
#define OMAP_ABE_S_BT_DL_ADDR                         0xEB8
 
132
#define OMAP_ABE_S_BT_DL_SIZE                         0x60
 
133
 
 
134
#define OMAP_ABE_S_BT_UL_ADDR                         0xF18
 
135
#define OMAP_ABE_S_BT_UL_SIZE                         0x60
 
136
 
 
137
#define OMAP_ABE_S_BT_DL_8K_ADDR                      0xF78
 
138
#define OMAP_ABE_S_BT_DL_8K_SIZE                      0x18
 
139
 
 
140
#define OMAP_ABE_S_BT_DL_16K_ADDR                     0xF90
 
141
#define OMAP_ABE_S_BT_DL_16K_SIZE                     0x28
 
142
 
 
143
#define OMAP_ABE_S_BT_UL_8K_ADDR                      0xFB8
 
144
#define OMAP_ABE_S_BT_UL_8K_SIZE                      0x10
 
145
 
 
146
#define OMAP_ABE_S_BT_UL_16K_ADDR                     0xFC8
 
147
#define OMAP_ABE_S_BT_UL_16K_SIZE                     0x20
 
148
 
 
149
#define OMAP_ABE_S_SDT_F_ADDR                         0xFE8
 
150
#define OMAP_ABE_S_SDT_F_SIZE                         0x60
 
151
 
 
152
#define OMAP_ABE_S_SDT_F_DATA_ADDR                    0x1048
 
153
#define OMAP_ABE_S_SDT_F_DATA_SIZE                    0x48
 
154
 
 
155
#define OMAP_ABE_S_MM_DL_OSR_ADDR                     0x1090
 
156
#define OMAP_ABE_S_MM_DL_OSR_SIZE                     0xC0
 
157
 
 
158
#define OMAP_ABE_S_24_ZEROS_ADDR                      0x1150
 
159
#define OMAP_ABE_S_24_ZEROS_SIZE                      0xC0
 
160
 
 
161
#define OMAP_ABE_S_DMIC1_ADDR                         0x1210
 
162
#define OMAP_ABE_S_DMIC1_SIZE                         0x60
 
163
 
 
164
#define OMAP_ABE_S_DMIC2_ADDR                         0x1270
 
165
#define OMAP_ABE_S_DMIC2_SIZE                         0x60
 
166
 
 
167
#define OMAP_ABE_S_DMIC3_ADDR                         0x12D0
 
168
#define OMAP_ABE_S_DMIC3_SIZE                         0x60
 
169
 
 
170
#define OMAP_ABE_S_AMIC_ADDR                          0x1330
 
171
#define OMAP_ABE_S_AMIC_SIZE                          0x60
 
172
 
 
173
#define OMAP_ABE_S_DMIC1_L_ADDR                       0x1390
 
174
#define OMAP_ABE_S_DMIC1_L_SIZE                       0x60
 
175
 
 
176
#define OMAP_ABE_S_DMIC1_R_ADDR                       0x13F0
 
177
#define OMAP_ABE_S_DMIC1_R_SIZE                       0x60
 
178
 
 
179
#define OMAP_ABE_S_DMIC2_L_ADDR                       0x1450
 
180
#define OMAP_ABE_S_DMIC2_L_SIZE                       0x60
 
181
 
 
182
#define OMAP_ABE_S_DMIC2_R_ADDR                       0x14B0
 
183
#define OMAP_ABE_S_DMIC2_R_SIZE                       0x60
 
184
 
 
185
#define OMAP_ABE_S_DMIC3_L_ADDR                       0x1510
 
186
#define OMAP_ABE_S_DMIC3_L_SIZE                       0x60
 
187
 
 
188
#define OMAP_ABE_S_DMIC3_R_ADDR                       0x1570
 
189
#define OMAP_ABE_S_DMIC3_R_SIZE                       0x60
 
190
 
 
191
#define OMAP_ABE_S_BT_UL_L_ADDR                       0x15D0
 
192
#define OMAP_ABE_S_BT_UL_L_SIZE                       0x60
 
193
 
 
194
#define OMAP_ABE_S_BT_UL_R_ADDR                       0x1630
 
195
#define OMAP_ABE_S_BT_UL_R_SIZE                       0x60
 
196
 
 
197
#define OMAP_ABE_S_AMIC_L_ADDR                        0x1690
 
198
#define OMAP_ABE_S_AMIC_L_SIZE                        0x60
 
199
 
 
200
#define OMAP_ABE_S_AMIC_R_ADDR                        0x16F0
 
201
#define OMAP_ABE_S_AMIC_R_SIZE                        0x60
 
202
 
 
203
#define OMAP_ABE_S_ECHOREF_L_ADDR                     0x1750
 
204
#define OMAP_ABE_S_ECHOREF_L_SIZE                     0x60
 
205
 
 
206
#define OMAP_ABE_S_ECHOREF_R_ADDR                     0x17B0
 
207
#define OMAP_ABE_S_ECHOREF_R_SIZE                     0x60
 
208
 
 
209
#define OMAP_ABE_S_MM_DL_L_ADDR                       0x1810
 
210
#define OMAP_ABE_S_MM_DL_L_SIZE                       0x60
 
211
 
 
212
#define OMAP_ABE_S_MM_DL_R_ADDR                       0x1870
 
213
#define OMAP_ABE_S_MM_DL_R_SIZE                       0x60
 
214
 
 
215
#define OMAP_ABE_S_MM_UL_ADDR                         0x18D0
 
216
#define OMAP_ABE_S_MM_UL_SIZE                         0x3C0
 
217
 
 
218
#define OMAP_ABE_S_AMIC_96K_ADDR                      0x1C90
 
219
#define OMAP_ABE_S_AMIC_96K_SIZE                      0xC0
 
220
 
 
221
#define OMAP_ABE_S_DMIC0_96K_ADDR                     0x1D50
 
222
#define OMAP_ABE_S_DMIC0_96K_SIZE                     0xC0
 
223
 
 
224
#define OMAP_ABE_S_DMIC1_96K_ADDR                     0x1E10
 
225
#define OMAP_ABE_S_DMIC1_96K_SIZE                     0xC0
 
226
 
 
227
#define OMAP_ABE_S_DMIC2_96K_ADDR                     0x1ED0
 
228
#define OMAP_ABE_S_DMIC2_96K_SIZE                     0xC0
 
229
 
 
230
#define OMAP_ABE_S_UL_VX_UL_48_8K_ADDR                0x1F90
 
231
#define OMAP_ABE_S_UL_VX_UL_48_8K_SIZE                0x60
 
232
 
 
233
#define OMAP_ABE_S_UL_VX_UL_48_16K_ADDR               0x1FF0
 
234
#define OMAP_ABE_S_UL_VX_UL_48_16K_SIZE               0x60
 
235
 
 
236
#define OMAP_ABE_S_UL_MIC_48K_ADDR                    0x2050
 
237
#define OMAP_ABE_S_UL_MIC_48K_SIZE                    0x60
 
238
 
 
239
#define OMAP_ABE_S_VOICE_8K_UL_ADDR                   0x20B0
 
240
#define OMAP_ABE_S_VOICE_8K_UL_SIZE                   0x18
 
241
 
 
242
#define OMAP_ABE_S_VOICE_8K_DL_ADDR                   0x20C8
 
243
#define OMAP_ABE_S_VOICE_8K_DL_SIZE                   0x10
 
244
 
 
245
#define OMAP_ABE_S_MCPDM_OUT1_ADDR                    0x20D8
 
246
#define OMAP_ABE_S_MCPDM_OUT1_SIZE                    0xC0
 
247
 
 
248
#define OMAP_ABE_S_MCPDM_OUT2_ADDR                    0x2198
 
249
#define OMAP_ABE_S_MCPDM_OUT2_SIZE                    0xC0
 
250
 
 
251
#define OMAP_ABE_S_MCPDM_OUT3_ADDR                    0x2258
 
252
#define OMAP_ABE_S_MCPDM_OUT3_SIZE                    0xC0
 
253
 
 
254
#define OMAP_ABE_S_VOICE_16K_UL_ADDR                  0x2318
 
255
#define OMAP_ABE_S_VOICE_16K_UL_SIZE                  0x28
 
256
 
 
257
#define OMAP_ABE_S_VOICE_16K_DL_ADDR                  0x2340
 
258
#define OMAP_ABE_S_VOICE_16K_DL_SIZE                  0x20
 
259
 
 
260
#define OMAP_ABE_S_XINASRC_DL_VX_ADDR                 0x2360
 
261
#define OMAP_ABE_S_XINASRC_DL_VX_SIZE                 0x140
 
262
 
 
263
#define OMAP_ABE_S_XINASRC_UL_VX_ADDR                 0x24A0
 
264
#define OMAP_ABE_S_XINASRC_UL_VX_SIZE                 0x140
 
265
 
 
266
#define OMAP_ABE_S_XINASRC_MM_EXT_IN_ADDR             0x25E0
 
267
#define OMAP_ABE_S_XINASRC_MM_EXT_IN_SIZE             0x140
 
268
 
 
269
#define OMAP_ABE_S_VX_REC_ADDR                        0x2720
 
270
#define OMAP_ABE_S_VX_REC_SIZE                        0x60
 
271
 
 
272
#define OMAP_ABE_S_VX_REC_L_ADDR                      0x2780
 
273
#define OMAP_ABE_S_VX_REC_L_SIZE                      0x60
 
274
 
 
275
#define OMAP_ABE_S_VX_REC_R_ADDR                      0x27E0
 
276
#define OMAP_ABE_S_VX_REC_R_SIZE                      0x60
 
277
 
 
278
#define OMAP_ABE_S_DL2_M_L_ADDR                       0x2840
 
279
#define OMAP_ABE_S_DL2_M_L_SIZE                       0x60
 
280
 
 
281
#define OMAP_ABE_S_DL2_M_R_ADDR                       0x28A0
 
282
#define OMAP_ABE_S_DL2_M_R_SIZE                       0x60
 
283
 
 
284
#define OMAP_ABE_S_DL2_M_LR_EQ_DATA_ADDR              0x2900
 
285
#define OMAP_ABE_S_DL2_M_LR_EQ_DATA_SIZE              0xC8
 
286
 
 
287
#define OMAP_ABE_S_DL1_M_EQ_DATA_ADDR                 0x29C8
 
288
#define OMAP_ABE_S_DL1_M_EQ_DATA_SIZE                 0xC8
 
289
 
 
290
#define OMAP_ABE_S_EARP_48_96_LP_DATA_ADDR            0x2A90
 
291
#define OMAP_ABE_S_EARP_48_96_LP_DATA_SIZE            0x78
 
292
 
 
293
#define OMAP_ABE_S_IHF_48_96_LP_DATA_ADDR             0x2B08
 
294
#define OMAP_ABE_S_IHF_48_96_LP_DATA_SIZE             0x78
 
295
 
 
296
#define OMAP_ABE_S_VX_UL_8_TEMP_ADDR                  0x2B80
 
297
#define OMAP_ABE_S_VX_UL_8_TEMP_SIZE                  0x10
 
298
 
 
299
#define OMAP_ABE_S_VX_UL_16_TEMP_ADDR                 0x2B90
 
300
#define OMAP_ABE_S_VX_UL_16_TEMP_SIZE                 0x20
 
301
 
 
302
#define OMAP_ABE_S_VX_DL_8_48_LP_DATA_ADDR            0x2BB0
 
303
#define OMAP_ABE_S_VX_DL_8_48_LP_DATA_SIZE            0x58
 
304
 
 
305
#define OMAP_ABE_S_VX_DL_8_48_HP_DATA_ADDR            0x2C08
 
306
#define OMAP_ABE_S_VX_DL_8_48_HP_DATA_SIZE            0x38
 
307
 
 
308
#define OMAP_ABE_S_VX_DL_16_48_LP_DATA_ADDR           0x2C40
 
309
#define OMAP_ABE_S_VX_DL_16_48_LP_DATA_SIZE           0x58
 
310
 
 
311
#define OMAP_ABE_S_VX_DL_16_48_HP_DATA_ADDR           0x2C98
 
312
#define OMAP_ABE_S_VX_DL_16_48_HP_DATA_SIZE           0x28
 
313
 
 
314
#define OMAP_ABE_S_VX_UL_48_8_LP_DATA_ADDR            0x2CC0
 
315
#define OMAP_ABE_S_VX_UL_48_8_LP_DATA_SIZE            0x58
 
316
 
 
317
#define OMAP_ABE_S_VX_UL_48_8_HP_DATA_ADDR            0x2D18
 
318
#define OMAP_ABE_S_VX_UL_48_8_HP_DATA_SIZE            0x38
 
319
 
 
320
#define OMAP_ABE_S_VX_UL_48_16_LP_DATA_ADDR           0x2D50
 
321
#define OMAP_ABE_S_VX_UL_48_16_LP_DATA_SIZE           0x58
 
322
 
 
323
#define OMAP_ABE_S_VX_UL_48_16_HP_DATA_ADDR           0x2DA8
 
324
#define OMAP_ABE_S_VX_UL_48_16_HP_DATA_SIZE           0x38
 
325
 
 
326
#define OMAP_ABE_S_BT_UL_8_48_LP_DATA_ADDR            0x2DE0
 
327
#define OMAP_ABE_S_BT_UL_8_48_LP_DATA_SIZE            0x58
 
328
 
 
329
#define OMAP_ABE_S_BT_UL_8_48_HP_DATA_ADDR            0x2E38
 
330
#define OMAP_ABE_S_BT_UL_8_48_HP_DATA_SIZE            0x38
 
331
 
 
332
#define OMAP_ABE_S_BT_UL_16_48_LP_DATA_ADDR           0x2E70
 
333
#define OMAP_ABE_S_BT_UL_16_48_LP_DATA_SIZE           0x58
 
334
 
 
335
#define OMAP_ABE_S_BT_UL_16_48_HP_DATA_ADDR           0x2EC8
 
336
#define OMAP_ABE_S_BT_UL_16_48_HP_DATA_SIZE           0x28
 
337
 
 
338
#define OMAP_ABE_S_BT_DL_48_8_LP_DATA_ADDR            0x2EF0
 
339
#define OMAP_ABE_S_BT_DL_48_8_LP_DATA_SIZE            0x58
 
340
 
 
341
#define OMAP_ABE_S_BT_DL_48_8_HP_DATA_ADDR            0x2F48
 
342
#define OMAP_ABE_S_BT_DL_48_8_HP_DATA_SIZE            0x38
 
343
 
 
344
#define OMAP_ABE_S_BT_DL_48_16_LP_DATA_ADDR           0x2F80
 
345
#define OMAP_ABE_S_BT_DL_48_16_LP_DATA_SIZE           0x58
 
346
 
 
347
#define OMAP_ABE_S_BT_DL_48_16_HP_DATA_ADDR           0x2FD8
 
348
#define OMAP_ABE_S_BT_DL_48_16_HP_DATA_SIZE           0x28
 
349
 
 
350
#define OMAP_ABE_S_ECHO_REF_48_8_LP_DATA_ADDR         0x3000
 
351
#define OMAP_ABE_S_ECHO_REF_48_8_LP_DATA_SIZE         0x58
 
352
 
 
353
#define OMAP_ABE_S_ECHO_REF_48_8_HP_DATA_ADDR         0x3058
 
354
#define OMAP_ABE_S_ECHO_REF_48_8_HP_DATA_SIZE         0x38
 
355
 
 
356
#define OMAP_ABE_S_ECHO_REF_48_16_LP_DATA_ADDR        0x3090
 
357
#define OMAP_ABE_S_ECHO_REF_48_16_LP_DATA_SIZE        0x58
 
358
 
 
359
#define OMAP_ABE_S_ECHO_REF_48_16_HP_DATA_ADDR        0x30E8
 
360
#define OMAP_ABE_S_ECHO_REF_48_16_HP_DATA_SIZE        0x28
 
361
 
 
362
#define OMAP_ABE_S_APS_IIRMEM1_ADDR                   0x3110
 
363
#define OMAP_ABE_S_APS_IIRMEM1_SIZE                   0x48
 
364
 
 
365
#define OMAP_ABE_S_APS_M_IIRMEM2_ADDR                 0x3158
 
366
#define OMAP_ABE_S_APS_M_IIRMEM2_SIZE                 0x18
 
367
 
 
368
#define OMAP_ABE_S_APS_C_IIRMEM2_ADDR                 0x3170
 
369
#define OMAP_ABE_S_APS_C_IIRMEM2_SIZE                 0x18
 
370
 
 
371
#define OMAP_ABE_S_APS_DL1_OUTSAMPLES_ADDR            0x3188
 
372
#define OMAP_ABE_S_APS_DL1_OUTSAMPLES_SIZE            0x10
 
373
 
 
374
#define OMAP_ABE_S_APS_DL1_COIL_OUTSAMPLES_ADDR       0x3198
 
375
#define OMAP_ABE_S_APS_DL1_COIL_OUTSAMPLES_SIZE       0x10
 
376
 
 
377
#define OMAP_ABE_S_APS_DL2_L_OUTSAMPLES_ADDR          0x31A8
 
378
#define OMAP_ABE_S_APS_DL2_L_OUTSAMPLES_SIZE          0x10
 
379
 
 
380
#define OMAP_ABE_S_APS_DL2_L_COIL_OUTSAMPLES_ADDR     0x31B8
 
381
#define OMAP_ABE_S_APS_DL2_L_COIL_OUTSAMPLES_SIZE     0x10
 
382
 
 
383
#define OMAP_ABE_S_APS_DL2_R_OUTSAMPLES_ADDR          0x31C8
 
384
#define OMAP_ABE_S_APS_DL2_R_OUTSAMPLES_SIZE          0x10
 
385
 
 
386
#define OMAP_ABE_S_APS_DL2_R_COIL_OUTSAMPLES_ADDR     0x31D8
 
387
#define OMAP_ABE_S_APS_DL2_R_COIL_OUTSAMPLES_SIZE     0x10
 
388
 
 
389
#define OMAP_ABE_S_XINASRC_ECHO_REF_ADDR              0x31E8
 
390
#define OMAP_ABE_S_XINASRC_ECHO_REF_SIZE              0x140
 
391
 
 
392
#define OMAP_ABE_S_ECHO_REF_16K_ADDR                  0x3328
 
393
#define OMAP_ABE_S_ECHO_REF_16K_SIZE                  0x28
 
394
 
 
395
#define OMAP_ABE_S_ECHO_REF_8K_ADDR                   0x3350
 
396
#define OMAP_ABE_S_ECHO_REF_8K_SIZE                   0x18
 
397
 
 
398
#define OMAP_ABE_S_DL1_EQ_ADDR                        0x3368
 
399
#define OMAP_ABE_S_DL1_EQ_SIZE                        0x60
 
400
 
 
401
#define OMAP_ABE_S_DL2_EQ_ADDR                        0x33C8
 
402
#define OMAP_ABE_S_DL2_EQ_SIZE                        0x60
 
403
 
 
404
#define OMAP_ABE_S_DL1_GAIN_OUT_ADDR                  0x3428
 
405
#define OMAP_ABE_S_DL1_GAIN_OUT_SIZE                  0x60
 
406
 
 
407
#define OMAP_ABE_S_DL2_GAIN_OUT_ADDR                  0x3488
 
408
#define OMAP_ABE_S_DL2_GAIN_OUT_SIZE                  0x60
 
409
 
 
410
#define OMAP_ABE_S_APS_DL2_L_IIRMEM1_ADDR             0x34E8
 
411
#define OMAP_ABE_S_APS_DL2_L_IIRMEM1_SIZE             0x48
 
412
 
 
413
#define OMAP_ABE_S_APS_DL2_R_IIRMEM1_ADDR             0x3530
 
414
#define OMAP_ABE_S_APS_DL2_R_IIRMEM1_SIZE             0x48
 
415
 
 
416
#define OMAP_ABE_S_APS_DL2_L_M_IIRMEM2_ADDR           0x3578
 
417
#define OMAP_ABE_S_APS_DL2_L_M_IIRMEM2_SIZE           0x18
 
418
 
 
419
#define OMAP_ABE_S_APS_DL2_R_M_IIRMEM2_ADDR           0x3590
 
420
#define OMAP_ABE_S_APS_DL2_R_M_IIRMEM2_SIZE           0x18
 
421
 
 
422
#define OMAP_ABE_S_APS_DL2_L_C_IIRMEM2_ADDR           0x35A8
 
423
#define OMAP_ABE_S_APS_DL2_L_C_IIRMEM2_SIZE           0x18
 
424
 
 
425
#define OMAP_ABE_S_APS_DL2_R_C_IIRMEM2_ADDR           0x35C0
 
426
#define OMAP_ABE_S_APS_DL2_R_C_IIRMEM2_SIZE           0x18
 
427
 
 
428
#define OMAP_ABE_S_DL1_APS_ADDR                       0x35D8
 
429
#define OMAP_ABE_S_DL1_APS_SIZE                       0x60
 
430
 
 
431
#define OMAP_ABE_S_DL2_L_APS_ADDR                     0x3638
 
432
#define OMAP_ABE_S_DL2_L_APS_SIZE                     0x60
 
433
 
 
434
#define OMAP_ABE_S_DL2_R_APS_ADDR                     0x3698
 
435
#define OMAP_ABE_S_DL2_R_APS_SIZE                     0x60
 
436
 
 
437
#define OMAP_ABE_S_APS_DL1_EQ_DATA_ADDR               0x36F8
 
438
#define OMAP_ABE_S_APS_DL1_EQ_DATA_SIZE               0x48
 
439
 
 
440
#define OMAP_ABE_S_APS_DL2_EQ_DATA_ADDR               0x3740
 
441
#define OMAP_ABE_S_APS_DL2_EQ_DATA_SIZE               0x48
 
442
 
 
443
#define OMAP_ABE_S_DC_DCVALUE_ADDR                    0x3788
 
444
#define OMAP_ABE_S_DC_DCVALUE_SIZE                    0x8
 
445
 
 
446
#define OMAP_ABE_S_VIBRA_ADDR                         0x3790
 
447
#define OMAP_ABE_S_VIBRA_SIZE                         0x30
 
448
 
 
449
#define OMAP_ABE_S_VIBRA2_IN_ADDR                     0x37C0
 
450
#define OMAP_ABE_S_VIBRA2_IN_SIZE                     0x30
 
451
 
 
452
#define OMAP_ABE_S_VIBRA2_ADDR_ADDR                   0x37F0
 
453
#define OMAP_ABE_S_VIBRA2_ADDR_SIZE                   0x8
 
454
 
 
455
#define OMAP_ABE_S_VIBRACTRL_FORRIGHTSM_ADDR          0x37F8
 
456
#define OMAP_ABE_S_VIBRACTRL_FORRIGHTSM_SIZE          0xC0
 
457
 
 
458
#define OMAP_ABE_S_RNOISE_MEM_ADDR                    0x38B8
 
459
#define OMAP_ABE_S_RNOISE_MEM_SIZE                    0x8
 
460
 
 
461
#define OMAP_ABE_S_CTRL_ADDR                          0x38C0
 
462
#define OMAP_ABE_S_CTRL_SIZE                          0x90
 
463
 
 
464
#define OMAP_ABE_S_VIBRA1_IN_ADDR                     0x3950
 
465
#define OMAP_ABE_S_VIBRA1_IN_SIZE                     0x30
 
466
 
 
467
#define OMAP_ABE_S_VIBRA1_TEMP_ADDR                   0x3980
 
468
#define OMAP_ABE_S_VIBRA1_TEMP_SIZE                   0xC0
 
469
 
 
470
#define OMAP_ABE_S_VIBRACTRL_FORLEFTSM_ADDR           0x3A40
 
471
#define OMAP_ABE_S_VIBRACTRL_FORLEFTSM_SIZE           0xC0
 
472
 
 
473
#define OMAP_ABE_S_VIBRA1_MEM_ADDR                    0x3B00
 
474
#define OMAP_ABE_S_VIBRA1_MEM_SIZE                    0x58
 
475
 
 
476
#define OMAP_ABE_S_VIBRACTRL_STEREO_ADDR              0x3B58
 
477
#define OMAP_ABE_S_VIBRACTRL_STEREO_SIZE              0xC0
 
478
 
 
479
#define OMAP_ABE_S_AMIC_96_48_DATA_ADDR               0x3C18
 
480
#define OMAP_ABE_S_AMIC_96_48_DATA_SIZE               0x98
 
481
 
 
482
#define OMAP_ABE_S_DMIC0_96_48_DATA_ADDR              0x3CB0
 
483
#define OMAP_ABE_S_DMIC0_96_48_DATA_SIZE              0x98
 
484
 
 
485
#define OMAP_ABE_S_DMIC1_96_48_DATA_ADDR              0x3D48
 
486
#define OMAP_ABE_S_DMIC1_96_48_DATA_SIZE              0x98
 
487
 
 
488
#define OMAP_ABE_S_DMIC2_96_48_DATA_ADDR              0x3DE0
 
489
#define OMAP_ABE_S_DMIC2_96_48_DATA_SIZE              0x98
 
490
 
 
491
#define OMAP_ABE_S_DBG_8K_PATTERN_ADDR                0x3E78
 
492
#define OMAP_ABE_S_DBG_8K_PATTERN_SIZE                0x10
 
493
 
 
494
#define OMAP_ABE_S_DBG_16K_PATTERN_ADDR               0x3E88
 
495
#define OMAP_ABE_S_DBG_16K_PATTERN_SIZE               0x20
 
496
 
 
497
#define OMAP_ABE_S_DBG_24K_PATTERN_ADDR               0x3EA8
 
498
#define OMAP_ABE_S_DBG_24K_PATTERN_SIZE               0x30
 
499
 
 
500
#define OMAP_ABE_S_DBG_48K_PATTERN_ADDR               0x3ED8
 
501
#define OMAP_ABE_S_DBG_48K_PATTERN_SIZE               0x60
 
502
 
 
503
#define OMAP_ABE_S_DBG_96K_PATTERN_ADDR               0x3F38
 
504
#define OMAP_ABE_S_DBG_96K_PATTERN_SIZE               0xC0
 
505
 
 
506
#define OMAP_ABE_S_MM_EXT_IN_ADDR                     0x3FF8
 
507
#define OMAP_ABE_S_MM_EXT_IN_SIZE                     0x60
 
508
 
 
509
#define OMAP_ABE_S_MM_EXT_IN_L_ADDR                   0x4058
 
510
#define OMAP_ABE_S_MM_EXT_IN_L_SIZE                   0x60
 
511
 
 
512
#define OMAP_ABE_S_MM_EXT_IN_R_ADDR                   0x40B8
 
513
#define OMAP_ABE_S_MM_EXT_IN_R_SIZE                   0x60
 
514
 
 
515
#define OMAP_ABE_S_MIC4_ADDR                          0x4118
 
516
#define OMAP_ABE_S_MIC4_SIZE                          0x60
 
517
 
 
518
#define OMAP_ABE_S_MIC4_L_ADDR                        0x4178
 
519
#define OMAP_ABE_S_MIC4_L_SIZE                        0x60
 
520
 
 
521
#define OMAP_ABE_S_MIC4_R_ADDR                        0x41D8
 
522
#define OMAP_ABE_S_MIC4_R_SIZE                        0x60
 
523
 
 
524
#define OMAP_ABE_S_HW_TEST_ADDR                       0x4238
 
525
#define OMAP_ABE_S_HW_TEST_SIZE                       0x8
 
526
 
 
527
#define OMAP_ABE_S_XINASRC_BT_UL_ADDR                 0x4240
 
528
#define OMAP_ABE_S_XINASRC_BT_UL_SIZE                 0x140
 
529
 
 
530
#define OMAP_ABE_S_XINASRC_BT_DL_ADDR                 0x4380
 
531
#define OMAP_ABE_S_XINASRC_BT_DL_SIZE                 0x140
 
532
 
 
533
#define OMAP_ABE_S_BT_DL_8K_TEMP_ADDR                 0x44C0
 
534
#define OMAP_ABE_S_BT_DL_8K_TEMP_SIZE                 0x10
 
535
 
 
536
#define OMAP_ABE_S_BT_DL_16K_TEMP_ADDR                0x44D0
 
537
#define OMAP_ABE_S_BT_DL_16K_TEMP_SIZE                0x20