2
* (C) 2001-2004 Dave Jones. <davej@redhat.com>
3
* (C) 2002 Padraig Brady. <padraig@antefacto.com>
5
* Licensed under the terms of the GNU GPL License version 2.
6
* Based upon datasheets & sample CPUs kindly provided by VIA.
8
* VIA have currently 3 different versions of Longhaul.
9
* Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10
* It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11
* Version 2 of longhaul is backward compatible with v1, but adds
12
* LONGHAUL MSR for purpose of both frequency and voltage scaling.
13
* Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14
* Version 3 of longhaul got renamed to Powersaver and redesigned
15
* to use only the POWERSAVER MSR at 0x110a.
16
* It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17
* It's pretty much the same feature wise to longhaul v2, though
18
* there is provision for scaling FSB too, but this doesn't work
19
* too well in practice so we don't even try to use this.
21
* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
24
#include <linux/kernel.h>
25
#include <linux/module.h>
26
#include <linux/moduleparam.h>
27
#include <linux/init.h>
28
#include <linux/cpufreq.h>
29
#include <linux/pci.h>
30
#include <linux/slab.h>
31
#include <linux/string.h>
32
#include <linux/delay.h>
33
#include <linux/timex.h>
35
#include <linux/acpi.h>
38
#include <acpi/processor.h>
42
#define PFX "longhaul: "
44
#define TYPE_LONGHAUL_V1 1
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#define TYPE_LONGHAUL_V2 2
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#define TYPE_POWERSAVER 3
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#define CPU_NEHEMIAH 5
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#define CPU_NEHEMIAH_C 6
56
#define USE_ACPI_C3 (1 << 1)
57
#define USE_NORTHBRIDGE (1 << 2)
60
static unsigned int numscales = 16;
61
static unsigned int fsb;
63
static const struct mV_pos *vrm_mV_table;
64
static const unsigned char *mV_vrm_table;
66
static unsigned int highest_speed, lowest_speed; /* kHz */
67
static unsigned int minmult, maxmult;
68
static int can_scale_voltage;
69
static struct acpi_processor *pr;
70
static struct acpi_processor_cx *cx;
71
static u32 acpi_regs_addr;
72
static u8 longhaul_flags;
73
static unsigned int longhaul_index;
75
/* Module parameters */
76
static int scale_voltage;
77
static int disable_acpi_c3;
78
static int revid_errata;
80
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
84
/* Clock ratios multiplied by 10 */
87
static int longhaul_version;
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static struct cpufreq_frequency_table *longhaul_table;
90
#ifdef CONFIG_CPU_FREQ_DEBUG
91
static char speedbuffer[8];
93
static char *print_speed(int speed)
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snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed);
101
snprintf(speedbuffer, sizeof(speedbuffer),
102
"%dGHz", speed/1000);
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snprintf(speedbuffer, sizeof(speedbuffer),
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"%d.%dGHz", speed/1000, (speed%1000)/100);
112
static unsigned int calc_speed(int mult)
123
static int longhaul_get_cpu_mult(void)
125
unsigned long invalue = 0, lo, hi;
127
rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
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invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
129
if (longhaul_version == TYPE_LONGHAUL_V2 ||
130
longhaul_version == TYPE_POWERSAVER) {
134
return eblcr[invalue];
137
/* For processor with BCR2 MSR */
139
static void do_longhaul1(unsigned int mults_index)
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rdmsrl(MSR_VIA_BCR2, bcr2.val);
144
/* Enable software clock multiplier */
145
bcr2.bits.ESOFTBF = 1;
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bcr2.bits.CLOCKMUL = mults_index & 0xff;
148
/* Sync to timer tick */
150
/* Change frequency on next halt or sleep */
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wrmsrl(MSR_VIA_BCR2, bcr2.val);
152
/* Invoke transition */
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ACPI_FLUSH_CPU_CACHE();
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/* Disable software clock multiplier */
158
rdmsrl(MSR_VIA_BCR2, bcr2.val);
159
bcr2.bits.ESOFTBF = 0;
160
wrmsrl(MSR_VIA_BCR2, bcr2.val);
163
/* For processor with Longhaul MSR */
165
static void do_powersaver(int cx_address, unsigned int mults_index,
168
union msr_longhaul longhaul;
171
rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
172
/* Setup new frequency */
174
longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
176
longhaul.bits.RevisionKey = 0;
177
longhaul.bits.SoftBusRatio = mults_index & 0xf;
178
longhaul.bits.SoftBusRatio4 = (mults_index & 0x10) >> 4;
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/* Setup new voltage */
180
if (can_scale_voltage)
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longhaul.bits.SoftVID = (mults_index >> 8) & 0x1f;
182
/* Sync to timer tick */
184
/* Raise voltage if necessary */
185
if (can_scale_voltage && dir) {
186
longhaul.bits.EnableSoftVID = 1;
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
190
ACPI_FLUSH_CPU_CACHE();
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ACPI_FLUSH_CPU_CACHE();
196
/* Dummy op - must do something useless after P_LVL3
198
t = inl(acpi_gbl_FADT.xpm_timer_block.address);
200
longhaul.bits.EnableSoftVID = 0;
201
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
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/* Change frequency on next halt or sleep */
205
longhaul.bits.EnableSoftBusRatio = 1;
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wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
208
ACPI_FLUSH_CPU_CACHE();
211
ACPI_FLUSH_CPU_CACHE();
214
/* Dummy op - must do something useless after P_LVL3 read */
215
t = inl(acpi_gbl_FADT.xpm_timer_block.address);
217
/* Disable bus ratio bit */
218
longhaul.bits.EnableSoftBusRatio = 0;
219
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
221
/* Reduce voltage if necessary */
222
if (can_scale_voltage && !dir) {
223
longhaul.bits.EnableSoftVID = 1;
224
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
227
ACPI_FLUSH_CPU_CACHE();
230
ACPI_FLUSH_CPU_CACHE();
233
/* Dummy op - must do something useless after P_LVL3
235
t = inl(acpi_gbl_FADT.xpm_timer_block.address);
237
longhaul.bits.EnableSoftVID = 0;
238
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
243
* longhaul_set_cpu_frequency()
244
* @mults_index : bitpattern of the new multiplier.
246
* Sets a new clock ratio.
249
static void longhaul_setstate(unsigned int table_index)
251
unsigned int mults_index;
253
struct cpufreq_freqs freqs;
255
unsigned int pic1_mask, pic2_mask;
257
u32 bm_timeout = 1000;
258
unsigned int dir = 0;
260
mults_index = longhaul_table[table_index].index;
261
/* Safety precautions */
262
mult = mults[mults_index & 0x1f];
265
speed = calc_speed(mult);
266
if ((speed > highest_speed) || (speed < lowest_speed))
268
/* Voltage transition before frequency transition? */
269
if (can_scale_voltage && longhaul_index < table_index)
272
freqs.old = calc_speed(longhaul_get_cpu_mult());
274
freqs.cpu = 0; /* longhaul.c is UP only driver */
276
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
278
dprintk("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
279
fsb, mult/10, mult%10, print_speed(speed/1000));
282
local_irq_save(flags);
284
pic2_mask = inb(0xA1);
285
pic1_mask = inb(0x21); /* works on C3. save mask. */
286
outb(0xFF, 0xA1); /* Overkill */
287
outb(0xFE, 0x21); /* TMR0 only */
289
/* Wait while PCI bus is busy. */
290
if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
291
|| ((pr != NULL) && pr->flags.bm_control))) {
292
bm_status = inw(acpi_regs_addr);
294
while (bm_status && bm_timeout) {
295
outw(1 << 4, acpi_regs_addr);
297
bm_status = inw(acpi_regs_addr);
302
if (longhaul_flags & USE_NORTHBRIDGE) {
303
/* Disable AGP and PCI arbiters */
305
} else if ((pr != NULL) && pr->flags.bm_control) {
306
/* Disable bus master arbitration */
307
acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
309
switch (longhaul_version) {
312
* Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
313
* Software controlled multipliers only.
315
case TYPE_LONGHAUL_V1:
316
do_longhaul1(mults_index);
320
* Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
322
* Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
323
* Nehemiah can do FSB scaling too, but this has never been proven
324
* to work in practice.
326
case TYPE_LONGHAUL_V2:
327
case TYPE_POWERSAVER:
328
if (longhaul_flags & USE_ACPI_C3) {
329
/* Don't allow wakeup */
330
acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
331
do_powersaver(cx->address, mults_index, dir);
333
do_powersaver(0, mults_index, dir);
338
if (longhaul_flags & USE_NORTHBRIDGE) {
339
/* Enable arbiters */
341
} else if ((pr != NULL) && pr->flags.bm_control) {
342
/* Enable bus master arbitration */
343
acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
345
outb(pic2_mask, 0xA1); /* restore mask */
346
outb(pic1_mask, 0x21);
348
local_irq_restore(flags);
351
freqs.new = calc_speed(longhaul_get_cpu_mult());
352
/* Check if requested frequency is set. */
353
if (unlikely(freqs.new != speed)) {
354
printk(KERN_INFO PFX "Failed to set requested frequency!\n");
355
/* Revision ID = 1 but processor is expecting revision key
356
* equal to 0. Jumpers at the bottom of processor will change
357
* multiplier and FSB, but will not change bits in Longhaul
358
* MSR nor enable voltage scaling. */
360
printk(KERN_INFO PFX "Enabling \"Ignore Revision ID\" "
366
/* Why ACPI C3 sometimes doesn't work is a mystery for me.
367
* But it does happen. Processor is entering ACPI C3 state,
368
* but it doesn't change frequency. I tried poking various
369
* bits in northbridge registers, but without success. */
370
if (longhaul_flags & USE_ACPI_C3) {
371
printk(KERN_INFO PFX "Disabling ACPI C3 support.\n");
372
longhaul_flags &= ~USE_ACPI_C3;
374
printk(KERN_INFO PFX "Disabling \"Ignore "
375
"Revision ID\" option.\n");
381
/* This shouldn't happen. Longhaul ver. 2 was reported not
382
* working on processors without voltage scaling, but with
383
* RevID = 1. RevID errata will make things right. Just
384
* to be 100% sure. */
385
if (longhaul_version == TYPE_LONGHAUL_V2) {
386
printk(KERN_INFO PFX "Switching to Longhaul ver. 1\n");
387
longhaul_version = TYPE_LONGHAUL_V1;
392
/* Report true CPU frequency */
393
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
396
printk(KERN_INFO PFX "Warning: Timeout while waiting for "
401
* Centaur decided to make life a little more tricky.
402
* Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
403
* Samuel2 and above have to try and guess what the FSB is.
404
* We do this by assuming we booted at maximum multiplier, and interpolate
405
* between that value multiplied by possible FSBs and cpu_mhz which
406
* was calculated at boot time. Really ugly, but no other way to do this.
411
static int guess_fsb(int mult)
413
int speed = cpu_khz / 1000;
415
int speeds[] = { 666, 1000, 1333, 2000 };
418
for (i = 0; i < 4; i++) {
419
f_max = ((speeds[i] * mult) + 50) / 100;
420
f_max += (ROUNDING / 2);
421
f_min = f_max - ROUNDING;
422
if ((speed <= f_max) && (speed >= f_min))
423
return speeds[i] / 10;
429
static int __cpuinit longhaul_get_ranges(void)
431
unsigned int i, j, k = 0;
435
/* Get current frequency */
436
mult = longhaul_get_cpu_mult();
438
printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
441
fsb = guess_fsb(mult);
443
printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
446
/* Get max multiplier - as we always did.
447
* Longhaul MSR is usefull only when voltage scaling is enabled.
448
* C3 is booting at max anyway. */
450
/* Get min multiplier */
463
dprintk("MinMult:%d.%dx MaxMult:%d.%dx\n",
464
minmult/10, minmult%10, maxmult/10, maxmult%10);
466
highest_speed = calc_speed(maxmult);
467
lowest_speed = calc_speed(minmult);
468
dprintk("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
469
print_speed(lowest_speed/1000),
470
print_speed(highest_speed/1000));
472
if (lowest_speed == highest_speed) {
473
printk(KERN_INFO PFX "highestspeed == lowest, aborting.\n");
476
if (lowest_speed > highest_speed) {
477
printk(KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
478
lowest_speed, highest_speed);
482
longhaul_table = kmalloc((numscales + 1) * sizeof(*longhaul_table),
487
for (j = 0; j < numscales; j++) {
491
if (ratio > maxmult || ratio < minmult)
493
longhaul_table[k].frequency = calc_speed(ratio);
494
longhaul_table[k].index = j;
498
kfree(longhaul_table);
502
for (j = 0; j < k - 1; j++) {
503
unsigned int min_f, min_i;
504
min_f = longhaul_table[j].frequency;
506
for (i = j + 1; i < k; i++) {
507
if (longhaul_table[i].frequency < min_f) {
508
min_f = longhaul_table[i].frequency;
513
swap(longhaul_table[j].frequency,
514
longhaul_table[min_i].frequency);
515
swap(longhaul_table[j].index,
516
longhaul_table[min_i].index);
520
longhaul_table[k].frequency = CPUFREQ_TABLE_END;
522
/* Find index we are running on */
523
for (j = 0; j < k; j++) {
524
if (mults[longhaul_table[j].index & 0x1f] == mult) {
533
static void __cpuinit longhaul_setup_voltagescaling(void)
535
union msr_longhaul longhaul;
536
struct mV_pos minvid, maxvid, vid;
537
unsigned int j, speed, pos, kHz_step, numvscales;
540
rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
541
if (!(longhaul.bits.RevisionID & 1)) {
542
printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
546
if (!longhaul.bits.VRMRev) {
547
printk(KERN_INFO PFX "VRM 8.5\n");
548
vrm_mV_table = &vrm85_mV[0];
549
mV_vrm_table = &mV_vrm85[0];
551
printk(KERN_INFO PFX "Mobile VRM\n");
552
if (cpu_model < CPU_NEHEMIAH)
554
vrm_mV_table = &mobilevrm_mV[0];
555
mV_vrm_table = &mV_mobilevrm[0];
558
minvid = vrm_mV_table[longhaul.bits.MinimumVID];
559
maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
561
if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
562
printk(KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
563
"Voltage scaling disabled.\n",
564
minvid.mV/1000, minvid.mV%1000,
565
maxvid.mV/1000, maxvid.mV%1000);
569
if (minvid.mV == maxvid.mV) {
570
printk(KERN_INFO PFX "Claims to support voltage scaling but "
571
"min & max are both %d.%03d. "
572
"Voltage scaling disabled\n",
573
maxvid.mV/1000, maxvid.mV%1000);
577
/* How many voltage steps*/
578
numvscales = maxvid.pos - minvid.pos + 1;
582
"%d possible voltage scales\n",
583
maxvid.mV/1000, maxvid.mV%1000,
584
minvid.mV/1000, minvid.mV%1000,
587
/* Calculate max frequency at min voltage */
588
j = longhaul.bits.MinMHzBR;
589
if (longhaul.bits.MinMHzBR4)
591
min_vid_speed = eblcr[j];
592
if (min_vid_speed == -1)
594
switch (longhaul.bits.MinMHzFSB) {
596
min_vid_speed *= 13333;
599
min_vid_speed *= 10000;
602
min_vid_speed *= 6666;
608
if (min_vid_speed >= highest_speed)
610
/* Calculate kHz for one voltage step */
611
kHz_step = (highest_speed - min_vid_speed) / numvscales;
614
while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
615
speed = longhaul_table[j].frequency;
616
if (speed > min_vid_speed)
617
pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
620
longhaul_table[j].index |= mV_vrm_table[pos] << 8;
621
vid = vrm_mV_table[mV_vrm_table[pos]];
622
printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n",
627
can_scale_voltage = 1;
628
printk(KERN_INFO PFX "Voltage scaling enabled.\n");
632
static int longhaul_verify(struct cpufreq_policy *policy)
634
return cpufreq_frequency_table_verify(policy, longhaul_table);
638
static int longhaul_target(struct cpufreq_policy *policy,
639
unsigned int target_freq, unsigned int relation)
641
unsigned int table_index = 0;
643
unsigned int dir = 0;
646
if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq,
647
relation, &table_index))
650
/* Don't set same frequency again */
651
if (longhaul_index == table_index)
654
if (!can_scale_voltage)
655
longhaul_setstate(table_index);
657
/* On test system voltage transitions exceeding single
658
* step up or down were turning motherboard off. Both
659
* "ondemand" and "userspace" are unsafe. C7 is doing
660
* this in hardware, C3 is old and we need to do this
663
current_vid = (longhaul_table[longhaul_index].index >> 8);
665
if (table_index > longhaul_index)
667
while (i != table_index) {
668
vid = (longhaul_table[i].index >> 8) & 0x1f;
669
if (vid != current_vid) {
670
longhaul_setstate(i);
679
longhaul_setstate(table_index);
681
longhaul_index = table_index;
686
static unsigned int longhaul_get(unsigned int cpu)
690
return calc_speed(longhaul_get_cpu_mult());
693
static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
695
void *context, void **return_value)
697
struct acpi_device *d;
699
if (acpi_bus_get_device(obj_handle, &d))
702
*return_value = acpi_driver_data(d);
706
/* VIA don't support PM2 reg, but have something similar */
707
static int enable_arbiter_disable(void)
714
/* Find PLE133 host bridge */
716
dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
718
/* Find PM133/VT8605 host bridge */
720
dev = pci_get_device(PCI_VENDOR_ID_VIA,
721
PCI_DEVICE_ID_VIA_8605_0, NULL);
722
/* Find CLE266 host bridge */
725
dev = pci_get_device(PCI_VENDOR_ID_VIA,
726
PCI_DEVICE_ID_VIA_862X_0, NULL);
727
/* Find CN400 V-Link host bridge */
729
dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
732
/* Enable access to port 0x22 */
733
pci_read_config_byte(dev, reg, &pci_cmd);
734
if (!(pci_cmd & 1<<7)) {
736
pci_write_config_byte(dev, reg, pci_cmd);
737
pci_read_config_byte(dev, reg, &pci_cmd);
738
if (!(pci_cmd & 1<<7)) {
740
"Can't enable access to port 0x22.\n");
750
static int longhaul_setup_southbridge(void)
755
/* Find VT8235 southbridge */
756
dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
758
/* Find VT8237 southbridge */
759
dev = pci_get_device(PCI_VENDOR_ID_VIA,
760
PCI_DEVICE_ID_VIA_8237, NULL);
762
/* Set transition time to max */
763
pci_read_config_byte(dev, 0xec, &pci_cmd);
764
pci_cmd &= ~(1 << 2);
765
pci_write_config_byte(dev, 0xec, pci_cmd);
766
pci_read_config_byte(dev, 0xe4, &pci_cmd);
767
pci_cmd &= ~(1 << 7);
768
pci_write_config_byte(dev, 0xe4, pci_cmd);
769
pci_read_config_byte(dev, 0xe5, &pci_cmd);
771
pci_write_config_byte(dev, 0xe5, pci_cmd);
772
/* Get address of ACPI registers block*/
773
pci_read_config_byte(dev, 0x81, &pci_cmd);
774
if (pci_cmd & 1 << 7) {
775
pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
776
acpi_regs_addr &= 0xff00;
777
printk(KERN_INFO PFX "ACPI I/O at 0x%x\n",
787
static int __cpuinit longhaul_cpu_init(struct cpufreq_policy *policy)
789
struct cpuinfo_x86 *c = &cpu_data(0);
790
char *cpuname = NULL;
794
/* Check what we have on this motherboard */
795
switch (c->x86_model) {
797
cpu_model = CPU_SAMUEL;
798
cpuname = "C3 'Samuel' [C5A]";
799
longhaul_version = TYPE_LONGHAUL_V1;
800
memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
801
memcpy(eblcr, samuel1_eblcr, sizeof(samuel1_eblcr));
805
switch (c->x86_mask) {
807
longhaul_version = TYPE_LONGHAUL_V1;
808
cpu_model = CPU_SAMUEL2;
809
cpuname = "C3 'Samuel 2' [C5B]";
810
/* Note, this is not a typo, early Samuel2's had
812
memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
813
memcpy(eblcr, samuel2_eblcr, sizeof(samuel2_eblcr));
816
longhaul_version = TYPE_LONGHAUL_V2;
817
if (c->x86_mask < 8) {
818
cpu_model = CPU_SAMUEL2;
819
cpuname = "C3 'Samuel 2' [C5B]";
821
cpu_model = CPU_EZRA;
822
cpuname = "C3 'Ezra' [C5C]";
824
memcpy(mults, ezra_mults, sizeof(ezra_mults));
825
memcpy(eblcr, ezra_eblcr, sizeof(ezra_eblcr));
831
cpu_model = CPU_EZRA_T;
832
cpuname = "C3 'Ezra-T' [C5M]";
833
longhaul_version = TYPE_POWERSAVER;
835
memcpy(mults, ezrat_mults, sizeof(ezrat_mults));
836
memcpy(eblcr, ezrat_eblcr, sizeof(ezrat_eblcr));
840
longhaul_version = TYPE_POWERSAVER;
842
memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
843
memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
844
switch (c->x86_mask) {
846
cpu_model = CPU_NEHEMIAH;
847
cpuname = "C3 'Nehemiah A' [C5XLOE]";
850
cpu_model = CPU_NEHEMIAH;
851
cpuname = "C3 'Nehemiah B' [C5XLOH]";
854
cpu_model = CPU_NEHEMIAH_C;
855
cpuname = "C3 'Nehemiah C' [C5P]";
864
/* Check Longhaul ver. 2 */
865
if (longhaul_version == TYPE_LONGHAUL_V2) {
866
rdmsr(MSR_VIA_LONGHAUL, lo, hi);
867
if (lo == 0 && hi == 0)
868
/* Looks like MSR isn't present */
869
longhaul_version = TYPE_LONGHAUL_V1;
872
printk(KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
873
switch (longhaul_version) {
874
case TYPE_LONGHAUL_V1:
875
case TYPE_LONGHAUL_V2:
876
printk(KERN_CONT "Longhaul v%d supported.\n", longhaul_version);
878
case TYPE_POWERSAVER:
879
printk(KERN_CONT "Powersaver supported.\n");
884
longhaul_setup_southbridge();
886
/* Find ACPI data for processor */
887
acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
888
ACPI_UINT32_MAX, &longhaul_walk_callback, NULL,
891
/* Check ACPI support for C3 state */
892
if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
893
cx = &pr->power.states[ACPI_STATE_C3];
894
if (cx->address > 0 && cx->latency <= 1000)
895
longhaul_flags |= USE_ACPI_C3;
897
/* Disable if it isn't working */
899
longhaul_flags &= ~USE_ACPI_C3;
900
/* Check if northbridge is friendly */
901
if (enable_arbiter_disable())
902
longhaul_flags |= USE_NORTHBRIDGE;
904
/* Check ACPI support for bus master arbiter disable */
905
if (!(longhaul_flags & USE_ACPI_C3
906
|| longhaul_flags & USE_NORTHBRIDGE)
907
&& ((pr == NULL) || !(pr->flags.bm_control))) {
909
"No ACPI support. Unsupported northbridge.\n");
913
if (longhaul_flags & USE_NORTHBRIDGE)
914
printk(KERN_INFO PFX "Using northbridge support.\n");
915
if (longhaul_flags & USE_ACPI_C3)
916
printk(KERN_INFO PFX "Using ACPI support.\n");
918
ret = longhaul_get_ranges();
922
if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
923
longhaul_setup_voltagescaling();
925
policy->cpuinfo.transition_latency = 200000; /* nsec */
926
policy->cur = calc_speed(longhaul_get_cpu_mult());
928
ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
932
cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
937
static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
939
cpufreq_frequency_table_put_attr(policy->cpu);
943
static struct freq_attr *longhaul_attr[] = {
944
&cpufreq_freq_attr_scaling_available_freqs,
948
static struct cpufreq_driver longhaul_driver = {
949
.verify = longhaul_verify,
950
.target = longhaul_target,
952
.init = longhaul_cpu_init,
953
.exit = __devexit_p(longhaul_cpu_exit),
955
.owner = THIS_MODULE,
956
.attr = longhaul_attr,
960
static int __init longhaul_init(void)
962
struct cpuinfo_x86 *c = &cpu_data(0);
964
if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
968
if (num_online_cpus() > 1) {
969
printk(KERN_ERR PFX "More than 1 CPU detected, "
970
"longhaul disabled.\n");
974
#ifdef CONFIG_X86_IO_APIC
976
printk(KERN_ERR PFX "APIC detected. Longhaul is currently "
977
"broken in this configuration.\n");
981
switch (c->x86_model) {
983
return cpufreq_register_driver(&longhaul_driver);
985
printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
994
static void __exit longhaul_exit(void)
998
for (i = 0; i < numscales; i++) {
999
if (mults[i] == maxmult) {
1000
longhaul_setstate(i);
1005
cpufreq_unregister_driver(&longhaul_driver);
1006
kfree(longhaul_table);
1009
/* Even if BIOS is exporting ACPI C3 state, and it is used
1010
* with success when CPU is idle, this state doesn't
1011
* trigger frequency transition in some cases. */
1012
module_param(disable_acpi_c3, int, 0644);
1013
MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
1014
/* Change CPU voltage with frequency. Very usefull to save
1015
* power, but most VIA C3 processors aren't supporting it. */
1016
module_param(scale_voltage, int, 0644);
1017
MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
1018
/* Force revision key to 0 for processors which doesn't
1019
* support voltage scaling, but are introducing itself as
1021
module_param(revid_errata, int, 0644);
1022
MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
1024
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1025
MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors.");
1026
MODULE_LICENSE("GPL");
1028
late_initcall(longhaul_init);
1029
module_exit(longhaul_exit);
added
removed
arch/x86/kernel/cpu/cpufreq/longhaul.c
