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Viewing changes to arch/arm/mach-lh7a40x/irq-lh7a404.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/arm/mach-lh7a40x/irq-lh7a404.c
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/* arch/arm/mach-lh7a40x/irq-lh7a404.c
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 *
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 *  Copyright (C) 2004 Logic Product Development
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 *
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 *  This program is free software; you can redistribute it and/or
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 *  modify it under the terms of the GNU General Public License
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 *  version 2 as published by the Free Software Foundation.
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 *
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 */
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/irqs.h>
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20
 
#include "common.h"
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#define USE_PRIORITIES
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/* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
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 * information on using the vectored interrupt controller's
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 * prioritizing feature. */
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static unsigned char irq_pri_vic1[] = {
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#if defined (USE_PRIORITIES)
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        IRQ_GPIO3INTR,                  /* CPLD */
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        IRQ_DMAM2P4, IRQ_DMAM2P5,       /* AC97 */
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#endif
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};
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static unsigned char irq_pri_vic2[] = {
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#if defined (USE_PRIORITIES)
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        IRQ_T3UI,                       /* Timer */
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        IRQ_GPIO7INTR,                  /* CPLD */
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        IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
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        IRQ_LCDINTR,                    /* LCD */
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        IRQ_TSCINTR,                    /* ADC/Touchscreen */
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#endif
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};
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44
 
  /* CPU IRQ handling */
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46
 
static void lh7a404_vic1_mask_irq(struct irq_data *d)
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{
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        VIC1_INTENCLR = (1 << d->irq);
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}
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51
 
static void lh7a404_vic1_unmask_irq(struct irq_data *d)
52
 
{
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        VIC1_INTEN = (1 << d->irq);
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}
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56
 
static void lh7a404_vic2_mask_irq(struct irq_data *d)
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{
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        VIC2_INTENCLR = (1 << (d->irq - 32));
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}
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61
 
static void lh7a404_vic2_unmask_irq(struct irq_data *d)
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{
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        VIC2_INTEN = (1 << (d->irq - 32));
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}
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static void lh7a404_vic1_ack_gpio_irq(struct irq_data *d)
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{
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        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
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        VIC1_INTENCLR = (1 << d->irq);
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}
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static void lh7a404_vic2_ack_gpio_irq(struct irq_data *d)
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{
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        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
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        VIC2_INTENCLR = (1 << d->irq);
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}
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static struct irq_chip lh7a404_vic1_chip = {
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        .name           = "VIC1",
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        .irq_ack        = lh7a404_vic1_mask_irq, /* Because level-triggered */
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        .irq_mask       = lh7a404_vic1_mask_irq,
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        .irq_unmask     = lh7a404_vic1_unmask_irq,
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};
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static struct irq_chip lh7a404_vic2_chip = {
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        .name           = "VIC2",
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        .irq_ack        = lh7a404_vic2_mask_irq, /* Because level-triggered */
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        .irq_mask       = lh7a404_vic2_mask_irq,
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        .irq_unmask     = lh7a404_vic2_unmask_irq,
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};
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static struct irq_chip lh7a404_gpio_vic1_chip = {
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        .name           = "GPIO-VIC1",
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        .irq_ack        = lh7a404_vic1_ack_gpio_irq,
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        .irq_mask       = lh7a404_vic1_mask_irq,
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        .irq_unmask     = lh7a404_vic1_unmask_irq,
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};
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static struct irq_chip lh7a404_gpio_vic2_chip = {
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        .name           = "GPIO-VIC2",
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        .irq_ack        = lh7a404_vic2_ack_gpio_irq,
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        .irq_mask       = lh7a404_vic2_mask_irq,
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        .irq_unmask     = lh7a404_vic2_unmask_irq,
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};
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  /* IRQ initialization */
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#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
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extern void* branch_irq_lh7a400;
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#endif
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void __init lh7a404_init_irq (void)
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{
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        int irq;
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#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
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#define NOP 0xe1a00000                  /* mov r0, r0 */
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        branch_irq_lh7a400 = NOP;
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#endif
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        VIC1_INTENCLR = 0xffffffff;
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        VIC2_INTENCLR = 0xffffffff;
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        VIC1_INTSEL = 0;                /* All IRQs */
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        VIC2_INTSEL = 0;                /* All IRQs */
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        VIC1_NVADDR = VA_VIC1DEFAULT;
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        VIC2_NVADDR = VA_VIC2DEFAULT;
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        VIC1_VECTADDR = 0;
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        VIC2_VECTADDR = 0;
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        GPIO_GPIOFINTEN = 0x00;         /* Disable all GPIOF interrupts */
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        barrier ();
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133
 
                /* Install prioritized interrupts, if there are any. */
134
 
                /* The | 0x20*/
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        for (irq = 0; irq < 16; ++irq) {
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                (&VIC1_VAD0)[irq]
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                        = (irq < ARRAY_SIZE (irq_pri_vic1))
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                        ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
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                (&VIC1_VECTCNTL0)[irq]
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                        = (irq < ARRAY_SIZE (irq_pri_vic1))
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                        ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
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                (&VIC2_VAD0)[irq]
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                        = (irq < ARRAY_SIZE (irq_pri_vic2))
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                        ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
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                (&VIC2_VECTCNTL0)[irq]
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                        = (irq < ARRAY_SIZE (irq_pri_vic2))
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                        ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
148
 
        }
149
 
 
150
 
        for (irq = 0; irq < NR_IRQS; ++irq) {
151
 
                switch (irq) {
152
 
                case IRQ_GPIO0INTR:
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                case IRQ_GPIO1INTR:
154
 
                case IRQ_GPIO2INTR:
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                case IRQ_GPIO3INTR:
156
 
                case IRQ_GPIO4INTR:
157
 
                case IRQ_GPIO5INTR:
158
 
                case IRQ_GPIO6INTR:
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                case IRQ_GPIO7INTR:
160
 
                        set_irq_chip (irq, irq < 32
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                                      ? &lh7a404_gpio_vic1_chip
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                                      : &lh7a404_gpio_vic2_chip);
163
 
                        set_irq_handler (irq, handle_level_irq); /* OK default */
164
 
                        break;
165
 
                default:
166
 
                        set_irq_chip (irq, irq < 32
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                                      ? &lh7a404_vic1_chip
168
 
                                      : &lh7a404_vic2_chip);
169
 
                        set_irq_handler (irq, handle_level_irq);
170
 
                }
171
 
                set_irq_flags (irq, IRQF_VALID);
172
 
        }
173
 
 
174
 
        lh7a40x_init_board_irq ();
175
 
}