~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise : revision 29

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/**********************************************************************

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*

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*

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* This program is free software; you can redistribute it and/or modify it

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* under the terms and conditions of the GNU General Public License,

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* version 2, as published by the Free Software Foundation.

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*

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* This program is distributed in the hope it will be useful but, except

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* as otherwise stated in writing, without any warranty; without even the

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* implied warranty of merchantability or fitness for a particular purpose.

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* See the GNU General Public License for more details.

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*

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* You should have received a copy of the GNU General Public License along with

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* this program; if not, write to the Free Software Foundation, Inc.,

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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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*

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* The full GNU General Public License is included in this distribution in

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* the file called "COPYING".

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*

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* Contact Information:

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* Imagination Technologies Ltd. <gpl-support@imgtec.com>

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* Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK

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*

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******************************************************************************/

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#ifndef _SGX543DEFS_KM_H_

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#define _SGX543DEFS_KM_H_

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#define EUR_CR_CLKGATECTL 0x0000

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#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U

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#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0

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#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU

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#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2

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#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U

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#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4

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#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U

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#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6

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#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U

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#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8

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#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U

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#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10

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#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U

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#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12

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#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U

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#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14

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#define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U

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#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16

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#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U

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#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18

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#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U

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#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20

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#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U

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#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24

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#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0

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#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U

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#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28

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#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2 0x0004

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#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U

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#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0

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#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU

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#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2

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#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U

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#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4

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#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U

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#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6

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#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U

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#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8

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#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U

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#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10

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#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U

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#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14

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#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U

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#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16

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#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U

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#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18

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#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U

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#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22

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#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U

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#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24

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#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0

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#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U

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#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26

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#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0

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#define EUR_CR_CLKGATESTATUS 0x0008

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#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U

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#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0

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#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U

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#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1

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#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U

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#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2

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#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U

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#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3

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#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U

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#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4

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#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U

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#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5

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#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U

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#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6

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#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U

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#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7

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#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U

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#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8

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#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U

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#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9

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#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U

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#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10

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#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U

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#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11

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#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U

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#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12

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#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U

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#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13

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#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U

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#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15

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#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U

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#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16

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#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U

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#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17

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#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U

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#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19

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#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U

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#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20

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#define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U

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#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21

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#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U

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#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22

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#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U

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#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23

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#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0

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#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U

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#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24

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#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR 0x000C

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#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U

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#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0

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#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU

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#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2

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#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U

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#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4

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#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U

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#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6

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#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U

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#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8

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#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U

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#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10

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#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U

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#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12

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#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U

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#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14

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#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U

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#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16

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#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U

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#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18

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#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0

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#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U

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#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20

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#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0

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#define EUR_CR_POWER 0x001C

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#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U

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#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0

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#define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0

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#define EUR_CR_CORE_ID 0x0020

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#define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U

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#define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0

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#define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0

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#define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U

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#define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1

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#define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0

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#define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU

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#define EUR_CR_CORE_ID_CONFIG_SHIFT 2

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#define EUR_CR_CORE_ID_CONFIG_SIGNED 0

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#define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U

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#define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8

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#define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0

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#define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U

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#define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12

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#define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0

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#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U

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#define EUR_CR_CORE_ID_ID_SHIFT 16

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#define EUR_CR_CORE_ID_ID_SIGNED 0

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#define EUR_CR_CORE_REVISION 0x0024

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#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU

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#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0

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#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0

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#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U

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#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8

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#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0

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#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U

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#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16

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#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0

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#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U

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#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24

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#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0

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#define EUR_CR_DESIGNER_REV_FIELD1 0x0028

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#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU

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#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0

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#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0

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#define EUR_CR_DESIGNER_REV_FIELD2 0x002C

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#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU

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#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0

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#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0

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#define EUR_CR_SOFT_RESET 0x0080

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#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U

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#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0

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#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U

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#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1

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#define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U

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#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2

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#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U

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#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3

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#define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U

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#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4

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#define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U

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#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5

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#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U

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#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6

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#define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U

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#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7

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#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U

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#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8

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#define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U

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#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9

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#define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U

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#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10

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#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U

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#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11

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#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U

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#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13

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#define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U

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#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14

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#define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U

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#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15

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#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U

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#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16

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#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U

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#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17

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#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U

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#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18

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#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0

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#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U

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#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19

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#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0

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#define EUR_CR_EVENT_HOST_ENABLE2 0x0110

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#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U

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#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11

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#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0

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#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U

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#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10

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#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0

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#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U

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#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9

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#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0

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#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U

324

#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8

325

#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0

326

#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U

327

#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7

328

#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0

329

#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U

330

#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6

331

#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0

332

#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U

333

#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5

334

#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0

335

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U

336

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4

337

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0

338

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U

339

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3

340

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0

341

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U

342

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2

343

#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0

344

#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U

345

#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1

346

#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0

347

#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U

348

#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0

349

#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0

350

#define EUR_CR_EVENT_HOST_CLEAR2 0x0114

351

#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U

352

#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11

353

#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0

354

#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U

355

#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10

356

#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0

357

#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U

358

#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9

359

#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0

360

#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U

361

#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8

362

#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0

363

#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U

364

#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7

365

#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0

366

#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U

367

#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6

368

#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0

369

#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U

370

#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5

371

#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0

372

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U

373

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4

374

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0

375

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U

376

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3

377

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0

378

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U

379

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2

380

#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0

381

#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U

382

#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1

383

#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0

384

#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U

385

#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0

386

#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0

387

#define EUR_CR_EVENT_STATUS2 0x0118

388

#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U

389

#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11

390

#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0

391

#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U

392

#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10

393

#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0

394

#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U

395

#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9

396

#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0

397

#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U

398

#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8

399

#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0

400

#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U

401

#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7

402

#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0

403

#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U

404

#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6

405

#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0

406

#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U

407

#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5

408

#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0

409

#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U

410

#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4

411

#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0

412

#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U

413

#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3

414

#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0

415

#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U

416

#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2

417

#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0

418

#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U

419

#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1

420

#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0

421

#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U

422

#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0

423

#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0

424

#define EUR_CR_EVENT_STATUS 0x012C

425

#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U

426

#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31

427

#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0

428

#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U

429

#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29

430

#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0

431

#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U

432

#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28

433

#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0

434

#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U

435

#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26

436

#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0

437

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U

438

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25

439

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0

440

#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U

441

#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24

442

#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0

443

#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U

444

#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23

445

#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0

446

#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U

447

#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22

448

#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0

449

#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U

450

#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21

451

#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0

452

#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U

453

#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20

454

#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0

455

#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U

456

#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19

457

#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0

458

#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U

459

#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18

460

#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0

461

#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U

462

#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15

463

#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0

464

#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U

465

#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14

466

#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0

467

#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U

468

#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13

469

#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0

470

#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U

471

#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12

472

#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0

473

#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U

474

#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11

475

#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0

476

#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U

477

#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10

478

#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0

479

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U

480

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9

481

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0

482

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U

483

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8

484

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0

485

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U

486

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7

487

#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0

488

#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U

489

#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6

490

#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0

491

#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U

492

#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5

493

#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0

494

#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U

495

#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4

496

#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0

497

#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U

498

#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3

499

#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0

500

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U

501

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2

502

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0

503

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U

504

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1

505

#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0

506

#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U

507

#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0

508

#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0

509

#define EUR_CR_EVENT_HOST_ENABLE 0x0130

510

#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U

511

#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31

512

#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0

513

#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U

514

#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29

515

#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0

516

#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U

517

#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28

518

#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0

519

#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U

520

#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26

521

#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0

522

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U

523

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25

524

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0

525

#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U

526

#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24

527

#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0

528

#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U

529

#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23

530

#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0

531

#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U

532

#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22

533

#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0

534

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U

535

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21

536

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0

537

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U

538

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20

539

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0

540

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U

541

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19

542

#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0

543

#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U

544

#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18

545

#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0

546

#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U

547

#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15

548

#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0

549

#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U

550

#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14

551

#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0

552

#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U

553

#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13

554

#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0

555

#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U

556

#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12

557

#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0

558

#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U

559

#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11

560

#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0

561

#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U

562

#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10

563

#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0

564

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U

565

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9

566

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0

567

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U

568

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8

569

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0

570

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U

571

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7

572

#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0

573

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U

574

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6

575

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0

576

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U

577

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5

578

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0

579

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U

580

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4

581

#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0

582

#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U

583

#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3

584

#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0

585

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U

586

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2

587

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0

588

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U

589

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1

590

#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0

591

#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U

592

#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0

593

#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0

594

#define EUR_CR_EVENT_HOST_CLEAR 0x0134

595

#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U

596

#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31

597

#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0

598

#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U

599

#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29

600

#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0

601

#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U

602

#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28

603

#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0

604

#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U

605

#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26

606

#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0

607

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U

608

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25

609

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0

610

#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U

611

#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24

612

#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0

613

#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U

614

#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23

615

#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0

616

#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U

617

#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22

618

#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0

619

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U

620

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21

621

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0

622

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U

623

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20

624

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0

625

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U

626

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19

627

#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0

628

#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U

629

#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18

630

#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0

631

#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U

632

#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15

633

#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0

634

#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U

635

#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14

636

#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0

637

#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U

638

#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13

639

#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0

640

#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U

641

#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12

642

#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0

643

#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U

644

#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11

645

#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0

646

#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U

647

#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10

648

#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0

649

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U

650

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9

651

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0

652

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U

653

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8

654

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0

655

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U

656

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7

657

#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0

658

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U

659

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6

660

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0

661

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U

662

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5

663

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0

664

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U

665

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4

666

#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0

667

#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U

668

#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3

669

#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0

670

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U

671

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2

672

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0

673

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U

674

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1

675

#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0

676

#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U

677

#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0

678

#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0

679

#define EUR_CR_TIMER 0x0144

680

#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU

681

#define EUR_CR_TIMER_VALUE_SHIFT 0

682

#define EUR_CR_TIMER_VALUE_SIGNED 0

683

#define EUR_CR_EVENT_KICK1 0x0AB0

684

#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU

685

#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0

686

#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0

687

#define EUR_CR_EVENT_KICK2 0x0AC0

688

#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U

689

#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0

690

#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0

691

#define EUR_CR_EVENT_KICKER 0x0AC4

692

#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U

693

#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4

694

#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0

695

#define EUR_CR_EVENT_KICK 0x0AC8

696

#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U

697

#define EUR_CR_EVENT_KICK_NOW_SHIFT 0

698

#define EUR_CR_EVENT_KICK_NOW_SIGNED 0

699

#define EUR_CR_EVENT_TIMER 0x0ACC

700

#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U

701

#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24

702

#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0

703

#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU

704

#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0

705

#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0

706

#define EUR_CR_PDS_INV0 0x0AD0

707

#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U

708

#define EUR_CR_PDS_INV0_DSC_SHIFT 0

709

#define EUR_CR_PDS_INV0_DSC_SIGNED 0

710

#define EUR_CR_PDS_INV1 0x0AD4

711

#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U

712

#define EUR_CR_PDS_INV1_DSC_SHIFT 0

713

#define EUR_CR_PDS_INV1_DSC_SIGNED 0

714

#define EUR_CR_EVENT_KICK3 0x0AD8

715

#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U

716

#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0

717

#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0

718

#define EUR_CR_PDS_INV3 0x0ADC

719

#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U

720

#define EUR_CR_PDS_INV3_DSC_SHIFT 0

721

#define EUR_CR_PDS_INV3_DSC_SIGNED 0

722

#define EUR_CR_PDS_INV_CSC 0x0AE0

723

#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U

724

#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0

725

#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0

726

#define EUR_CR_BIF_CTRL 0x0C00

727

#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U

728

#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0

729

#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0

730

#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U

731

#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1

732

#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0

733

#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U

734

#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4

735

#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0

736

#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U

737

#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9

738

#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0

739

#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U

740

#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10

741

#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0

742

#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U

743

#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12

744

#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0

745

#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U

746

#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13

747

#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0

748

#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U

749

#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14

750

#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0

751

#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U

752

#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15

753

#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0

754

#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U

755

#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16

756

#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0

757

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U

758

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17

759

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0

760

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U

761

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18

762

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0

763

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U

764

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19

765

#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0

766

#define EUR_CR_BIF_INT_STAT 0x0C04

767

#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU

768

#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0

769

#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0

770

#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U

771

#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16

772

#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0

773

#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U

774

#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19

775

#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0

776

#define EUR_CR_BIF_FAULT 0x0C08

777

#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU

778

#define EUR_CR_BIF_FAULT_CID_SHIFT 0

779

#define EUR_CR_BIF_FAULT_CID_SIGNED 0

780

#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U

781

#define EUR_CR_BIF_FAULT_SB_SHIFT 4

782

#define EUR_CR_BIF_FAULT_SB_SIGNED 0

783

#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U

784

#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12

785

#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0

786

#define EUR_CR_BIF_TILE0 0x0C0C

787

#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU

788

#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0

789

#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0

790

#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U

791

#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12

792

#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0

793

#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U

794

#define EUR_CR_BIF_TILE0_CFG_SHIFT 24

795

#define EUR_CR_BIF_TILE0_CFG_SIGNED 0

796

#define EUR_CR_BIF_TILE1 0x0C10

797

#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU

798

#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0

799

#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0

800

#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U

801

#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12

802

#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0

803

#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U

804

#define EUR_CR_BIF_TILE1_CFG_SHIFT 24

805

#define EUR_CR_BIF_TILE1_CFG_SIGNED 0

806

#define EUR_CR_BIF_TILE2 0x0C14

807

#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU

808

#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0

809

#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0

810

#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U

811

#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12

812

#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0

813

#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U

814

#define EUR_CR_BIF_TILE2_CFG_SHIFT 24

815

#define EUR_CR_BIF_TILE2_CFG_SIGNED 0

816

#define EUR_CR_BIF_TILE3 0x0C18

817

#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU

818

#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0

819

#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0

820

#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U

821

#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12

822

#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0

823

#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U

824

#define EUR_CR_BIF_TILE3_CFG_SHIFT 24

825

#define EUR_CR_BIF_TILE3_CFG_SIGNED 0

826

#define EUR_CR_BIF_TILE4 0x0C1C

827

#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU

828

#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0

829

#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0

830

#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U

831

#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12

832

#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0

833

#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U

834

#define EUR_CR_BIF_TILE4_CFG_SHIFT 24

835

#define EUR_CR_BIF_TILE4_CFG_SIGNED 0

836

#define EUR_CR_BIF_TILE5 0x0C20

837

#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU

838

#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0

839

#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0

840

#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U

841

#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12

842

#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0

843

#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U

844

#define EUR_CR_BIF_TILE5_CFG_SHIFT 24

845

#define EUR_CR_BIF_TILE5_CFG_SIGNED 0

846

#define EUR_CR_BIF_TILE6 0x0C24

847

#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU

848

#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0

849

#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0

850

#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U

851

#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12

852

#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0

853

#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U

854

#define EUR_CR_BIF_TILE6_CFG_SHIFT 24

855

#define EUR_CR_BIF_TILE6_CFG_SIGNED 0

856

#define EUR_CR_BIF_TILE7 0x0C28

857

#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU

858

#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0

859

#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0

860

#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U

861

#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12

862

#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0

863

#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U

864

#define EUR_CR_BIF_TILE7_CFG_SHIFT 24

865

#define EUR_CR_BIF_TILE7_CFG_SIGNED 0

866

#define EUR_CR_BIF_TILE8 0x0C2C

867

#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU

868

#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0

869

#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0

870

#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U

871

#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12

872

#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0

873

#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U

874

#define EUR_CR_BIF_TILE8_CFG_SHIFT 24

875

#define EUR_CR_BIF_TILE8_CFG_SIGNED 0

876

#define EUR_CR_BIF_TILE9 0x0C30

877

#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU

878

#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0

879

#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0

880

#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U

881

#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12

882

#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0

883

#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U

884

#define EUR_CR_BIF_TILE9_CFG_SHIFT 24

885

#define EUR_CR_BIF_TILE9_CFG_SIGNED 0

886

#define EUR_CR_BIF_CTRL_INVAL 0x0C34

887

#define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U

888

#define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2

889

#define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0

890

#define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U

891

#define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3

892

#define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0

893

#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38

894

#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U

895

#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12

896

#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0

897

#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C

898

#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U

899

#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12

900

#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0

901

#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40

902

#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U

903

#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12

904

#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0

905

#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44

906

#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U

907

#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12

908

#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0

909

#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48

910

#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U

911

#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12

912

#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0

913

#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C

914

#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U

915

#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12

916

#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0

917

#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50

918

#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U

919

#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12

920

#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0

921

#define EUR_CR_BIF_BANK_SET 0x0C74

922

#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U

923

#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0

924

#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0

925

#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU

926

#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2

927

#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0

928

#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U

929

#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4

930

#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0

931

#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U

932

#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6

933

#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0

934

#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U

935

#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8

936

#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0

937

#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U

938

#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9

939

#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0

940

#define EUR_CR_BIF_BANK0 0x0C78

941

#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU

942

#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0

943

#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0

944

#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U

945

#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4

946

#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0

947

#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U

948

#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12

949

#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0

950

#define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U

951

#define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16

952

#define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0

953

#define EUR_CR_BIF_BANK1 0x0C7C

954

#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU

955

#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0

956

#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0

957

#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U

958

#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4

959

#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0

960

#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U

961

#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12

962

#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0

963

#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84

964

#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U

965

#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12

966

#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0

967

#define EUR_CR_BIF_TA_REQ_BASE 0x0C90

968

#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U

969

#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20

970

#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0

971

#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8

972

#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU

973

#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0

974

#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0

975

#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC

976

#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U

977

#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20

978

#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0

979

#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0

980

#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U

981

#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20

982

#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0

983

#define EUR_CR_BIF_BANK_STATUS 0x0CB4

984

#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U

985

#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0

986

#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0

987

#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U

988

#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1

989

#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0

990

#define EUR_CR_BIF_MMU_CTRL 0x0CD0

991

#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U

992

#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0

993

#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0

994

#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U

995

#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1

996

#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0

997

#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U

998

#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3

999

#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0

1000

#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U

1001

#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4

1002

#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0

1003

#define EUR_CR_2D_BLIT_STATUS 0x0E04

1004

#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU

1005

#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0

1006

#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0

1007

#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U

1008

#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24

1009

#define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0

1010

#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10

1011

#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U

1012

#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0

1013

#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0

1014

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU

1015

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1

1016

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0

1017

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U

1018

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4

1019

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0

1020

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U

1021

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12

1022

#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0

1023

#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14

1024

#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU

1025

#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0

1026

#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0

1027

#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U

1028

#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12

1029

#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0

1030

#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U

1031

#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24

1032

#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0

1033

#define EUR_CR_BREAKPOINT0_START 0x0F44

1034

#define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U

1035

#define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4

1036

#define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0

1037

#define EUR_CR_BREAKPOINT0_END 0x0F48

1038

#define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U

1039

#define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4

1040

#define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0

1041

#define EUR_CR_BREAKPOINT0 0x0F4C

1042

#define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U

1043

#define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3

1044

#define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0

1045

#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U

1046

#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2

1047

#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0

1048

#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U

1049

#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1

1050

#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0

1051

#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U

1052

#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0

1053

#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0

1054

#define EUR_CR_BREAKPOINT1_START 0x0F50

1055

#define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U

1056

#define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4

1057

#define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0

1058

#define EUR_CR_BREAKPOINT1_END 0x0F54

1059

#define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U

1060

#define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4

1061

#define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0

1062

#define EUR_CR_BREAKPOINT1 0x0F58

1063

#define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U

1064

#define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3

1065

#define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0

1066

#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U

1067

#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2

1068

#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0

1069

#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U

1070

#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1

1071

#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0

1072

#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U

1073

#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0

1074

#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0

1075

#define EUR_CR_BREAKPOINT2_START 0x0F5C

1076

#define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U

1077

#define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4

1078

#define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0

1079

#define EUR_CR_BREAKPOINT2_END 0x0F60

1080

#define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U

1081

#define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4

1082

#define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0

1083

#define EUR_CR_BREAKPOINT2 0x0F64

1084

#define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U

1085

#define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3

1086

#define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0

1087

#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U

1088

#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2

1089

#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0

1090

#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U

1091

#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1

1092

#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0

1093

#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U

1094

#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0

1095

#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0

1096

#define EUR_CR_BREAKPOINT3_START 0x0F68

1097

#define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U

1098

#define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4

1099

#define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0

1100

#define EUR_CR_BREAKPOINT3_END 0x0F6C

1101

#define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U

1102

#define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4

1103

#define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0

1104

#define EUR_CR_BREAKPOINT3 0x0F70

1105

#define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U

1106

#define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3

1107

#define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0

1108

#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U

1109

#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2

1110

#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0

1111

#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U

1112

#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1

1113

#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0

1114

#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U

1115

#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0

1116

#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0

1117

#define EUR_CR_BREAKPOINT_READ 0x0F74

1118

#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U

1119

#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4

1120

#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0

1121

#define EUR_CR_BREAKPOINT_TRAP 0x0F78

1122

#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U

1123

#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SHIFT 1

1124

#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SIGNED 0

1125

#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U

1126

#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0

1127

#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0

1128

#define EUR_CR_BREAKPOINT 0x0F7C

1129

#define EUR_CR_BREAKPOINT_MODULE_ID_MASK 0x000003C0U

1130

#define EUR_CR_BREAKPOINT_MODULE_ID_SHIFT 6

1131

#define EUR_CR_BREAKPOINT_MODULE_ID_SIGNED 0

1132

#define EUR_CR_BREAKPOINT_ID_MASK 0x00000030U

1133

#define EUR_CR_BREAKPOINT_ID_SHIFT 4

1134

#define EUR_CR_BREAKPOINT_ID_SIGNED 0

1135

#define EUR_CR_BREAKPOINT_UNTRAPPED_MASK 0x00000008U

1136

#define EUR_CR_BREAKPOINT_UNTRAPPED_SHIFT 3

1137

#define EUR_CR_BREAKPOINT_UNTRAPPED_SIGNED 0

1138

#define EUR_CR_BREAKPOINT_TRAPPED_MASK 0x00000004U

1139

#define EUR_CR_BREAKPOINT_TRAPPED_SHIFT 2

1140

#define EUR_CR_BREAKPOINT_TRAPPED_SIGNED 0

1141

#define EUR_CR_BREAKPOINT_TRAP_INFO0 0x0F80

1142

#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U

1143

#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4

1144

#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0

1145

#define EUR_CR_BREAKPOINT_TRAP_INFO1 0x0F84

1146

#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U

1147

#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10

1148

#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0

1149

#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U

1150

#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8

1151

#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0

1152

#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U

1153

#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3

1154

#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0

1155

#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U

1156

#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1

1157

#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0

1158

#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U

1159

#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0

1160

#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0

1161

#define EUR_CR_USE_CODE_BASE_0 0x0A0C

1162

#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU

1163

#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0

1164

#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0

1165

#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U

1166

#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26

1167

#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0

1168

#define EUR_CR_USE_CODE_BASE_1 0x0A10

1169

#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU

1170

#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0

1171

#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0

1172

#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U

1173

#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26

1174

#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0

1175

#define EUR_CR_USE_CODE_BASE_2 0x0A14

1176

#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU

1177

#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0

1178

#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0

1179

#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U

1180

#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26

1181

#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0

1182

#define EUR_CR_USE_CODE_BASE_3 0x0A18

1183

#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU

1184

#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0

1185

#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0

1186

#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U

1187

#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26

1188

#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0

1189

#define EUR_CR_USE_CODE_BASE_4 0x0A1C

1190

#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU

1191

#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0

1192

#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0

1193

#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U

1194

#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26

1195

#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0

1196

#define EUR_CR_USE_CODE_BASE_5 0x0A20

1197

#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU

1198

#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0

1199

#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0

1200

#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U

1201

#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26

1202

#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0

1203

#define EUR_CR_USE_CODE_BASE_6 0x0A24

1204

#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU

1205

#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0

1206

#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0

1207

#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U

1208

#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26

1209

#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0

1210

#define EUR_CR_USE_CODE_BASE_7 0x0A28

1211

#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU

1212

#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0

1213

#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0

1214

#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U

1215

#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26

1216

#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0

1217

#define EUR_CR_USE_CODE_BASE_8 0x0A2C

1218

#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU

1219

#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0

1220

#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0

1221

#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U

1222

#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26

1223

#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0

1224

#define EUR_CR_USE_CODE_BASE_9 0x0A30

1225

#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU

1226

#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0

1227

#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0

1228

#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U

1229

#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26

1230

#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0

1231

#define EUR_CR_USE_CODE_BASE_10 0x0A34

1232

#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU

1233

#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0

1234

#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0

1235

#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U

1236

#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26

1237

#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0

1238

#define EUR_CR_USE_CODE_BASE_11 0x0A38

1239

#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU

1240

#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0

1241

#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0

1242

#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U

1243

#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26

1244

#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0

1245

#define EUR_CR_USE_CODE_BASE_12 0x0A3C

1246

#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU

1247

#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0

1248

#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0

1249

#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U

1250

#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26

1251

#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0

1252

#define EUR_CR_USE_CODE_BASE_13 0x0A40

1253

#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU

1254

#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0

1255

#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0

1256

#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U

1257

#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26

1258

#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0

1259

#define EUR_CR_USE_CODE_BASE_14 0x0A44

1260

#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU

1261

#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0

1262

#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0

1263

#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U

1264

#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26

1265

#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0

1266

#define EUR_CR_USE_CODE_BASE_15 0x0A48

1267

#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU

1268

#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0

1269

#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0

1270

#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U

1271

#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26

1272

#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0

1273

#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))

1274

#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU

1275

#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0

1276

#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0

1277

#define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U

1278

#define EUR_CR_USE_CODE_BASE_DM_SHIFT 26

1279

#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0

1280

#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16

1281

#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16

1282

1283

#endif

1284