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Viewing changes to drivers/net/ixgbe/ixgbe_dcb_82598.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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drivers/net/ixgbe/ixgbe_dcb_82598.c
1
1
/*******************************************************************************
2
2
 
3
3
  Intel 10 Gigabit PCI Express Linux driver
4
 
  Copyright(c) 1999 - 2010 Intel Corporation.
 
4
  Copyright(c) 1999 - 2011 Intel Corporation.
5
5
 
6
6
  This program is free software; you can redistribute it and/or modify it
7
7
  under the terms and conditions of the GNU General Public License,
38
38
 *
39
39
 * Configure packet buffers for DCB mode.
40
40
 */
41
 
static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
42
 
                                                 struct ixgbe_dcb_config *dcb_config)
 
41
static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba)
43
42
{
44
43
        s32 ret_val = 0;
45
44
        u32 value = IXGBE_RXPBSIZE_64KB;
46
45
        u8  i = 0;
47
46
 
48
47
        /* Setup Rx packet buffer sizes */
49
 
        switch (dcb_config->rx_pba_cfg) {
 
48
        switch (rx_pba) {
50
49
        case pba_80_48:
51
50
                /* Setup the first four at 80KB */
52
51
                value = IXGBE_RXPBSIZE_80KB;
78
77
 *
79
78
 * Configure Rx Data Arbiter and credits for each traffic class.
80
79
 */
81
 
static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
82
 
                                      struct ixgbe_dcb_config *dcb_config)
 
80
s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
 
81
                                        u16 *refill,
 
82
                                        u16 *max,
 
83
                                        u8 *prio_type)
83
84
{
84
 
        struct tc_bw_alloc    *p;
85
85
        u32    reg           = 0;
86
86
        u32    credit_refill = 0;
87
87
        u32    credit_max    = 0;
102
102
 
103
103
        /* Configure traffic class credits and priority */
104
104
        for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
105
 
                p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
106
 
                credit_refill = p->data_credits_refill;
107
 
                credit_max    = p->data_credits_max;
 
105
                credit_refill = refill[i];
 
106
                credit_max    = max[i];
108
107
 
109
108
                reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
110
109
 
111
 
                if (p->prio_type == prio_link)
 
110
                if (prio_type[i] == prio_link)
112
111
                        reg |= IXGBE_RT2CR_LSP;
113
112
 
114
113
                IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
135
134
 *
136
135
 * Configure Tx Descriptor Arbiter and credits for each traffic class.
137
136
 */
138
 
static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
139
 
                                           struct ixgbe_dcb_config *dcb_config)
 
137
s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
 
138
                                                u16 *refill,
 
139
                                                u16 *max,
 
140
                                                u8 *bwg_id,
 
141
                                                u8 *prio_type)
140
142
{
141
 
        struct tc_bw_alloc *p;
142
143
        u32    reg, max_credits;
143
144
        u8     i;
144
145
 
146
147
 
147
148
        /* Enable arbiter */
148
149
        reg &= ~IXGBE_DPMCS_ARBDIS;
149
 
        if (!(dcb_config->round_robin_enable)) {
150
 
                /* Enable DFP and Recycle mode */
151
 
                reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
152
 
        }
 
150
        /* Enable DFP and Recycle mode */
 
151
        reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
153
152
        reg |= IXGBE_DPMCS_TSOEF;
154
153
        /* Configure Max TSO packet size 34KB including payload and headers */
155
154
        reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
158
157
 
159
158
        /* Configure traffic class credits and priority */
160
159
        for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
161
 
                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
162
 
                max_credits = dcb_config->tc_config[i].desc_credits_max;
 
160
                max_credits = max[i];
163
161
                reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
164
 
                reg |= p->data_credits_refill;
165
 
                reg |= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
 
162
                reg |= refill[i];
 
163
                reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
166
164
 
167
 
                if (p->prio_type == prio_group)
 
165
                if (prio_type[i] == prio_group)
168
166
                        reg |= IXGBE_TDTQ2TCCR_GSP;
169
167
 
170
 
                if (p->prio_type == prio_link)
 
168
                if (prio_type[i] == prio_link)
171
169
                        reg |= IXGBE_TDTQ2TCCR_LSP;
172
170
 
173
171
                IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
183
181
 *
184
182
 * Configure Tx Data Arbiter and credits for each traffic class.
185
183
 */
186
 
static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
187
 
                                           struct ixgbe_dcb_config *dcb_config)
 
184
s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
 
185
                                                u16 *refill,
 
186
                                                u16 *max,
 
187
                                                u8 *bwg_id,
 
188
                                                u8 *prio_type)
188
189
{
189
 
        struct tc_bw_alloc *p;
190
190
        u32 reg;
191
191
        u8 i;
192
192
 
200
200
 
201
201
        /* Configure traffic class credits and priority */
202
202
        for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
203
 
                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
204
 
                reg = p->data_credits_refill;
205
 
                reg |= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT;
206
 
                reg |= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;
 
203
                reg = refill[i];
 
204
                reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
 
205
                reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
207
206
 
208
 
                if (p->prio_type == prio_group)
 
207
                if (prio_type[i] == prio_group)
209
208
                        reg |= IXGBE_TDPT2TCCR_GSP;
210
209
 
211
 
                if (p->prio_type == prio_link)
 
210
                if (prio_type[i] == prio_link)
212
211
                        reg |= IXGBE_TDPT2TCCR_LSP;
213
212
 
214
213
                IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
229
228
 *
230
229
 * Configure Priority Flow Control for each traffic class.
231
230
 */
232
 
s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
233
 
                               struct ixgbe_dcb_config *dcb_config)
 
231
s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
234
232
{
235
233
        u32 reg, rx_pba_size;
236
234
        u8  i;
237
235
 
238
 
        if (!dcb_config->pfc_mode_enable)
239
 
                goto out;
240
 
 
241
 
        /* Enable Transmit Priority Flow Control */
242
 
        reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
243
 
        reg &= ~IXGBE_RMCS_TFCE_802_3X;
244
 
        /* correct the reporting of our flow control status */
245
 
        reg |= IXGBE_RMCS_TFCE_PRIORITY;
246
 
        IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
247
 
 
248
 
        /* Enable Receive Priority Flow Control */
249
 
        reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
250
 
        reg &= ~IXGBE_FCTRL_RFCE;
251
 
        reg |= IXGBE_FCTRL_RPFCE;
252
 
        IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
 
236
        if (pfc_en) {
 
237
                /* Enable Transmit Priority Flow Control */
 
238
                reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 
239
                reg &= ~IXGBE_RMCS_TFCE_802_3X;
 
240
                /* correct the reporting of our flow control status */
 
241
                reg |= IXGBE_RMCS_TFCE_PRIORITY;
 
242
                IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
 
243
 
 
244
                /* Enable Receive Priority Flow Control */
 
245
                reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 
246
                reg &= ~IXGBE_FCTRL_RFCE;
 
247
                reg |= IXGBE_FCTRL_RPFCE;
 
248
                IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
 
249
 
 
250
                /* Configure pause time */
 
251
                for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
 
252
                        IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
 
253
 
 
254
                /* Configure flow control refresh threshold value */
 
255
                IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
 
256
        }
253
257
 
254
258
        /*
255
259
         * Configure flow control thresholds and enable priority flow control
256
260
         * for each traffic class.
257
261
         */
258
262
        for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 
263
                int enabled = pfc_en & (1 << i);
259
264
                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
260
265
                rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
261
266
                reg = (rx_pba_size - hw->fc.low_water) << 10;
262
267
 
263
 
                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
264
 
                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
 
268
                if (enabled == pfc_enabled_tx ||
 
269
                    enabled == pfc_enabled_full)
265
270
                        reg |= IXGBE_FCRTL_XONE;
266
271
 
267
272
                IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
268
273
 
269
274
                reg = (rx_pba_size - hw->fc.high_water) << 10;
270
 
                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
271
 
                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
 
275
                if (enabled == pfc_enabled_tx ||
 
276
                    enabled == pfc_enabled_full)
272
277
                        reg |= IXGBE_FCRTH_FCEN;
273
278
 
274
279
                IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
275
280
        }
276
281
 
277
 
        /* Configure pause time */
278
 
        for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
279
 
                IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
280
 
 
281
 
        /* Configure flow control refresh threshold value */
282
 
        IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
283
 
 
284
 
out:
285
282
        return 0;
286
283
}
287
284
 
325
322
 * Configure dcb settings and enable dcb mode.
326
323
 */
327
324
s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
328
 
                              struct ixgbe_dcb_config *dcb_config)
 
325
                              u8 rx_pba, u8 pfc_en, u16 *refill,
 
326
                              u16 *max, u8 *bwg_id, u8 *prio_type)
329
327
{
330
 
        ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config);
331
 
        ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
332
 
        ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
333
 
        ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
334
 
        ixgbe_dcb_config_pfc_82598(hw, dcb_config);
 
328
        ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba);
 
329
        ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
 
330
        ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
 
331
                                               bwg_id, prio_type);
 
332
        ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
 
333
                                               bwg_id, prio_type);
 
334
        ixgbe_dcb_config_pfc_82598(hw, pfc_en);
335
335
        ixgbe_dcb_config_tc_stats_82598(hw);
336
336
 
337
337
        return 0;