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Viewing changes to arch/arm/mach-stmp378x/include/mach/regs-i2c.h

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/arm/mach-stmp378x/include/mach/regs-i2c.h
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/*
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 * stmp378x: I2C register definitions
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 *
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 * Copyright (c) 2008 Freescale Semiconductor
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 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
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 */
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#define REGS_I2C_BASE   (STMP3XXX_REGS_BASE + 0x58000)
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#define REGS_I2C_PHYS   0x80058000
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#define REGS_I2C_SIZE   0x2000
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#define HW_I2C_CTRL0            0x0
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#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
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#define BP_I2C_CTRL0_XFER_COUNT 0
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#define BM_I2C_CTRL0_DIRECTION  0x00010000
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#define BM_I2C_CTRL0_MASTER_MODE        0x00020000
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#define BM_I2C_CTRL0_PRE_SEND_START     0x00080000
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#define BM_I2C_CTRL0_POST_SEND_STOP     0x00100000
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#define BM_I2C_CTRL0_RETAIN_CLOCK       0x00200000
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#define BM_I2C_CTRL0_SEND_NAK_ON_LAST   0x02000000
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#define BM_I2C_CTRL0_CLKGATE    0x40000000
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#define BM_I2C_CTRL0_SFTRST     0x80000000
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#define HW_I2C_TIMING0          0x10
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#define HW_I2C_TIMING1          0x20
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#define HW_I2C_TIMING2          0x30
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#define HW_I2C_CTRL1            0x40
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#define BM_I2C_CTRL1_SLAVE_IRQ  0x00000001
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#define BP_I2C_CTRL1_SLAVE_IRQ  0
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#define BM_I2C_CTRL1_SLAVE_STOP_IRQ     0x00000002
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#define BM_I2C_CTRL1_MASTER_LOSS_IRQ    0x00000004
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#define BM_I2C_CTRL1_EARLY_TERM_IRQ     0x00000008
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#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ     0x00000010
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#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ   0x00000020
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#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ      0x00000040
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#define BM_I2C_CTRL1_BUS_FREE_IRQ       0x00000080
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#define BM_I2C_CTRL1_CLR_GOT_A_NAK      0x10000000
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#define HW_I2C_VERSION          0x90