~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise

RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));

849

if(ptrArray[i] == 0x318)

850

{

851

ptrArray[i+2] = 0x00000800;

852

}

853

PHY_SetBBReg(dev, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);

854

}*/

855

for(i = 0 ;i < ArrayLength;i=i+2){

856

write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);

857

}

858

return true;

859

}

860

861

862

static bool

863

phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)

864

{

865

int i;

866

u32* Rtl819XPHY_REGArray_Table;

867

u32* Rtl819XAGCTAB_Array_Table;

868

u16 PHY_REGArrayLen, AGCTAB_ArrayLen;

869

/*if(dev->bInHctTest)

870

{

871

872

AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;

873

Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;

874

875

if(pHalData->RF_Type == RF_2T4R)

876

{

877

PHY_REGArrayLen = PHY_REGArrayLengthDTM;

878

Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;

879

}

880

else if (pHalData->RF_Type == RF_1T2R)

881

{

882

PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;

883

Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;

884

}

885

886

}

887

else

888

889

AGCTAB_ArrayLen = AGCTAB_ArrayLength;

890

Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;

891

PHY_REGArrayLen = PHY_REG_2T2RArrayLength;

892

Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;

893

894

if(ConfigType == BaseBand_Config_PHY_REG)

895

{

896

for(i=0;i<PHY_REGArrayLen;i=i+2)

897

{

898

if (Rtl819XPHY_REGArray_Table[i] == 0xfe)

899

mdelay(50);

900

else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)

901

mdelay(5);

902

else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)

903

mdelay(1);

904

else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)

905

udelay(50);

906

else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)

907

udelay(5);

908

else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)

909

udelay(1);

910

911

udelay(1);

912

913

rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);

914

915

}

916

}

917

else if(ConfigType == BaseBand_Config_AGC_TAB){

918

for(i=0;i<AGCTAB_ArrayLen;i=i+2)

919

{

920

rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);

921

udelay(1);

922

}

923

}

924

return true;

925

}

926

927

928

static bool

929

phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)

930

{

931

int i;

932

struct r8192_priv *priv = rtllib_priv(dev);

933

u32* Rtl819XPHY_REGArraytoXTXR_Table;

934

u16 PHY_REGArraytoXTXRLen;

935

936

if(priv->rf_type == RF_1T1R)

937

{

938

Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;

939

PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;

940

}

941

else if(priv->rf_type == RF_1T2R)

942

{

943

Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;

944

PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;

945

}

946

else

947

{

948

return false;

949

}

950

951

if(ConfigType == BaseBand_Config_PHY_REG)

952

{

953

for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)

954

{

955

if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)

956

mdelay(50);

957

else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)

958

mdelay(5);

959

else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)

960

mdelay(1);

961

else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)

962

udelay(50);

963

else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)

964

udelay(5);

965

else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)

966

udelay(1);

967

rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);

968

}

969

}

970

else {

971

RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");

972

}

973

return true;

974

}

975

976

void

977

storePwrIndexDiffRateOffset(

978

struct net_device* dev,

979

u32 RegAddr,

980

u32 BitMask,

981

u32 Data

982

)

983

{

984

struct r8192_priv *priv = rtllib_priv(dev);

985

986

if(RegAddr == rTxAGC_Rate18_06)

987

{

988

priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][0] = Data;

989

}

990

if(RegAddr == rTxAGC_Rate54_24)

991

{

992

priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][1] = Data;

993

}

994

if(RegAddr == rTxAGC_CCK_Mcs32)

995

{

996

priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][6] = Data;

997

}

998

if(RegAddr == rTxAGC_Mcs03_Mcs00)

999

{

1000

priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][2] = Data;

1001

}

1002

if(RegAddr == rTxAGC_Mcs07_Mcs04)

1003

{

1004

priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][3] = Data;

1005

}

1006

if(RegAddr == rTxAGC_Mcs11_Mcs08)

1007

{

1008

priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][4] = Data;

1009

}

1010

if(RegAddr == rTxAGC_Mcs15_Mcs12)

1011

{

1012

priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][5] = Data;

1013

priv->pwrGroupCnt++;

1014

}

1015

}

1016

1017

static bool

1018

phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)

1019

{

1020

int i;

1021

u32* Rtl819XPHY_REGArray_Table_PG;

1022

u16 PHY_REGArrayPGLen;

1023

1024

PHY_REGArrayPGLen = PHY_REG_Array_PGLength;

1025

Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;

1026

1027

if(ConfigType == BaseBand_Config_PHY_REG)

1028

{

1029

for(i=0;i<PHY_REGArrayPGLen;i=i+3)

1030

{

1031

if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)

1032

mdelay(50);

1033

else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)

1034

mdelay(5);

1035

else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)

1036

mdelay(1);

1037

else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)

1038

udelay(50);

1039

else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)

1040

udelay(5);

1041

else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)

1042

udelay(1);

1043

storePwrIndexDiffRateOffset(dev, Rtl819XPHY_REGArray_Table_PG[i],

1044

Rtl819XPHY_REGArray_Table_PG[i+1],

1045

Rtl819XPHY_REGArray_Table_PG[i+2]);

1046

rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);

1047

}

1048

}

1049

else{

1050

RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");

1051

}

1052

return true;

1053

1054

} /* phy_ConfigBBWithPgHeaderFile */

1055

1056

RT_STATUS rtl8192_phy_configRFPABiascurrent(struct net_device *dev, RF90_RADIO_PATH_E eRFPath)

1057

{

1058

struct r8192_priv *priv = rtllib_priv(dev);

1059

RT_STATUS rtStatus = RT_STATUS_SUCCESS;

1060

u32 tmpval=0;

1061

1062

if(priv->IC_Class != IC_INFERIORITY_A)

1063

{

1064

tmpval = rtl8192_phy_QueryRFReg(dev, eRFPath, RF_IPA, 0xf);

1065

rtl8192_phy_SetRFReg(dev, eRFPath, RF_IPA, 0xf, tmpval+1);

1066

}

1067

1068

return rtStatus;

1069

}

1070

1071

u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)

1072

{

1073

struct r8192_priv *priv = rtllib_priv(dev);

1074

int i;

1075

bool rtStatus = true;

1076

u32 *Rtl819XRadioA_Array_Table;

1077

u32 *Rtl819XRadioB_Array_Table;

1078

u16 RadioA_ArrayLen,RadioB_ArrayLen;

1079

1080

RadioA_ArrayLen = RadioA_1T_ArrayLength;

1081

Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;

1082

1083

if(priv->rf_type == RF_2T2R_GREEN)

1084

{

1085

Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;

1086

RadioB_ArrayLen = RadioB_GM_ArrayLength;

1087

}

1088

else

1089

{

1090

Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;

1091

RadioB_ArrayLen = RadioB_ArrayLength;

1092

}

1093

1094

1095

RT_TRACE(COMP_INIT, "PHY_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath);

1096

rtStatus = true;

1097

1098

switch(eRFPath){

1099

case RF90_PATH_A:

1100

for(i = 0;i<RadioA_ArrayLen; i=i+2)

1101

{

1102

if(Rtl819XRadioA_Array_Table[i] == 0xfe)

1103

{

1104

mdelay(50);

1105

}

1106

else if (Rtl819XRadioA_Array_Table[i] == 0xfd)

1107

mdelay(5);

1108

else if (Rtl819XRadioA_Array_Table[i] == 0xfc)

1109

mdelay(1);

1110

else if (Rtl819XRadioA_Array_Table[i] == 0xfb)

1111

udelay(50);

1112

else if (Rtl819XRadioA_Array_Table[i] == 0xfa)

1113

udelay(5);

1114

else if (Rtl819XRadioA_Array_Table[i] == 0xf9)

1115

udelay(1);

1116

else {

1117

rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i],

1118

bMask20Bits, Rtl819XRadioA_Array_Table[i+1]);

1119

}

1120

1121

udelay(1);

1122

}

1123

rtl8192_phy_configRFPABiascurrent(dev, eRFPath);

1124

break;

1125

case RF90_PATH_B:

1126

for(i = 0;i<RadioB_ArrayLen; i=i+2){

1127

if(Rtl819XRadioB_Array_Table[i] == 0xfe)

1128

{

1129

mdelay(50);

1130

}

1131

else if (Rtl819XRadioB_Array_Table[i] == 0xfd)

1132

mdelay(5);

1133

else if (Rtl819XRadioB_Array_Table[i] == 0xfc)

1134

mdelay(1);

1135

else if (Rtl819XRadioB_Array_Table[i] == 0xfb)

1136

udelay(50);

1137

else if (Rtl819XRadioB_Array_Table[i] == 0xfa)

1138

udelay(5);

1139

else if (Rtl819XRadioB_Array_Table[i] == 0xf9)

1140

udelay(1);

1141

else

1142

{

1143

rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bMask20Bits, Rtl819XRadioB_Array_Table[i+1]);

1144

}

1145

1146

udelay(1);

1147

}

1148

break;

1149

case RF90_PATH_C:

1150

break;

1151

case RF90_PATH_D:

1152

break;

1153

default:

1154

break;

1155

}

1156

return rtStatus;

1157

1158

}

1159

1160

bool rtl8192_phy_checkBBAndRF(

1161

struct net_device* dev,

1162

HW90_BLOCK_E CheckBlock,

1163

RF90_RADIO_PATH_E eRFPath

1164

)

1165

{

1166

bool rtStatus = true;

1167

u32 i, CheckTimes = 4,ulRegRead = 0;

1168

u32 WriteAddr[4];

1169

u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};

1170

1171

WriteAddr[HW90_BLOCK_MAC] = 0x100;

1172

WriteAddr[HW90_BLOCK_PHY0] = 0x900;

1173

WriteAddr[HW90_BLOCK_PHY1] = 0x800;

1174

WriteAddr[HW90_BLOCK_RF] = 0x3;

1175

1176

for(i=0 ; i < CheckTimes ; i++)

1177

{

1178

1179

switch(CheckBlock)

1180

{

1181

case HW90_BLOCK_MAC:

1182

RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");

1183

break;

1184

1185

case HW90_BLOCK_PHY0:

1186

case HW90_BLOCK_PHY1:

1187

write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);

1188

ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);

1189

break;

1190

1191

case HW90_BLOCK_RF:

1192

WriteData[i] &= 0xfff;

1193

rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask20Bits, WriteData[i]);

1194

mdelay(10);

1195

ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);

1196

mdelay(10);

1197

break;

1198

1199

default:

1200

rtStatus = false;

1201

break;

1202

}

1203

1204

1205

if(ulRegRead != WriteData[i])

1206

{

1207

RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);

1208

rtStatus = false;

1209

break;

1210

}

1211

}

1212

1213

return rtStatus;

1214

}

1215

1216

#ifdef TO_DO_LIST

1217

void

1218

PHY_SetRFPowerState8192SUsb(

1219

struct net_device* dev,

1220

RF_POWER_STATE RFPowerState

1221

)

1222

{

1223

struct r8192_priv *priv = rtllib_priv(dev);

1224

bool WaitShutDown = false;

1225

u32 DWordContent;

1226

u8 eRFPath;

1227

BB_REGISTER_DEFINITION_T *pPhyReg;

1228

1229

if(priv->SetRFPowerStateInProgress == true)

1230

return;

1231

1232

priv->SetRFPowerStateInProgress = true;

1233

1234

1235

if(RFPowerState==RF_SHUT_DOWN)

1236

{

1237

RFPowerState=RF_OFF;

1238

WaitShutDown=true;

1239

}

1240

1241

1242

priv->RFPowerState = RFPowerState;

1243

switch( priv->rf_chip )

1244

{

1245

case RF_8225:

1246

case RF_6052:

1247

switch( RFPowerState )

1248

{

1249

case RF_ON:

1250

break;

1251

1252

case RF_SLEEP:

1253

break;

1254

1255

case RF_OFF:

1256

break;

1257

}

1258

break;

1259

1260

case RF_8256:

1261

switch( RFPowerState )

1262

{

1263

case RF_ON:

1264

break;

1265

1266

case RF_SLEEP:

1267

break;

1268

1269

case RF_OFF:

1270

for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)

1271

{

1272

if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))

1273

continue;

1274

1275

pPhyReg = &priv->PHYRegDef[eRFPath];

1276

rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);

1277

rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);

1278

}

1279

break;

1280

}

1281

break;

1282

1283

case RF_8258:

1284

break;

1285

}

1286

1287

priv->SetRFPowerStateInProgress = false;

1288

}

1289

#endif

1290

1291

void PHY_GetHWRegOriginalValue(struct net_device* dev)

1292

{

1293

struct r8192_priv *priv = rtllib_priv(dev);

1294

#if 0

1295

priv->MCSTxPowerLevelOriginalOffset[0] =

1296

rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);

1297

priv->MCSTxPowerLevelOriginalOffset[1] =

1298

rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);

1299

priv->MCSTxPowerLevelOriginalOffset[2] =

1300

rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);

1301

priv->MCSTxPowerLevelOriginalOffset[3] =

1302

rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);

1303

priv->MCSTxPowerLevelOriginalOffset[4] =

1304

rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);

1305

priv->MCSTxPowerLevelOriginalOffset[5] =

1306

rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);

1307

1308

priv->CCKTxPowerLevelOriginalOffset=

1309

rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);

1310

RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",

1311

priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,

1312

priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,

1313

priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );

1314

#endif

1315

1316

priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);

1317

priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);

1318

priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);

1319

priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);

1320

RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",

1321

priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],

1322

priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);

1323

1324

priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);

1325

priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);

1326

RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",

1327

rOFDM0_RxDetector3, priv->framesync);

1328

1329

}

1330

1331

1332

1333

static void phy_InitBBRFRegisterDefinition( struct net_device* dev)

1334

{

1335

struct r8192_priv *priv = rtllib_priv(dev);

1336

1337

priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;

1338

priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;

1339

priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;

1340

priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;

1341

1342

priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;

1343

priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;

1344

priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;

1345

priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;

1346

1347

priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;

1348

priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;

1349

priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;

1350

priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;

1351

1352

priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;

1353

priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;

1354

priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;

1355

priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;

1356

1357

priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;

1358

priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;

1359

priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;

1360

priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;

1361

1362

priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;

1363

priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;

1364

priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;

1365

priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;

1366

1367

priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;

1368

priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;

1369

priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;

1370

priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;

1371

1372

priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;

1373

priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;

1374

priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;

1375

priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;

1376

1377

priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;

1378

priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;

1379

priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;

1380

priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;

1381

1382

priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;

1383

priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;

1384

priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;

1385

priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;

1386

1387

priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;

1388

priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;

1389

priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;

1390

priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;

1391

1392

priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;

1393

priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;

1394

priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;

1395

priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;

1396

1397

priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;

1398

priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;

1399

priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;

1400

priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;

1401

1402

priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;

1403

priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;

1404

priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;

1405

priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;

1406

1407

priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;

1408

priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;

1409

priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;

1410

priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;

1411

1412

priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;

1413

priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;

1414

priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;

1415

priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;

1416

1417

priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;

1418

priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;

1419

priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;

1420

priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;

1421

1422

priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;

1423

priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;

1424

1425

}

1426

1427

1428

bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)

1429

{

1430

struct r8192_priv *priv = rtllib_priv(dev);

1431

bool bResult = false;

1432

1433

RT_TRACE((COMP_PS | COMP_RF), "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);

1434

1435

if(eRFPowerState == priv->rtllib->eRFPowerState)

1436

{

1437

;

1438

return bResult;

1439

}

1440

1441

bResult = phy_SetRFPowerState8192SE(dev, eRFPowerState);

1442

1443

RT_TRACE((COMP_PS | COMP_RF), "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);

1444

1445

return bResult;

1446

}

1447

1448

static bool phy_SetRFPowerState8192SE(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)

1449

{

1450

struct r8192_priv *priv = rtllib_priv(dev);

1451

PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));

1452

bool bResult = true;

1453

u8 i, QueueID;

1454

struct rtl8192_tx_ring *ring = NULL;

1455

priv->SetRFPowerStateInProgress = true;

1456

1457

switch(priv->rf_chip )

1458

{

1459

default:

1460

switch( eRFPowerState )

1461

{

1462

case eRfOn:

1463

RT_TRACE(COMP_PS,"========>%s():eRfOn\n", __func__);

1464

{

1465

if((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))

1466

{

1467

bool rtstatus = true;

1468

u32 InitializeCount = 0;

1469

1470

{

1471

InitializeCount++;

1472

rtstatus = NicIFEnableNIC(dev);

1473

}while( (rtstatus != true) &&(InitializeCount < 10) );

1474

if(rtstatus != true)

1475

{

1476

RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__);

1477

priv->SetRFPowerStateInProgress = false;

1478

return false;

1479

}

1480

RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);

1481

}

1482

else

1483

{

1484

write_nic_word(dev, CMDR, 0x37FC);

1485

write_nic_byte(dev, TXPAUSE, 0x00);

1486

write_nic_byte(dev, PHY_CCA, 0x3);

1487

}

1488

1489

#if 1

1490

if(priv->rtllib->state == RTLLIB_LINKED)

1491

{

1492

LedControl8192SE(dev, LED_CTL_LINK);

1493

}

1494

else

1495

{

1496

LedControl8192SE(dev, LED_CTL_NO_LINK);

1497

}

1498

#endif

1499

}

1500

break;

1501

case eRfOff:

1502

RT_TRACE(COMP_PS,"========>%s():eRfOff\n", __func__);

1503

{

1504

for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )

1505

{

1506

if(QueueID == 5)

1507

{

1508

QueueID++;

1509

continue;

1510

}

1511

1512

ring = &priv->tx_ring[QueueID];

1513

if(skb_queue_len(&ring->queue) == 0)

1514

{

1515

QueueID++;

1516

continue;

1517

}

1518

#ifdef TO_DO_LIST

1519

#if( DEV_BUS_TYPE==PCI_INTERFACE)

1520

else if(IsLowPowerState(Adapter))

1521

{

1522

RT_TRACE(COMP_PS, DBG_LOUD,

1523

("eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID));

1524

break;

1525

}

1526

#endif

1527

#endif

1528

else

1529

{

1530

RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);

1531

udelay(10);

1532

i++;

1533

}

1534

1535

if(i >= MAX_DOZE_WAITING_TIMES_9x)

1536

{

1537

RT_TRACE(COMP_PS, "\n\n\n %s(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", __FUNCTION__,MAX_DOZE_WAITING_TIMES_9x, QueueID);

1538

break;

1539

}

1540

}

1541

1542

if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))

1543

{

1544

NicIFDisableNIC(dev);

1545

RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);

1546

if(priv->pwrdown && priv->rtllib->RfOffReason>= RF_CHANGE_BY_HW)

1547

write_nic_byte(dev,0x03,0x31);

1548

}

1549

else if(!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))

1550

{

1551

SET_RTL8192SE_RF_SLEEP(dev);

1552

1553

#if 1

1554

if(priv->rtllib->RfOffReason == RF_CHANGE_BY_IPS )

1555

{

1556

LedControl8192SE(dev,LED_CTL_NO_LINK);

1557

}

1558

else

1559

{

1560

LedControl8192SE(dev, LED_CTL_POWER_OFF);

1561

}

1562

#endif

1563

}

1564

}

1565

break;

1566

1567

case eRfSleep:

1568

RT_TRACE(COMP_PS,"========>%s():eRfSleep\n", __func__);

1569

{

1570

if(priv->rtllib->eRFPowerState == eRfOff)

1571

break;

1572

1573

for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )

1574

{

1575

ring = &priv->tx_ring[QueueID];

1576

if(skb_queue_len(&ring->queue) == 0)

1577

{

1578

QueueID++;

1579

continue;

1580

}

1581

#ifdef TO_DO_LIST

1582

#if( DEV_BUS_TYPE==PCI_INTERFACE)

1583

else if(IsLowPowerState(Adapter))

1584

{

1585

RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID);

1586

break;

1587

}

1588

#endif

1589

#endif

1590

else

1591

{

1592

RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);

1593

udelay(10);

1594

i++;

1595

}

1596

1597

if(i >= MAX_DOZE_WAITING_TIMES_9x)

1598

{

1599

RT_TRACE(COMP_PS, "\n\n\n %s(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", __FUNCTION__,MAX_DOZE_WAITING_TIMES_9x, QueueID);

1600

break;

1601

}

1602

}

1603

1604

SET_RTL8192SE_RF_SLEEP(dev);

1605

}

1606

break;

1607

1608

default:

1609

bResult = false;

1610

RT_TRACE(COMP_ERR, "phy_SetRFPowerState8192S(): unknow state to set: 0x%X!!!\n", eRFPowerState);

1611

break;

1612

}

1613

break;

1614

}

1615

1616

if(bResult)

1617

{

1618

priv->rtllib->eRFPowerState = eRFPowerState;

1619

}

1620

1621

priv->SetRFPowerStateInProgress = false;

1622

1623

return bResult;

1624

}

1625

1626

1627

void

1628

PHY_SwitchEphyParameter(struct net_device* dev)

1629

{

1630

struct r8192_priv *priv = rtllib_priv(dev);

1631

1632

write_nic_dword(dev, 0x540, 0x73c11);

1633

write_nic_dword(dev, 0x548, 0x2407c);

1634

1635

write_nic_word(dev, 0x550, 0x1000);

1636

write_nic_byte(dev, 0x554, 0x20);

1637

phy_CheckEphySwitchReady(dev);

1638

1639

write_nic_word(dev, 0x550, 0xa0eb);

1640

write_nic_byte(dev, 0x554, 0x3e);

1641

phy_CheckEphySwitchReady(dev);

1642

1643

write_nic_word(dev, 0x550, 0xff80);

1644

write_nic_byte(dev, 0x554, 0x39);

1645

phy_CheckEphySwitchReady(dev);

1646

1647

if(priv->bSupportASPM && !priv->bSupportBackDoor)

1648

write_nic_byte(dev, 0x560, 0x40);

1649

else

1650

{

1651

write_nic_byte(dev, 0x560, 0x00);

1652

1653

if (priv->CustomerID == RT_CID_819x_SAMSUNG ||

1654

priv->CustomerID == RT_CID_819x_Lenovo)

1655

{

1656

if (priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_AMD ||

1657

priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_ATI)

1658

{

1659

write_nic_byte(dev, 0x560, 0x40);

1660

}

1661

}

1662

}

1663

1664

}

1665

1666

1667

void

1668

PHY_GetTxPowerLevel8192S(

1669

struct net_device* dev,

1670

long* powerlevel

1671

)

1672

{

1673

struct r8192_priv *priv = rtllib_priv(dev);

1674

u8 TxPwrLevel = 0;

1675

long TxPwrDbm;

1676

1677

TxPwrLevel = priv->CurrentCckTxPwrIdx;

1678

TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);

1679

1680

TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;

1681

1682

if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)

1683

TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);

1684

TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;

1685

1686

if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)

1687

TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);

1688

*powerlevel = TxPwrDbm;

1689

}

1690

1691

#if 1

1692

void getTxPowerIndex(

1693

struct net_device* dev,

1694

u8 channel,

1695

u8* cckPowerLevel,

1696

u8* ofdmPowerLevel

1697

)

1698

{

1699

struct r8192_priv *priv = rtllib_priv(dev);

1700

u8 index = (channel -1);

1701

cckPowerLevel[0] = priv->RfTxPwrLevelCck[0][index];

1702

cckPowerLevel[1] = priv->RfTxPwrLevelCck[1][index];

1703

1704

if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)

1705

{

1706

ofdmPowerLevel[0] = priv->RfTxPwrLevelOfdm1T[0][index];

1707

ofdmPowerLevel[1] = priv->RfTxPwrLevelOfdm1T[1][index];

1708

}

1709

else if (priv->rf_type == RF_2T2R)

1710

{

1711

ofdmPowerLevel[0] = priv->RfTxPwrLevelOfdm2T[0][index];

1712

ofdmPowerLevel[1] = priv->RfTxPwrLevelOfdm2T[1][index];

1713

}

1714

RT_TRACE(COMP_POWER,"Channel-%d, set tx power index !!\n", channel);

1715

}

1716

1717

void ccxPowerIndexCheck(

1718

struct net_device* dev,

1719

u8 channel,

1720

u8* cckPowerLevel,

1721

u8* ofdmPowerLevel

1722

)

1723

{

1724

struct r8192_priv *priv = rtllib_priv(dev);

1725

1726

#ifdef TODO

1727

if( priv->rtllib->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&

1728

channel == priv->rtllib->current_network.channel)

1729

{

1730

u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);

1731

u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);

1732

u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);

1733

1734

RT_TRACE(COMP_TXAGC,

1735

"CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",

1736

priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx);

1737

RT_TRACE(COMP_TXAGC,

1738

"EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",

1739

channel, cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);

1740

1741

if(cckPowerLevel[0] > CckCellPwrIdx)

1742

cckPowerLevel[0] = CckCellPwrIdx;

1743

if(ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)

1744

{

1745

if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)

1746

{

1747

ofdmPowerLevel[0] = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;

1748

}

1749

else

1750

{

1751

ofdmPowerLevel[0] = 0;

1752

}

1753

}

1754

1755

RT_TRACE(COMP_TXAGC,

1756

"Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",

1757

cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);

1758

}

1759

1760

#endif

1761

priv->CurrentCckTxPwrIdx = cckPowerLevel[0];

1762

priv->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];

1763

1764

RT_TRACE(COMP_TXAGC,

1765

"PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",

1766

cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);

1767

1768

}

1769

/*-----------------------------------------------------------------------------

1770

* Function: SetTxPowerLevel8190()

1771

1772

* Overview: This function is export to "HalCommon" moudule

1773

* We must consider RF path later!!!!!!!

1774

1775

* Input: PADAPTER Adapter

1776

* u1Byte channel

1777

1778

* Output: NONE

1779

1780

* Return: NONE

1781

* 2008/11/04 MHC We remove EEPROM_93C56.

1782

* We need to move CCX relative code to independet file.

1783

* 2009/01/21 MHC Support new EEPROM format from SD3 requirement.

1784

1785

*---------------------------------------------------------------------------*/

1786

void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)

1787

{

1788

struct r8192_priv *priv = rtllib_priv(dev);

1789

u8 cckPowerLevel[2], ofdmPowerLevel[2];

1790

1791

if(priv->bTXPowerDataReadFromEEPORM == false)

1792

return;

1793

getTxPowerIndex(dev, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);

1794

RT_TRACE(COMP_POWER, "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",

1795

channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]);

1796

1797

ccxPowerIndexCheck(dev, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);

1798

1799

switch(priv->rf_chip)

1800

{

1801

case RF_8225:

1802

break;

1803

1804

case RF_8256:

1805

;

1806

break;

1807

1808

case RF_6052:

1809

PHY_RF6052SetCckTxPower(dev, cckPowerLevel[0]);

1810

PHY_RF6052SetOFDMTxPower(dev, &ofdmPowerLevel[0], channel);

1811

break;

1812

1813

case RF_8258:

1814

break;

1815

default:

1816

break;

1817

}

1818

}

1819

#else

1820

void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)

1821

{

1822

struct r8192_priv *priv = rtllib_priv(dev);

1823

u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;

1824

s8 ant_pwr_diff = 0;

1825

u32 u4RegValue;

1826

u8 index = (channel -1);

1827

u8 pwrdiff[2] = {0};

1828

u8 ht20pwr[2] = {0}, ht40pwr[2] = {0};

1829

u8 rfpath = 0, rfpathnum = 2;

1830

1831

if(priv->bTXPowerDataReadFromEEPORM == false)

1832

return;

1833

1834

1835

powerlevel = priv->RfTxPwrLevelCck[0][index];

1836

1837

if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)

1838

{

1839

powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];

1840

1841

1842

rfpathnum = 1;

1843

ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];

1844

}

1845

else if (priv->rf_type == RF_2T2R)

1846

{

1847

powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];

1848

ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] -

1849

priv->RfTxPwrLevelOfdm2T[0][index];

1850

1851

RT_TRACE(COMP_POWER, "CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",

1852

channel, priv->RfTxPwrLevelOfdm2T[0][index],

1853

priv->RfTxPwrLevelOfdm2T[1][index],

1854

priv->RfTxPwrLevelOfdm2T[0][index],

1855

priv->RfTxPwrLevelOfdm2T[1][index]);

1856

1857

ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];

1858

ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];

1859

}

1860

RT_TRACE(COMP_POWER, "Channel-%d, set tx power index\n", channel);

1861

1862

if (priv->eeprom_version >= 2)

1863

{

1864

if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)

1865

{

1866

for (rfpath = 0; rfpath < rfpathnum; rfpath++)

1867

{

1868

pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];

1869

1870

if (pwrdiff[rfpath] < 8)

1871

{

1872

ht20pwr[rfpath] += pwrdiff[rfpath];

1873

}

1874

else

1875

{

1876

ht20pwr[rfpath] -= (16-pwrdiff[rfpath]);

1877

}

1878

}

1879

1880

if (priv->rf_type == RF_2T2R)

1881

ant_pwr_diff = ht20pwr[1] - ht20pwr[0];

1882

1883

RT_TRACE(COMP_POWER, "HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",

1884

pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]);

1885

}

1886

}

1887

1888

if(ant_pwr_diff > 7)

1889

ant_pwr_diff = 7;

1890

if(ant_pwr_diff < -8)

1891

ant_pwr_diff = -8;

1892

1893

RT_TRACE(COMP_POWER, "CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",

1894

powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff);

1895

1896

ant_pwr_diff &= 0xf;

1897

1898

priv->AntennaTxPwDiff[2] = 0;

1899

priv->AntennaTxPwDiff[1] = 0;

1900

priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);

1901

RT_TRACE(COMP_POWER, "pHalData->AntennaTxPwDiff[0]/[1]/[2] = 0x%x/0x%x/0x%x\n",

1902

priv->AntennaTxPwDiff[0], priv->AntennaTxPwDiff[1], priv->AntennaTxPwDiff[2]);

1903

u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |

1904

priv->AntennaTxPwDiff[1]<<4 |

1905

priv->AntennaTxPwDiff[0] );

1906

RT_TRACE(COMP_POWER, "BCD-Diff=0x%x\n", u4RegValue);

1907

1908

rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);

1909

1910

#ifdef TODO

1911

if( priv->rtllib->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&

1912

channel == priv->rtllib->current_network.channel)

1913

{

1914

u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);

1915

u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);

1916

u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);

1917

1918

RT_TRACE(COMP_TXAGC,

1919

("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",

1920

priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));

1921

RT_TRACE(COMP_TXAGC,

1922

("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",

1923

channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));

1924

1925

if(powerlevel > CckCellPwrIdx)

1926

powerlevel = CckCellPwrIdx;

1927

if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)

1928

{

1929

if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)

1930

{

1931

powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;

1932

}

1933

else

1934

{

1935

powerlevelOFDM24G = 0;

1936

}

1937

}

1938

1939

RT_TRACE(COMP_TXAGC,

1940

("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",

1941

powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));

1942

}

1943

#endif

1944

priv->CurrentCckTxPwrIdx = powerlevel;

1945

priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;

1946

1947

RT_TRACE(COMP_POWER, "PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",

1948

powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G);

1949

1950

switch(priv->rf_chip)

1951

{

1952

case RF_8225:

1953

break;

1954

1955

case RF_8256:

1956

break;

1957

1958

case RF_6052:

1959

PHY_RF6052SetCckTxPower(dev, powerlevel);

1960

PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G, channel);

1961

break;

1962

1963

case RF_8258:

1964

break;

1965

default:

1966

break;

1967

}

1968

1969

}

1970

#endif

1971

1972

bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)

1973

{

1974

struct r8192_priv *priv = rtllib_priv(dev);

1975

u8 idx;

1976

u8 rf_path;

1977

1978

u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);

1979

u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);

1980

1981

if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)

1982

OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;

1983

else

1984

OfdmTxPwrIdx = 0;

1985

1986

RT_TRACE(COMP_POWER, "PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx);

1987

1988

for(idx = 0; idx < 14; idx++)

1989

{

1990

priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;

1991

priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;

1992

priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;

1993

priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;

1994

priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;

1995

priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;

1996

for (rf_path = 0; rf_path < 2; rf_path++)

1997

{

1998

priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;

1999

priv->RfTxPwrLevelOfdm1T[rf_path][idx] =

2000

priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;

2001

}

2002

}

2003

2004

rtl8192_phy_setTxPower(dev, priv->chan);

2005

2006

return true;

2007

}

2008

2009

extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)

2010

{

2011

struct r8192_priv *priv = rtllib_priv(dev);

2012

u32 NewBeaconNum;

2013

2014

if(priv->pFirmware->FirmwareVersion >= 0x33)

2015

{

2016

write_nic_dword(dev,WFM5,0xF1000000|(BeaconInterval<<8));

2017

}

2018

else

2019

{

2020

NewBeaconNum = BeaconInterval *32 - 64;

2021

write_nic_dword(dev, WFM3+4, NewBeaconNum);

2022

write_nic_dword(dev, WFM3, 0xB026007C);

2023

}

2024

}

2025

2026

static u8 phy_DbmToTxPwrIdx(

2027

struct net_device* dev,

2028

WIRELESS_MODE WirelessMode,

2029

long PowerInDbm

2030

)

2031

{

2032

u8 TxPwrIdx = 0;

2033

long Offset = 0;

2034

2035

2036

switch(WirelessMode)

2037

{

2038

case WIRELESS_MODE_B:

2039

Offset = -7;

2040

break;

2041

2042

case WIRELESS_MODE_G:

2043

Offset = -8;

2044

break;

2045

2046

case WIRELESS_MODE_N_24G:

2047

default:

2048

Offset = -8;

2049

break;

2050

}

2051

2052

if((PowerInDbm - Offset) > 0)

2053

{

2054

TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);

2055

}

2056

else

2057

{

2058

TxPwrIdx = 0;

2059

}

2060

2061

if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)

2062

TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;

2063

2064

return TxPwrIdx;

2065

}

2066

2067

static long phy_TxPwrIdxToDbm(

2068

struct net_device* dev,

2069

WIRELESS_MODE WirelessMode,

2070

u8 TxPwrIdx

2071

)

2072

{

2073

long Offset = 0;

2074

long PwrOutDbm = 0;

2075

2076

switch(WirelessMode)

2077

{

2078

case WIRELESS_MODE_B:

2079

Offset = -7;

2080

break;

2081

2082

case WIRELESS_MODE_G:

2083

case WIRELESS_MODE_N_24G:

2084

Offset = -8;

2085

break;

2086

default:

2087

Offset = -8;

2088

break;

2089

}

2090

2091

PwrOutDbm = TxPwrIdx / 2 + Offset;

2092

2093

return PwrOutDbm;

2094

}

2095

2096

extern void

2097

PHY_ScanOperationBackup8192S(

2098

struct net_device* dev,

2099

u8 Operation

2100

)

2101

{

2102

#if(RTL8192S_DISABLE_FW_DM == 0)

2103

2104

struct r8192_priv *priv = rtllib_priv(dev);

2105

2106

if(priv->up)

2107

{

2108

switch(Operation)

2109

{

2110

case SCAN_OPT_BACKUP:

2111

priv->rtllib->SetFwCmdHandler(dev, FW_CMD_PAUSE_DM_BY_SCAN);

2112

break;

2113

2114

case SCAN_OPT_RESTORE:

2115

priv->rtllib->SetFwCmdHandler(dev, FW_CMD_RESUME_DM_BY_SCAN);

2116

break;

2117

2118

default:

2119

RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation. \n");

2120

break;

2121

}

2122

}

2123

#endif

2124

}

2125

2126

void PHY_SetBWModeCallback8192S(struct net_device *dev)

2127

{

2128

struct r8192_priv *priv = rtllib_priv(dev);

2129

u8 regBwOpMode, regRRSR_RSC;

2130

2131

2132

2133

RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8192s() Switch to %s bandwidth\n", \

2134

priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");

2135

2136

if(priv->rf_chip == RF_PSEUDO_11N)

2137

{

2138

priv->SetBWModeInProgress= false;

2139

return;

2140

}

2141

if(IS_NIC_DOWN(priv)){

2142

priv->SwChnlInProgress = priv->SetBWModeInProgress = false;

2143

return;

2144

}

2145

2146

regBwOpMode = read_nic_byte(dev, BW_OPMODE);

2147

regRRSR_RSC = read_nic_byte(dev, RRSR+2);

2148

2149

switch(priv->CurrentChannelBW)

2150

{

2151

case HT_CHANNEL_WIDTH_20:

2152

regBwOpMode |= BW_OPMODE_20MHZ;

2153

write_nic_byte(dev, BW_OPMODE, regBwOpMode);

2154

break;

2155

2156

case HT_CHANNEL_WIDTH_20_40:

2157

regBwOpMode &= ~BW_OPMODE_20MHZ;

2158

write_nic_byte(dev, BW_OPMODE, regBwOpMode);

2159

2160

break;

2161

2162

default:

2163

RT_TRACE(COMP_DBG, "SetBWModeCallback8192s():\

2164

unknown Bandwidth: %#X\n",priv->CurrentChannelBW);

2165

break;

2166

}

2167

2168

switch(priv->CurrentChannelBW)

2169

{

2170

case HT_CHANNEL_WIDTH_20:

2171

rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);

2172

rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);

2173

2174

if(priv->card_8192_version >= VERSION_8192S_BCUT)

2175

write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);

2176

break;

2177

2178

case HT_CHANNEL_WIDTH_20_40:

2179

rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);

2180

rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);

2181

2182

2183

rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));

2184

rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);

2185

2186

if(priv->card_8192_version >= VERSION_8192S_BCUT)

2187

write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);

2188

break;

2189

2190

default:

2191

RT_TRACE(COMP_DBG, "SetBWModeCallback8192s(): unknown Bandwidth: %#X\n"\

2192

,priv->CurrentChannelBW);

2193

break;

2194

2195

}

2196

2197

2198

switch( priv->rf_chip )

2199

{

2200

case RF_8225:

2201

break;

2202

2203

case RF_8256:

2204

break;

2205

2206

case RF_8258:

2207

break;

2208

2209

case RF_PSEUDO_11N:

2210

break;

2211

2212

case RF_6052:

2213

PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);

2214

break;

2215

default:

2216

printk("Unknown rf_chip: %d\n", priv->rf_chip);

2217

break;

2218

}

2219

2220

priv->SetBWModeInProgress= false;

2221

2222

RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8192s() \n" );

2223

}

2224

2225

2226

void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)

2227

{

2228

struct r8192_priv *priv = rtllib_priv(dev);

2229

2230

2231

2232

2233

2234

if(priv->SetBWModeInProgress)

2235

return;

2236

2237

priv->SetBWModeInProgress= true;

2238

2239

priv->CurrentChannelBW = Bandwidth;

2240

2241

if(Offset==HT_EXTCHNL_OFFSET_LOWER)

2242

priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;

2243

else if(Offset==HT_EXTCHNL_OFFSET_UPPER)

2244

priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;

2245

else

2246

priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;

2247

2248

#if 0

2249

if(!priv->bDriverStopped)

2250

{

2251

#ifdef USE_WORKITEM

2252

PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));

2253

#else

2254

PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);

2255

#endif

2256

}

2257

#endif

2258

if(!IS_NIC_DOWN(priv)){

2259

PHY_SetBWModeCallback8192S(dev);

2260

} else {

2261

priv->SetBWModeInProgress= false;

2262

}

2263

}

2264

2265

void PHY_SwChnlCallback8192S(struct net_device *dev)

2266

{

2267

2268

struct r8192_priv *priv = rtllib_priv(dev);

2269

u32 delay;

2270

2271

RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);

2272

2273

if(IS_NIC_DOWN(priv))

2274

{

2275

printk("%s: driver is not up\n", __FUNCTION__);

2276

priv->SwChnlInProgress = priv->SetBWModeInProgress = false;

2277

return;

2278

}

2279

if(priv->rf_chip == RF_PSEUDO_11N)

2280

{

2281

printk("%s: rt chip is RF_PSEUDO_11N\n", __FUNCTION__);

2282

priv->SwChnlInProgress=false;

2283

return;

2284

}

2285

2286

do{

2287

if(!priv->SwChnlInProgress)

2288

break;

2289

2290

if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))

2291

{

2292

if(delay>0)

2293

{

2294

mdelay(delay);

2295

}

2296

else

2297

continue;

2298

}

2299

else

2300

{

2301

priv->SwChnlInProgress=false;

2302

break;

2303

}

2304

}while(true);

2305

}

2306

2307

u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)

2308

{

2309

struct r8192_priv *priv = rtllib_priv(dev);

2310

2311

if(IS_NIC_DOWN(priv))

2312

{

2313

printk("%s: driver is not up.\n",__FUNCTION__);

2314

priv->SwChnlInProgress = priv->SetBWModeInProgress = false;

2315

return false;

2316

}

2317

if(priv->SwChnlInProgress){

2318

printk("%s: SwChnl is in progress\n",__FUNCTION__);

2319

return false;

2320

}

2321

2322

if(priv->SetBWModeInProgress){

2323

printk("%s: Set BWMode is in progress\n",__FUNCTION__);

2324

return false;

2325

}

2326

if (0)

2327

{

2328

u8 path;

2329

for(path=0; path<2; path++){

2330

printk("============>to set channel:%x\n", rtl8192_phy_QueryRFReg(dev, path, 0x18, 0x3ff));

2331

udelay(10);

2332

}

2333

}

2334

switch(priv->rtllib->mode)

2335

{

2336

case WIRELESS_MODE_A:

2337

case WIRELESS_MODE_N_5G:

2338

if (channel<=14){

2339

RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");

2340

return false;

2341

}

2342

break;

2343

2344

case WIRELESS_MODE_B:

2345

if (channel>14){

2346

RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");

2347

return false;

2348

}

2349

break;

2350

2351

case WIRELESS_MODE_G:

2352

case WIRELESS_MODE_N_24G:

2353

if (channel>14){

2354

RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");

2355

return false;

2356

}

2357

break;

2358

2359

default:

2360

break;

2361

}

2362

2363

priv->SwChnlInProgress = true;

2364

if( channel == 0)

2365

channel = 1;

2366

2367

priv->chan=channel;

2368

2369

priv->SwChnlStage=0;

2370

priv->SwChnlStep=0;

2371

2372

#if 0

2373

if(!dev->bDriverStopped)

2374

{

2375

#ifdef USE_WORKITEM

2376

PlatformScheduleWorkItem(&(priv->SwChnlWorkItem));

2377

#else

2378

PlatformSetTimer(dev, &(priv->SwChnlTimer), 0);

2379

#endif

2380

}

2381

#endif

2382

2383

if(!IS_NIC_DOWN(priv)){

2384

PHY_SwChnlCallback8192S(dev);

2385

} else {

2386

priv->SwChnlInProgress = false;

2387

}

2388

return true;

2389

}

2390

2391

2392

void PHY_SwChnlPhy8192S(

2393

struct net_device* dev,

2394

u8 channel

2395

)

2396

{

2397

struct r8192_priv *priv = rtllib_priv(dev);

2398

2399

RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);

2400

2401

#ifdef TO_DO_LIST

2402

if(RT_CANNOT_IO(dev))

2403

return;

2404

#endif

2405

2406

if(priv->SwChnlInProgress)

2407

return;

2408

2409

if(priv->rf_chip == RF_PSEUDO_11N)

2410

{

2411

priv->SwChnlInProgress=false;

2412

return;

2413

}

2414

2415

priv->SwChnlInProgress = true;

2416

if( channel == 0)

2417

channel = 1;

2418

2419

priv->chan=channel;

2420

2421

priv->SwChnlStage = 0;

2422

priv->SwChnlStep = 0;

2423

2424

phy_FinishSwChnlNow(dev,channel);

2425

2426

priv->SwChnlInProgress = false;

2427

}

2428

2429

static bool

2430

phy_SwChnlStepByStep(

2431

struct net_device* dev,

2432

u8 channel,

2433

u8 *stage,

2434

u8 *step,

2435

u32 *delay

2436

)

2437

{

2438

struct r8192_priv *priv = rtllib_priv(dev);

2439

SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];

2440

u32 PreCommonCmdCnt;

2441

SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];

2442

u32 PostCommonCmdCnt;

2443

SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];

2444

u32 RfDependCmdCnt;

2445

SwChnlCmd *CurrentCmd = NULL;

2446

u8 eRFPath;

2447

u16 u2Channel = 0;

2448

2449

RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);

2450

if (!IsLegalChannel(priv->rtllib, channel))

2451

{

2452

RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);

2453

return true;

2454

}

2455

2456

2457

PreCommonCmdCnt = 0;

2458

phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,

2459

CmdID_SetTxPowerLevel, 0, 0, 0);

2460

phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,

2461

CmdID_End, 0, 0, 0);

2462

2463

PostCommonCmdCnt = 0;

2464

2465

phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,

2466

CmdID_End, 0, 0, 0);

2467

2468

RfDependCmdCnt = 0;

2469

switch( priv->rf_chip )

2470

{

2471

case RF_8225:

2472

if (channel < 1 || channel > 14)

2473

RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);

2474

phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

2475

CmdID_RF_WriteReg, rRfChannel, channel, 10);

2476

phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

2477

CmdID_End, 0, 0, 0);

2478

break;

2479

2480

case RF_8256:

2481

if (channel < 1 || channel > 14)

2482

RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);

2483

phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

2484

CmdID_RF_WriteReg, rRfChannel, channel, 10);

2485

phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

2486

CmdID_End, 0, 0, 0);

2487

break;

2488

2489

case RF_6052:

2490

if (channel < 1 || channel > 14)

2491

RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);

2492

2493

u2Channel = channel;

2494

2495

switch(priv->CurrentChannelBW)

2496

{

2497

case HT_CHANNEL_WIDTH_20:

2498

u2Channel |= BIT10;

2499

break;

2500

2501

case HT_CHANNEL_WIDTH_20_40:

2502

u2Channel &= ~BIT10;

2503

break;

2504

default:

2505

u2Channel |= BIT10;

2506

break;

2507

}

2508

u2Channel |= BIT12|BIT13|BIT14;

2509

2510

phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

2511

CmdID_RF_WriteReg, RF_CHNLBW, u2Channel, 10);

2512

phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

2513

CmdID_End, 0, 0, 0);

2514

break;

2515

2516

case RF_8258:

2517

break;

2518

2519

default:

2520

return false;

2521

break;

2522

}

2523

2524

2525

do{

2526

switch(*stage)

2527

{

2528

case 0:

2529

CurrentCmd=&PreCommonCmd[*step];

2530

break;

2531

case 1:

2532

CurrentCmd=&RfDependCmd[*step];

2533

break;

2534

case 2:

2535

CurrentCmd=&PostCommonCmd[*step];

2536

break;

2537

}

2538

2539

if(CurrentCmd->CmdID==CmdID_End)

2540

{

2541

if((*stage)==2)

2542

{

2543

return true;

2544

}

2545

else

2546

{

2547

(*stage)++;

2548

(*step)=0;

2549

continue;

2550

}

2551

}

2552

2553

switch(CurrentCmd->CmdID)

2554

{

2555

case CmdID_SetTxPowerLevel:

2556

#ifndef CONFIG_MP

2557

rtl8192_phy_setTxPower(dev,channel);

2558

#endif

2559

break;

2560

case CmdID_WritePortUlong:

2561

write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);

2562

break;

2563

case CmdID_WritePortUshort:

2564

write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);

2565

break;

2566

case CmdID_WritePortUchar:

2567

write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);

2568

break;

2569

case CmdID_RF_WriteReg:

2570

for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)

2571

{

2572

if (IS_HARDWARE_TYPE_8192SE(dev)) {

2573

#ifdef CONFIG_FW_SETCHAN

2574

u32 rf_bw = ((priv->RfRegChnlVal[eRFPath] & 0xfffffc00) | (CurrentCmd->Para2 & 0xFF00));

2575

#endif

2576

priv->RfRegChnlVal[eRFPath] = ((priv->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);

2577

2578

#ifdef CONFIG_FW_SETCHAN

2579

rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, rf_bw);

2580

#else

2581

rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, priv->RfRegChnlVal[eRFPath]);

2582

#endif

2583

} else {

2584

rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));

2585

}

2586

}

2587

break;

2588

default:

2589

break;

2590

}

2591

2592

break;

2593

}while(true);

2594

2595

(*delay)=CurrentCmd->msDelay;

2596

(*step)++;

2597

RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);

2598

return false;

2599

}

2600

2601

static bool

2602

phy_SetSwChnlCmdArray(

2603

SwChnlCmd* CmdTable,

2604

u32 CmdTableIdx,

2605

u32 CmdTableSz,

2606

SwChnlCmdID CmdID,

2607

u32 Para1,

2608

u32 Para2,

2609

u32 msDelay

2610

)

2611

{

2612

SwChnlCmd* pCmd;

2613

2614

if(CmdTable == NULL)

2615

{

2616

return false;

2617

}

2618

if(CmdTableIdx >= CmdTableSz)

2619

{

2620

return false;

2621

}

2622

2623

pCmd = CmdTable + CmdTableIdx;

2624

pCmd->CmdID = CmdID;

2625

pCmd->Para1 = Para1;

2626

pCmd->Para2 = Para2;

2627

pCmd->msDelay = msDelay;

2628

2629

return true;

2630

}

2631

2632

static void

2633

phy_FinishSwChnlNow(

2634

struct net_device* dev,

2635

u8 channel

2636

)

2637

{

2638

struct r8192_priv *priv = rtllib_priv(dev);

2639

u32 delay;

2640

2641

while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))

2642

{

2643

if(delay>0)

2644

mdelay(delay);

2645

if(IS_NIC_DOWN(priv))

2646

break;

2647

}

2648

}

2649

2650

2651

u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)

2652

{

2653

bool rtValue = true;

2654

2655

#if 0

2656

if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)

2657

{

2658

rtValue = false;

2659

}

2660

if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)

2661

{

2662

2663

}

2664

#endif

2665

return rtValue;

2666

2667

} /* PHY_CheckIsLegalRfPath8192S */

2668

2669

2670

2671

void

2672

PHY_IQCalibrate( struct net_device* dev)

2673

{

2674

u32 i, reg;

2675

u32 old_value;

2676

long X, Y, TX0[4];

2677

u32 TXA[4];

2678

2679

2680

for (i = 0; i < 10; i++)

2681

{

2682

rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);

2683

udelay(5);

2684

rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);

2685

udelay(5);

2686

rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);

2687

udelay(5);

2688

rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);

2689

udelay(5);

2690

rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);

2691

udelay(5);

2692

rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);

2693

udelay(5);

2694

rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);

2695

udelay(5);

2696

rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);

2697

udelay(5);

2698

rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);

2699

udelay(5);

2700

rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);

2701

udelay(5);

2702

rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);

2703

udelay(2000);

2704

rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);

2705

udelay(5);

2706

rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);

2707

udelay(5);

2708

rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);

2709

2710

2711

reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);

2712

2713

if (!(reg&(BIT27|BIT28|BIT30|BIT31)))

2714

{

2715

old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);

2716

2717

X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;

2718

TXA[RF90_PATH_A] = (X * old_value)/0x100;

2719

reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);

2720

reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];

2721

rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);

2722

udelay(5);

2723

2724

Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;

2725

TX0[RF90_PATH_C] = ((Y * old_value)/0x100);

2726

reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);

2727

reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);

2728

rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);

2729

reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);

2730

reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);

2731

rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);

2732

udelay(5);

2733

2734

reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);

2735

X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;

2736

reg = (reg & 0xFFFFFC00) |X;

2737

rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);

2738

Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;

2739

reg = (reg & 0xFFFF03FF) |Y<<10;

2740

rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);

2741

udelay(5);

2742

old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);

2743

2744

X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;

2745

reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);

2746

TXA[RF90_PATH_A] = (X * old_value) / 0x100;

2747

reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];

2748

rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);

2749

udelay(5);

2750

2751

Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;

2752

TX0[RF90_PATH_C] = ((Y * old_value)/0x100);

2753

reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);

2754

reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);

2755

rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);

2756

reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);

2757

reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);

2758

rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);

2759

udelay(5);

2760

2761

reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);

2762

X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;

2763

reg = (reg & 0xFFFFFC00) |X;

2764

rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);

2765

2766

Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;

2767

reg = (reg & 0xFFFF03FF) |Y<<10;

2768

rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);

2769

udelay(5);

2770

2771

RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");

2772

break;

2773

}

2774

2775

}

2776

2777

2778

2779

2780

}

2781

2782

extern void PHY_IQCalibrateBcut(struct net_device* dev)

2783

{

2784

u32 i, reg;

2785

u32 old_value;

2786

long X, Y, TX0[4];

2787

u32 TXA[4];

2788

u32 calibrate_set[13] = {0};

2789

u32 load_value[13];

2790

u8 RfPiEnable=0;

2791

2792

2793

0xee0[31:0]=0x3fed92fb;

2794

0xedc[31:0] =0x3fed92fb;

2795

0xe70[31:0] =0x3fed92fb;

2796

0xe74[31:0] =0x3fed92fb;

2797

0xe78[31:0] =0x3fed92fb;

2798

0xe7c[31:0]= 0x3fed92fb;

2799

0xe80[31:0]= 0x3fed92fb;

2800

0xe84[31:0]= 0x3fed92fb;

2801

0xe88[31:0]= 0x3fed92fb;

2802

0xe8c[31:0]= 0x3fed92fb;

2803

0xed0[31:0]= 0x3fed92fb;

2804

0xed4[31:0]= 0x3fed92fb;

2805

0xed8[31:0]= 0x3fed92fb;

2806

2807

calibrate_set [0] = 0xee0;

2808

calibrate_set [1] = 0xedc;

2809

calibrate_set [2] = 0xe70;

2810

calibrate_set [3] = 0xe74;

2811

calibrate_set [4] = 0xe78;

2812

calibrate_set [5] = 0xe7c;

2813

calibrate_set [6] = 0xe80;

2814

calibrate_set [7] = 0xe84;

2815

calibrate_set [8] = 0xe88;

2816

calibrate_set [9] = 0xe8c;

2817

calibrate_set [10] = 0xed0;

2818

calibrate_set [11] = 0xed4;

2819

calibrate_set [12] = 0xed8;

2820

for (i = 0; i < 13; i++)

2821

{

2822

load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);

2823

rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);

2824

2825

}

2826

2827

RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);

2828

for (i = 0; i < 10; i++)

2829

{

2830

RT_TRACE(COMP_INIT, "IQK -%d\n", i);

2831

if (!RfPiEnable)

2832

{

2833

rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);

2834

rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);

2835

}

2836

2837

rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);

2838

udelay(5);

2839

rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);

2840

udelay(5);

2841

rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);

2842

udelay(5);

2843

rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);

2844

udelay(5);

2845

rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);

2846

udelay(5);

2847

rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);

2848

udelay(5);

2849

rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);

2850

udelay(5);

2851

rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);

2852

udelay(5);

2853

rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);

2854

udelay(5);

2855

rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);

2856

udelay(5);

2857

2858

udelay(2000);

2859

2860

rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);

2861

udelay(5);

2862

rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);

2863

udelay(5);

2864

rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);

2865

2866

udelay(2000);

2867

2868

rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);

2869

udelay(5);

2870

rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);

2871

udelay(5);

2872

rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);

2873

2874

if (!RfPiEnable)

2875

{

2876

rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);

2877

rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);

2878

}

2879

2880

2881

reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);

2882

2883

if (!(reg&(BIT27|BIT28|BIT30|BIT31)))

2884

{

2885

old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);

2886

2887

X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;

2888

TXA[RF90_PATH_A] = (X * old_value)/0x100;

2889

reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);

2890

reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];

2891

rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);

2892

udelay(5);

2893

2894

Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;

2895

TX0[RF90_PATH_C] = ((Y * old_value)/0x100);

2896

reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);

2897

reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);

2898

rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);

2899

reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);

2900

reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);

2901

rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);

2902

udelay(5);

2903

2904

reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);

2905

X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;

2906

reg = (reg & 0xFFFFFC00) |X;

2907

rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);

2908

Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;

2909

reg = (reg & 0xFFFF03FF) |Y<<10;

2910

rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);

2911

udelay(5);

2912

old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);

2913

2914

X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;

2915

reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);

2916

TXA[RF90_PATH_A] = (X * old_value) / 0x100;

2917

reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];

2918

rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);

2919

udelay(5);

2920

2921

Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;

2922

TX0[RF90_PATH_C] = ((Y * old_value)/0x100);

2923

reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);

2924

reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);

2925

rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);

2926

reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);

2927

reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);

2928

rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);

2929

udelay(5);

2930

2931

reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);

2932

X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;

2933

reg = (reg & 0xFFFFFC00) |X;

2934

rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);

2935

2936

Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;

2937

reg = (reg & 0xFFFF03FF) |Y<<10;

2938

rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);

2939

udelay(5);

2940

2941

RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");

2942

break;

2943

}

2944

2945

}

2946

2947

for (i = 0; i < 13; i++)

2948

rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);

2949

2950

2951

2952

2953

2954

}

2955

2956

#define HalGetFirmwareVerison(priv) (priv->pFirmware->FirmwareVersion )

2957

bool rtl8192se_set_fw_cmd(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO)

2958

{

2959

struct r8192_priv *priv = rtllib_priv(dev);

2960

u32 FwParam = FW_CMD_IO_PARA_QUERY(priv);

2961

u16 FwCmdMap = FW_CMD_IO_QUERY(priv);

2962

bool bPostProcessing = false;

2963

2964

RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%#x), SetFwCmdInProgress(%d)\n", FwCmdIO, priv->SetFwCmdInProgress);

2965

2966

2967

2968

2969

2970

RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%#x), SetFwCmdInProgress(%d)\n",

2971

FwCmdIO, priv->SetFwCmdInProgress);

2972

2973

do{

2974

2975

if(HalGetFirmwareVerison(priv) >= 0x35)

2976

{

2977

switch(FwCmdIO)

2978

{

2979

case FW_CMD_RA_REFRESH_N:

2980

FwCmdIO = FW_CMD_RA_REFRESH_N_COMB;

2981

break;

2982

case FW_CMD_RA_REFRESH_BG:

2983

FwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;

2984

break;

2985

default:

2986

break;

2987

}

2988

}

2989

else

2990

{

2991

if((FwCmdIO == FW_CMD_IQK_ENABLE) ||

2992

(FwCmdIO == FW_CMD_RA_REFRESH_N) ||

2993

(FwCmdIO == FW_CMD_RA_REFRESH_BG))

2994

{

2995

bPostProcessing = true;

2996

break;

2997

}

2998

}

2999

3000

if(HalGetFirmwareVerison(priv) >= 0x3E)

3001

{

3002

if(FwCmdIO == FW_CMD_CTRL_DM_BY_DRIVER)

3003

FwCmdIO = FW_CMD_CTRL_DM_BY_DRIVER_NEW;

3004

}

3005

3006

3007

switch(FwCmdIO)

3008

{

3009

3010

case FW_CMD_RA_INIT:

3011

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] RA init!!\n");

3012

FwCmdMap |= FW_RA_INIT_CTL;

3013

FW_CMD_IO_SET(priv, FwCmdMap);

3014

FW_CMD_IO_CLR(priv, FW_RA_INIT_CTL);

3015

break;

3016

3017

case FW_CMD_DIG_DISABLE:

3018

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG disable!!\n");

3019

FwCmdMap &= ~FW_DIG_ENABLE_CTL;

3020

FW_CMD_IO_SET(priv, FwCmdMap);

3021

break;

3022

3023

case FW_CMD_DIG_ENABLE:

3024

case FW_CMD_DIG_RESUME:

3025

if(!(priv->DMFlag & HAL_DM_DIG_DISABLE))

3026

{

3027

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG enable or resume!!\n");

3028

FwCmdMap |= (FW_DIG_ENABLE_CTL|FW_SS_CTL);

3029

FW_CMD_IO_SET(priv, FwCmdMap);

3030

}

3031

break;

3032

3033

case FW_CMD_DIG_HALT:

3034

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG halt!!\n");

3035

FwCmdMap &= ~(FW_DIG_ENABLE_CTL|FW_SS_CTL);

3036

FW_CMD_IO_SET(priv, FwCmdMap);

3037

break;

3038

3039

case FW_CMD_TXPWR_TRACK_THERMAL:

3040

{

3041

u8 ThermalVal = 0;

3042

FwCmdMap |= FW_PWR_TRK_CTL;

3043

FwParam &= FW_PWR_TRK_PARAM_CLR;

3044

ThermalVal = priv->ThermalValue;

3045

FwParam |= ((ThermalVal<<24) |(priv->ThermalMeter[0]<<16));

3046

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);

3047

FW_CMD_PARA_SET(priv, FwParam);

3048

FW_CMD_IO_SET(priv, FwCmdMap);

3049

FW_CMD_IO_CLR(priv, FW_PWR_TRK_CTL);

3050

}

3051

break;

3052

3053

case FW_CMD_RA_REFRESH_N_COMB:

3054

FwCmdMap |= FW_RA_N_CTL;

3055

FwCmdMap &= ~(FW_RA_BG_CTL |FW_RA_INIT_CTL);

3056

FwParam &= FW_RA_PARAM_CLR;

3057

if(!(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL))

3058

FwParam |= ((priv->rtllib->pHTInfo->IOTRaFunc)&0xf);

3059

FwParam |= ((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<4);

3060

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);

3061

FW_CMD_PARA_SET(priv, FwParam);

3062

FW_CMD_IO_SET(priv, FwCmdMap);

3063

FW_CMD_IO_CLR(priv, FW_RA_N_CTL);

3064

break;

3065

3066

case FW_CMD_RA_REFRESH_BG_COMB:

3067

FwCmdMap |= FW_RA_BG_CTL;

3068

FwCmdMap &= ~(FW_RA_N_CTL|FW_RA_INIT_CTL);

3069

FwParam &= FW_RA_PARAM_CLR;

3070

if(!(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL))

3071

FwParam |= ((priv->rtllib->pHTInfo->IOTRaFunc)&0xf);

3072

FwParam |= ((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<4);

3073

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set RA/IOT Comb in BG mode!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);

3074

FW_CMD_PARA_SET(priv, FwParam);

3075

FW_CMD_IO_SET(priv, FwCmdMap);

3076

FW_CMD_IO_CLR(priv, FW_RA_BG_CTL);

3077

break;

3078

3079

case FW_CMD_IQK_ENABLE:

3080

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] IQK enable.\n");

3081

FwCmdMap |= FW_IQK_CTL;

3082

FW_CMD_IO_SET(priv, FwCmdMap);

3083

FW_CMD_IO_CLR(priv, FW_IQK_CTL);

3084

break;

3085

3086

case FW_CMD_CTRL_DM_BY_DRIVER_NEW:

3087

RT_TRACE(COMP_CMD, "[FW CMD][New Version] Inform FW driver control some DM!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);

3088

FwCmdMap |= FW_DRIVER_CTRL_DM_CTL;

3089

FW_CMD_IO_SET(priv, FwCmdMap);

3090

break;

3091

3092

case FW_CMD_RESUME_DM_BY_SCAN:

3093

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Resume DM after scan.\n");

3094

FwCmdMap |= (FW_DIG_ENABLE_CTL|FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);

3095

3096

if(priv->DMFlag & HAL_DM_DIG_DISABLE || !dm_digtable.dig_enable_flag)

3097

FwCmdMap &= ~FW_DIG_ENABLE_CTL;

3098

3099

if((priv->DMFlag & HAL_DM_HIPWR_DISABLE) ||

3100

(priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) ||

3101

(priv->rtllib->bdynamic_txpower_enable == true))

3102

FwCmdMap &= ~FW_HIGH_PWR_ENABLE_CTL;

3103

3104

if( (dm_digtable.Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_0) ||

3105

(dm_digtable.Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_1))

3106

FwCmdMap &= ~FW_DIG_ENABLE_CTL;

3107

3108

FW_CMD_IO_SET(priv, FwCmdMap);

3109

bPostProcessing = true;

3110

break;

3111

3112

case FW_CMD_PAUSE_DM_BY_SCAN:

3113

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Pause DM before scan.\n");

3114

FwCmdMap &= ~(FW_DIG_ENABLE_CTL|FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);

3115

FW_CMD_IO_SET(priv, FwCmdMap);

3116

bPostProcessing = true;

3117

break;

3118

3119

case FW_CMD_HIGH_PWR_DISABLE:

3120

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set HighPwr disable!!\n");

3121

FwCmdMap &= ~FW_HIGH_PWR_ENABLE_CTL;

3122

FW_CMD_IO_SET(priv, FwCmdMap);

3123

bPostProcessing = true;

3124

break;

3125

3126

case FW_CMD_HIGH_PWR_ENABLE:

3127

if(((priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0) &&

3128

!(priv->DMFlag & HAL_DM_HIPWR_DISABLE) &&

3129

(priv->rtllib->bdynamic_txpower_enable != true))

3130

{

3131

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set HighPwr enable!!\n");

3132

FwCmdMap |= (FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);

3133

FW_CMD_IO_SET(priv, FwCmdMap);

3134

bPostProcessing = true;

3135

}

3136

break;

3137

3138

case FW_CMD_DIG_MODE_FA:

3139

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG Mode to FA.\n");

3140

FwCmdMap |= FW_FA_CTL;

3141

FW_CMD_IO_SET(priv, FwCmdMap);

3142

break;

3143

3144

case FW_CMD_DIG_MODE_SS:

3145

RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG Mode to SS.\n");

3146

FwCmdMap &= ~FW_FA_CTL;

3147

FW_CMD_IO_SET(priv, FwCmdMap);

3148

break;

3149

3150

case FW_CMD_PAPE_CONTROL:

3151

RT_TRACE(COMP_CMD, "[FW CMD] Set PAPE Control \n");

3152

#ifdef MERGE_TO_DO

3153

if(pHalData->bt_coexist.BT_PapeCtrl)

3154

{

3155

RTPRINT(FBT, BT_TRACE, ("BT set PAPE Control to SW/HW dynamically. \n"));

3156

FwCmdMap |= FW_PAPE_CTL_BY_SW_HW;

3157

}

3158

else

3159

#endif

3160

{

3161

printk("BT set PAPE Control to SW\n");

3162

FwCmdMap &= ~FW_PAPE_CTL_BY_SW_HW;

3163

}

3164

FW_CMD_IO_SET(priv, FwCmdMap);

3165

break;

3166

3167

default:

3168

bPostProcessing = true;

3169

break;

3170

}

3171

}while(false);

3172

3173

RT_TRACE(COMP_CMD, "[FW CMD] Current FwCmdMap(%#x)\n", priv->FwCmdIOMap);

3174

RT_TRACE(COMP_CMD, "[FW CMD] Current FwCmdIOParam(%#x)\n", priv->FwCmdIOParam);

3175

3176

if(bPostProcessing && !priv->SetFwCmdInProgress)

3177

{

3178

priv->SetFwCmdInProgress = true;

3179

priv->CurrentFwCmdIO = FwCmdIO;

3180

}

3181

else

3182

{

3183

return false;

3184

}

3185

3186

#if 0

3187

#ifdef USE_WORKITEM

3188

PlatformScheduleWorkItem(&(pHalData->FwCmdIOWorkItem));

3189

#else

3190

PlatformSetTimer(Adapter, &(pHalData->SetFwCmdIOTimer), 0);

3191

#endif

3192

#endif

3193

rtl8192_SetFwCmdIOCallback(dev);

3194

return true;

3195

}

3196

void ChkFwCmdIoDone(struct net_device* dev)

3197

{

3198

u16 PollingCnt = 10000;

3199

u32 tmpValue;

3200

3201

3202

{

3203

3204

udelay(10);

3205

3206

tmpValue = read_nic_dword(dev, WFM5);

3207

if(tmpValue == 0)

3208

{

3209

RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");

3210

break;

3211

}

3212

else

3213

{

3214

RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);

3215

}

3216

}while( --PollingCnt );

3217

3218

if(PollingCnt == 0)

3219

{

3220

RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");

3221

}

3222

}

3223

void rtl8192_SetFwCmdIOCallback(struct net_device* dev)

3224

{

3225

struct r8192_priv *priv = rtllib_priv(dev);

3226

u32 input,CurrentAID = 0;

3227

3228

if(IS_NIC_DOWN(priv)){

3229

RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");

3230

return;

3231

}

3232

3233

RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);

3234

3235

if(HalGetFirmwareVerison(priv) >= 0x34)

3236

{

3237

switch(priv->CurrentFwCmdIO)

3238

{

3239

case FW_CMD_RA_REFRESH_N:

3240

priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_N_COMB;

3241

break;

3242

case FW_CMD_RA_REFRESH_BG:

3243

priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;

3244

break;

3245

default:

3246

break;

3247

}

3248

}

3249

3250

switch(priv->CurrentFwCmdIO)

3251

{

3252

3253

case FW_CMD_RA_RESET:

3254

RT_TRACE(COMP_CMD, "[FW CMD] Set RA Reset!!\n");

3255

write_nic_dword(dev, WFM5, FW_RA_RESET);

3256

ChkFwCmdIoDone(dev);

3257

break;

3258

3259

case FW_CMD_RA_ACTIVE:

3260

RT_TRACE(COMP_CMD, "[FW CMD] Set RA Active!!\n");

3261

write_nic_dword(dev, WFM5, FW_RA_ACTIVE);

3262

ChkFwCmdIoDone(dev);

3263

break;

3264

3265

case FW_CMD_RA_REFRESH_N:

3266

RT_TRACE(COMP_CMD, "[FW CMD] Set RA n refresh!!\n");

3267

if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)

3268

input = FW_RA_REFRESH;

3269

else

3270

input = FW_RA_REFRESH | (priv->rtllib->pHTInfo->IOTRaFunc << 8);

3271

write_nic_dword(dev, WFM5, input);

3272

ChkFwCmdIoDone(dev);

3273

write_nic_dword(dev, WFM5, FW_RA_ENABLE_RSSI_MASK);

3274

ChkFwCmdIoDone(dev);

3275

break;

3276

3277

case FW_CMD_RA_REFRESH_BG:

3278

RT_TRACE(COMP_CMD, "[FW CMD] Set RA BG refresh!!\n");

3279

write_nic_dword(dev, WFM5, FW_RA_REFRESH);

3280

ChkFwCmdIoDone(dev);

3281

write_nic_dword(dev, WFM5, FW_RA_DISABLE_RSSI_MASK);

3282

ChkFwCmdIoDone(dev);

3283

break;

3284

3285

case FW_CMD_RA_REFRESH_N_COMB:

3286

RT_TRACE(COMP_CMD, "[FW CMD] Set RA n Combo refresh!!\n");

3287

if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)

3288

input = FW_RA_IOT_N_COMB;

3289

else

3290

input = FW_RA_IOT_N_COMB | (((priv->rtllib->pHTInfo->IOTRaFunc)&0x0f) << 8);

3291

input = input |((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<12);

3292

RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in n mode!! input(%#x)\n", input);

3293

write_nic_dword(dev, WFM5, input);

3294

ChkFwCmdIoDone(dev);

3295

break;

3296

3297

case FW_CMD_RA_REFRESH_BG_COMB:

3298

RT_TRACE(COMP_CMD, "[FW CMD] Set RA B/G Combo refresh!!\n");

3299

if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)

3300

input = FW_RA_IOT_BG_COMB;

3301

else

3302

input = FW_RA_IOT_BG_COMB | (((priv->rtllib->pHTInfo->IOTRaFunc)&0x0f) << 8);

3303

input = input |((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<12);

3304

RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in B/G mode!! input(%#x)\n", input);

3305

write_nic_dword(dev, WFM5, input);

3306

ChkFwCmdIoDone(dev);

3307

break;

3308

3309

case FW_CMD_IQK_ENABLE:

3310

RT_TRACE(COMP_CMD, "[FW CMD] IQK Enable!!\n");

3311

write_nic_dword(dev, WFM5, FW_IQK_ENABLE);

3312

ChkFwCmdIoDone(dev);

3313

break;

3314

3315

case FW_CMD_PAUSE_DM_BY_SCAN:

3316

RT_TRACE(COMP_CMD, "[FW CMD] Pause DM by Scan!!\n");

3317

rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);

3318

rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);

3319

rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);

3320

break;

3321

3322

case FW_CMD_RESUME_DM_BY_SCAN:

3323

RT_TRACE(COMP_CMD, "[FW CMD] Resume DM by Scan!!\n");

3324

rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0xcd);

3325

rtl8192_phy_setTxPower(dev, priv->rtllib->current_network.channel);

3326

break;

3327

3328

case FW_CMD_HIGH_PWR_DISABLE:

3329

RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Disable!!\n");

3330

if(priv->DMFlag & HAL_DM_HIPWR_DISABLE)

3331

break;

3332

rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);

3333

rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);

3334

rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);

3335

break;

3336

3337

case FW_CMD_HIGH_PWR_ENABLE:

3338

RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Enable!!\n");

3339

if((priv->DMFlag & HAL_DM_HIPWR_DISABLE) ||

3340

(priv->rtllib->bdynamic_txpower_enable == true))

3341

break;

3342

rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0xcd);

3343

break;

3344

3345

case FW_CMD_LPS_ENTER:

3346

RT_TRACE(COMP_CMD, "[FW CMD] Enter LPS mode!!\n");

3347

CurrentAID = priv->rtllib->assoc_id;

3348

write_nic_dword(dev, WFM5, (FW_LPS_ENTER| ((CurrentAID|0xc000)<<8)) );

3349

ChkFwCmdIoDone(dev);

3350

priv->rtllib->pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO;

3351

break;

3352

3353

case FW_CMD_LPS_LEAVE:

3354

RT_TRACE(COMP_CMD, "[FW CMD] Leave LPS mode!!\n");

3355

write_nic_dword(dev, WFM5, FW_LPS_LEAVE );

3356

ChkFwCmdIoDone(dev);

3357

priv->rtllib->pHTInfo->IOTAction &= (~HT_IOT_ACT_DISABLE_EDCA_TURBO);

3358

break;

3359

3360

case FW_CMD_ADD_A2_ENTRY:

3361

RT_TRACE(COMP_CMD, "[FW CMD] ADD A2 entry!!\n");

3362

write_nic_dword(dev, WFM5, FW_ADD_A2_ENTRY);

3363

ChkFwCmdIoDone(dev);

3364

break;

3365

3366

case FW_CMD_CTRL_DM_BY_DRIVER:

3367

RT_TRACE(COMP_CMD, "[FW CMD] Inform fw driver will do some dm at driver\n");

3368

write_nic_dword(dev, WFM5, FW_CTRL_DM_BY_DRIVER);

3369

ChkFwCmdIoDone(dev);

3370

break;

3371

#ifdef CONFIG_FW_SETCHAN

3372

case FW_CMD_CHAN_SET:

3373

input = FW_CHAN_SET | (((priv->chan)&0xff) << 8);

3374

RT_TRACE(COMP_CMD, "[FW CMD] Inform fw to set channel to %x!!, input(%#x):\n", priv->chan,input);

3375

write_nic_dword(dev, WFM5, input);

3376

ChkFwCmdIoDone(dev);

3377

break;

3378

#endif

3379

3380

default:

3381

break;

3382

}

3383

3384

3385

ChkFwCmdIoDone(dev);

3386

3387

3388

priv->SetFwCmdInProgress = false;

3389

RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");

3390

}

3391

3392

static void

3393

phy_CheckEphySwitchReady(struct net_device* dev)

3394

{

3395

u32 delay = 100;

3396

u8 regu1;

3397

3398

regu1 = read_nic_byte(dev, 0x554);

3399

while ((regu1 & BIT5) && (delay > 0))

3400

{

3401

regu1 = read_nic_byte(dev, 0x554);

3402

delay--;

3403

udelay(50);

3404

}

3405

RT_TRACE(COMP_INIT, "regu1=%02x delay = %d\n", regu1, delay);

3406

3407

}

3408

3409

#ifdef TO_DO_LIST

3410

void

3411

HW_RadioGpioChk92SE(

3412

IN PADAPTER pAdapter

3413

)

3414

{

3415

PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);

3416

u1Byte u1Tmp = 0;

3417

HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);

3418

RT_RF_POWER_STATE eRfPowerStateToSet;

3419

BOOLEAN bActuallySet = false;

3420

3421

#if 0

3422

if (!RT_IN_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3) &&

3423

pMgntInfo->RfOffReason != RF_CHANGE_BY_HW)

3424

{

3425

return;

3426

}

3427

3428

PlatformSwitchClkReq(pAdapter, 0x00);

3429

3430

if (RT_IN_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3))

3431

{

3432

RT_LEAVE_D3(pAdapter, false);

3433

RT_CLEAR_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3);

3434

Power_DomainInit92SE(pAdapter);

3435

}

3436

3437

PlatformEFIOWrite1Byte(pAdapter, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));

3438

3439

u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IO_SEL);

3440

u1Tmp &= HAL_8192S_HW_GPIO_OFF_MASK;

3441

PlatformEFIOWrite1Byte(pAdapter, GPIO_IO_SEL, u1Tmp);

3442

3443

RT_TRACE(COMP_CMD, DBG_LOUD,

3444

("HW_RadioGpioChk92SE HW_RadioGpioChk92SE=%02x\n", HW_RadioGpioChk92SE));

3445

3446

u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IN);

3447

3448

eRfPowerStateToSet = (u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? eRfOn : eRfOff;

3449

3450

if( (pHalData->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))

3451

{

3452

RT_TRACE(COMP_RF, DBG_LOUD, ("HW_RadioGpioChk92SE - HW Radio ON\n"));

3453

pHalData->bHwRadioOff = false;

3454

bActuallySet = true;

3455

}

3456

else if ( (pHalData->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))

3457

{

3458

RT_TRACE(COMP_RF, DBG_LOUD, ("HW_RadioGpioChk92SE - HW Radio OFF\n"));

3459

pHalData->bHwRadioOff = true;

3460

bActuallySet = true;

3461

}

3462

3463

if(bActuallySet)

3464

{

3465

pHalData->bHwRfOffAction = 1;

3466

MgntActSet_RF_State(pAdapter, eRfPowerStateToSet, RF_CHANGE_BY_HW);

3467

DrvIFIndicateCurrentPhyStatus(pAdapter);

3468

3469

3470

{

3471

PMP_ADAPTER pDevice = &(pAdapter->NdisAdapter);

3472

if(pDevice->RegHwSwRfOffD3 == 1 || pDevice->RegHwSwRfOffD3 == 2)

3473

(eRfPowerStateToSet == eRfOff) ? RT_ENABLE_ASPM(pAdapter) : RT_DISABLE_ASPM(pAdapter);

3474

}

3475

}

3476

RT_TRACE(COMP_RF, DBG_TRACE, ("HW_RadioGpioChk92SE() <--------- \n"));

3477

#endif

3478

}/* HW_RadioGpioChk92SE */

3479

#endif

3480

#endif

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