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Viewing changes to arch/x86/kernel/amd_nb.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
arch/x86/kernel/amd_nb.c
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static u32 *flush_words;
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struct pci_device_id amd_nb_misc_ids[] = {
 
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const struct pci_device_id amd_nb_misc_ids[] = {
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        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
 
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        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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        {}
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};
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EXPORT_SYMBOL(amd_nb_misc_ids);
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static struct pci_device_id amd_nb_link_ids[] = {
 
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        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
 
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        {}
 
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};
 
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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        { 0x00, 0x18, 0x20 },
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        { 0xff, 0x00, 0x20 },
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EXPORT_SYMBOL(amd_northbridges);
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static struct pci_dev *next_northbridge(struct pci_dev *dev,
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                                        struct pci_device_id *ids)
 
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                                        const struct pci_device_id *ids)
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{
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        do {
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                dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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int amd_cache_northbridges(void)
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{
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        int i = 0;
 
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        u16 i = 0;
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        struct amd_northbridge *nb;
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        struct pci_dev *misc;
 
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        struct pci_dev *misc, *link;
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        if (amd_nb_num())
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                return 0;
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        amd_northbridges.nb = nb;
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        amd_northbridges.num = i;
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        misc = NULL;
 
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        link = misc = NULL;
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        for (i = 0; i != amd_nb_num(); i++) {
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                node_to_amd_nb(i)->misc = misc =
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                        next_northbridge(misc, amd_nb_misc_ids);
 
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                node_to_amd_nb(i)->link = link =
 
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                        next_northbridge(link, amd_nb_link_ids);
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        }
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        /* some CPU families (e.g. family 0x11) do not support GART */
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             boot_cpu_data.x86_mask >= 0x1))
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                amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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        if (boot_cpu_data.x86 == 0x15)
 
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                amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 
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        /* L3 cache partitioning is supported on family 0x15 */
 
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        if (boot_cpu_data.x86 == 0x15)
 
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                amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
 
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        return 0;
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}
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EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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/* Ignores subdevice/subvendor but as far as I can figure out
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   they're useless anyways */
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int __init early_is_amd_nb(u32 device)
 
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/*
 
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 * Ignores subdevice/subvendor but as far as I can figure out
 
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 * they're useless anyways
 
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 */
 
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bool __init early_is_amd_nb(u32 device)
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{
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        struct pci_device_id *id;
 
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        const struct pci_device_id *id;
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        u32 vendor = device & 0xffff;
 
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        device >>= 16;
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        for (id = amd_nb_misc_ids; id->vendor; id++)
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                if (vendor == id->vendor && device == id->device)
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                        return 1;
 
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                        return true;
 
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        return false;
 
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}
 
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int amd_get_subcaches(int cpu)
 
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{
 
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        struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
 
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        unsigned int mask;
 
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        int cuid = 0;
 
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        if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 
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                return 0;
 
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        pci_read_config_dword(link, 0x1d4, &mask);
 
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#ifdef CONFIG_SMP
 
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        cuid = cpu_data(cpu).compute_unit_id;
 
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#endif
 
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        return (mask >> (4 * cuid)) & 0xf;
 
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}
 
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int amd_set_subcaches(int cpu, int mask)
 
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{
 
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        static unsigned int reset, ban;
 
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        struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
 
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        unsigned int reg;
 
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        int cuid = 0;
 
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        if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
 
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                return -EINVAL;
 
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        /* if necessary, collect reset state of L3 partitioning and BAN mode */
 
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        if (reset == 0) {
 
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                pci_read_config_dword(nb->link, 0x1d4, &reset);
 
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                pci_read_config_dword(nb->misc, 0x1b8, &ban);
 
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                ban &= 0x180000;
 
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        }
 
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        /* deactivate BAN mode if any subcaches are to be disabled */
 
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        if (mask != 0xf) {
 
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                pci_read_config_dword(nb->misc, 0x1b8, &reg);
 
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                pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
 
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        }
 
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#ifdef CONFIG_SMP
 
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        cuid = cpu_data(cpu).compute_unit_id;
 
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#endif
 
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        mask <<= 4 * cuid;
 
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        mask |= (0xf ^ (1 << cuid)) << 26;
 
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        pci_write_config_dword(nb->link, 0x1d4, mask);
 
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        /* reset BAN mode if L3 partitioning returned to reset state */
 
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        pci_read_config_dword(nb->link, 0x1d4, &reg);
 
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        if (reg == reset) {
 
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                pci_read_config_dword(nb->misc, 0x1b8, &reg);
 
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                reg &= ~0x180000;
 
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                pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
 
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        }
 
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        return 0;
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}
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int amd_cache_gart(void)
 
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static int amd_cache_gart(void)
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{
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       int i;
 
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        u16 i;
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       if (!amd_nb_has_feature(AMD_NB_GART))
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               return 0;