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#include <linux/ftrace.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/sysdev.h>
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#include <linux/syscore_ops.h>
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#include <linux/delay.h>
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#include <linux/timex.h>
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#include <linux/dmar.h>
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EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
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#ifdef CONFIG_X86_32
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* On x86_32, the mapping between cpu and logical apicid may vary
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* depending on apic in use. The following early percpu variable is
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* used for the mapping. This is where the behaviors of x86_64 and 32
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* actually diverge. Let's keep it ugly for now.
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DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
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* Knob to control our willingness to enable the local APIC.
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static int force_enable_local_apic;
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static int force_enable_local_apic __initdata;
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* APIC command line parameters
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unsigned long mp_lapic_addr;
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int disable_apic;
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/* Disable local APIC timer from the kernel commandline or via dmi quirk */
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static int disable_apic_timer __cpuinitdata;
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static int disable_apic_timer __initdata;
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
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EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
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static unsigned int calibration_result;
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static int lapic_next_event(unsigned long delta,
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struct clock_event_device *evt);
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static void lapic_timer_setup(enum clock_event_mode mode,
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struct clock_event_device *evt);
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static void lapic_timer_broadcast(const struct cpumask *mask);
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static void apic_pm_activate(void);
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* The local apic timer can be used for any function which is CPU local.
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static struct clock_event_device lapic_clockevent = {
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
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| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
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.set_mode = lapic_timer_setup,
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.set_next_event = lapic_next_event,
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.broadcast = lapic_timer_broadcast,
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static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
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static unsigned long apic_phys;
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return icr1 | ((u64)icr2 << 32);
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* enable_NMI_through_LVT0 - enable NMI through local vector table 0
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void __cpuinit enable_NMI_through_LVT0(void)
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/* unmask and set to NMI */
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/* Level triggered for 82489DX (32bit mode) */
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if (!lapic_is_integrated())
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v |= APIC_LVT_LEVEL_TRIGGER;
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apic_write(APIC_LVT0, v);
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#ifdef CONFIG_X86_32
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* get_physical_broadcast - Get number of physical broadcast IDs
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* If mask=1, the LVT entry does not generate interrupts while mask=0
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* enables the vector. See also the BKDGs.
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* enables the vector. See also the BKDGs. Must be called with
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* preemption disabled.
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int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
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* The local apic timer can be used for any function which is CPU local.
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static struct clock_event_device lapic_clockevent = {
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
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| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
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.set_mode = lapic_timer_setup,
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.set_next_event = lapic_next_event,
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.broadcast = lapic_timer_broadcast,
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static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
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* Setup the local APIC timer for this CPU. Copy the initialized values
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* of the boot CPU and register the clock event in the framework.
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struct clock_event_device *levt = &__get_cpu_var(lapic_events);
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if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_ARAT)) {
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if (this_cpu_has(X86_FEATURE_ARAT)) {
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lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
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/* Make LAPIC timer preferrable over percpu HPET */
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lapic_clockevent.rating = 150;
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apic->init_apic_ldr();
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#ifdef CONFIG_X86_32
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* APIC LDR is initialized. If logical_apicid mapping was
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* initialized during get_smp_config(), make sure it matches the
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i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
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WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
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/* always use the value from LDR */
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early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
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logical_smp_processor_id();
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* Some NUMA implementations (NUMAQ) don't initialize apicid to
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* node mapping during NUMA init. Now that logical apicid is
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* guaranteed to be known, give it another chance. This is already
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* a bit too late - percpu allocation has already happened without
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* proper NUMA affinity.
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if (apic->x86_32_numa_cpu_node)
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set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
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apic->x86_32_numa_cpu_node(cpu));
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* Set Task Priority to 'accept all'. We never change this
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if (dmar_table_init_ret && !x2apic_supported())
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ioapic_entries = alloc_ioapic_entries();
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if (!ioapic_entries) {
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pr_err("Allocate ioapic_entries failed\n");
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ret = save_IO_APIC_setup(ioapic_entries);
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ret = save_ioapic_entries();
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pr_info("Saving IO-APIC state failed: %d\n", ret);
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if (!ret) /* IR enabling failed */
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restore_IO_APIC_setup(ioapic_entries);
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restore_ioapic_entries();
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legacy_pic->restore_mask();
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local_irq_restore(flags);
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free_ioapic_entries(ioapic_entries);
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if (x2apic_enabled)
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if (!(l & MSR_IA32_APICBASE_ENABLE)) {
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pr_info("Local APIC disabled by BIOS -- reenabling.\n");
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l &= ~MSR_IA32_APICBASE_BASE;
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l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
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l |= MSR_IA32_APICBASE_ENABLE | addr;
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wrmsr(MSR_IA32_APICBASE, l, h);
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enabled_via_apicbase = 1;
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/* see sw-dev-man vol 3, chapter 7.4.13.5 */
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pr_info("spurious APIC interrupt on CPU#%d, "
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"should never happen.\n", smp_processor_id());
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trace_irq_exit(IRQ_HANDLED);
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void smp_error_interrupt(struct pt_regs *regs)
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static const char * const error_interrupt_reason[] = {
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"Send CS error", /* APIC Error Bit 0 */
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"Receive CS error", /* APIC Error Bit 1 */
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"Send accept error", /* APIC Error Bit 2 */
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"Receive accept error", /* APIC Error Bit 3 */
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"Redirectable IPI", /* APIC Error Bit 4 */
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"Send illegal vector", /* APIC Error Bit 5 */
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"Received illegal vector", /* APIC Error Bit 6 */
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"Illegal register address", /* APIC Error Bit 7 */
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trace_irq_entry(ERROR_APIC_VECTOR, NULL, NULL);
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/* First tickle the hardware, only then report what went on. -- REW */
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v = apic_read(APIC_ESR);
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v0 = apic_read(APIC_ESR);
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apic_write(APIC_ESR, 0);
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v1 = apic_read(APIC_ESR);
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ack_APIC_irq();
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atomic_inc(&irq_err_count);
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* Here is what the APIC error bits mean:
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* 1: Receive CS error
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* 2: Send accept error
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* 3: Receive accept error
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* 5: Send illegal vector
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* 6: Received illegal vector
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* 7: Illegal register address
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pr_debug("APIC error on CPU%d: %02x(%02x)\n",
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smp_processor_id(), v , v1);
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trace_irq_exit(IRQ_HANDLED);
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apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
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smp_processor_id(), v0 , v1);
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apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
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apic_printk(APIC_DEBUG, KERN_CONT "\n");
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if (version == 0x0) {
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pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
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"fixing up to 0x10. (tell your hw vendor)\n",
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apic_version[apicid] = version;
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if (num_processors >= nr_cpu_ids) {
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int max = nr_cpu_ids;
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int thiscpu = max + disabled_cpus;
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num_processors++;
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cpu = cpumask_next_zero(-1, cpu_present_mask);
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if (version != apic_version[boot_cpu_physical_apicid])
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"ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
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apic_version[boot_cpu_physical_apicid], cpu, version);
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physid_set(apicid, phys_cpu_present_map);
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if (apicid == boot_cpu_physical_apicid) {
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* x86_bios_cpu_apicid is required to have processors listed
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* in same order as logical cpu numbers. Hence the first
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* entry is BSP, and so on.
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* boot_cpu_init() already hold bit 0 in cpu_present_mask
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cpu = cpumask_next_zero(-1, cpu_present_mask);
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if (version == 0x0) {
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pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
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apic_version[apicid] = version;
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if (version != apic_version[boot_cpu_physical_apicid]) {
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pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
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apic_version[boot_cpu_physical_apicid], cpu, version);
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physid_set(apicid, phys_cpu_present_map);
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if (apicid > max_physical_apicid)
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max_physical_apicid = apicid;
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early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
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early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
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#ifdef CONFIG_X86_32
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early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
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apic->x86_32_early_logical_apicid(cpu);
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set_cpu_possible(cpu, true);
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set_cpu_present(cpu, true);
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static int lapic_resume(struct sys_device *dev)
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static void lapic_resume(void)
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unsigned int l, h;
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unsigned long flags;
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struct IO_APIC_route_entry **ioapic_entries = NULL;
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if (!apic_pm_state.active)
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local_irq_save(flags);
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if (intr_remapping_enabled) {
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ioapic_entries = alloc_ioapic_entries();
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if (!ioapic_entries) {
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WARN(1, "Alloc ioapic_entries in lapic resume failed.");
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ret = save_IO_APIC_setup(ioapic_entries);
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WARN(1, "Saving IO-APIC state failed: %d\n", ret);
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free_ioapic_entries(ioapic_entries);
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mask_IO_APIC_setup(ioapic_entries);
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* IO-APIC and PIC have their own resume routines.
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* We just mask them here to make sure the interrupt
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* subsystem is completely quiet while we enable x2apic
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* and interrupt-remapping.
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mask_ioapic_entries();
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legacy_pic->mask_all();
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apic_write(APIC_ESR, 0);
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apic_read(APIC_ESR);
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if (intr_remapping_enabled) {
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if (intr_remapping_enabled)
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reenable_intr_remapping(x2apic_mode);
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legacy_pic->restore_mask();
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restore_IO_APIC_setup(ioapic_entries);
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free_ioapic_entries(ioapic_entries);
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local_irq_restore(flags);
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* are needed on every CPU up until machine_halt/restart/poweroff.
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static struct sysdev_class lapic_sysclass = {
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static struct syscore_ops lapic_syscore_ops = {
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.resume = lapic_resume,
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.suspend = lapic_suspend,
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static struct sys_device device_lapic = {
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.cls = &lapic_sysclass,
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static void __cpuinit apic_pm_activate(void)
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apic_pm_state.active = 1;
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static int __init init_lapic_sysfs(void)
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/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
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register_syscore_ops(&lapic_syscore_ops);
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error = sysdev_class_register(&lapic_sysclass);
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error = sysdev_register(&device_lapic);
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/* local apic needs to resume before other devices access its registers. */