← Back to branch summary

~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise

« back to all changes in this revision

Viewing changes to drivers/video/via/hw.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

Show diffs side-by-side

added added

removed removed

Lines of Context:
drivers/video/via/hw.c
20
20
 */
21
21
 
22
22
#include <linux/via-core.h>
 
23
#include <asm/olpc.h>
23
24
#include "global.h"
24
 
 
25
 
static struct pll_map pll_value[] = {
26
 
        {25175000,
27
 
                {99, 7, 3},
28
 
                {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
29
 
                {141, 5, 4},
30
 
                {141, 5, 4} },
31
 
        {29581000,
32
 
                {33, 4, 2},
33
 
                {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
34
 
                {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
35
 
                {165, 5, 4} },
36
 
        {26880000,
37
 
                {15, 4, 1},
38
 
                {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
39
 
                {150, 5, 4},
40
 
                {150, 5, 4} },
41
 
        {31500000,
42
 
                {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
43
 
                {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
44
 
                {176, 5, 4},
45
 
                {176, 5, 4} },
46
 
        {31728000,
47
 
                {31, 7, 1},
48
 
                {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
49
 
                {177, 5, 4},
50
 
                {142, 4, 4} },
51
 
        {32688000,
52
 
                {73, 4, 3},
53
 
                {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
54
 
                {183, 5, 4},
55
 
                {146, 4, 4} },
56
 
        {36000000,
57
 
                {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
58
 
                {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
59
 
                {202, 5, 4},
60
 
                {161, 4, 4} },
61
 
        {40000000,
62
 
                {89, 4, 3},
63
 
                {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
64
 
                {112, 5, 3},
65
 
                {112, 5, 3} },
66
 
        {41291000,
67
 
                {23, 4, 1},
68
 
                {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
69
 
                {115, 5, 3},
70
 
                {115, 5, 3} },
71
 
        {43163000,
72
 
                {121, 5, 3},
73
 
                {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
74
 
                {121, 5, 3},
75
 
                {121, 5, 3} },
76
 
        {45250000,
77
 
                {127, 5, 3},
78
 
                {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
79
 
                {127, 5, 3},
80
 
                {127, 5, 3} },
81
 
        {46000000,
82
 
                {90, 7, 2},
83
 
                {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
84
 
                {129, 5, 3},
85
 
                {103, 4, 3} },
86
 
        {46996000,
87
 
                {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
88
 
                {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
89
 
                {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
90
 
                {105, 4, 3} },
91
 
        {48000000,
92
 
                {67, 20, 0},
93
 
                {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
94
 
                {134, 5, 3},
95
 
                {134, 5, 3} },
96
 
        {48875000,
97
 
                {99, 29, 0},
98
 
                {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
99
 
                {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
100
 
                {137, 5, 3} },
101
 
        {49500000,
102
 
                {83, 6, 2},
103
 
                {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
104
 
                {138, 5, 3},
105
 
                {83, 3, 3} },
106
 
        {52406000,
107
 
                {117, 4, 3},
108
 
                {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
109
 
                {117, 4, 3},
110
 
                {88, 3, 3} },
111
 
        {52977000,
112
 
                {37, 5, 1},
113
 
                {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
114
 
                {148, 5, 3},
115
 
                {148, 5, 3} },
116
 
        {56250000,
117
 
                {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
118
 
                {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
119
 
                {157, 5, 3},
120
 
                {157, 5, 3} },
121
 
        {57275000,
122
 
                {0, 0, 0},
123
 
                {2, 2, 0},
124
 
                {2, 2, 0},
125
 
                {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
126
 
        {60466000,
127
 
                {76, 9, 1},
128
 
                {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
129
 
                {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
130
 
                {169, 5, 3} },
131
 
        {61500000,
132
 
                {86, 20, 0},
133
 
                {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
134
 
                {172, 5, 3},
135
 
                {172, 5, 3} },
136
 
        {65000000,
137
 
                {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
138
 
                {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
139
 
                {109, 3, 3},
140
 
                {109, 3, 3} },
141
 
        {65178000,
142
 
                {91, 5, 2},
143
 
                {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
144
 
                {109, 3, 3},
145
 
                {182, 5, 3} },
146
 
        {66750000,
147
 
                {75, 4, 2},
148
 
                {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
149
 
                {150, 4, 3},
150
 
                {112, 3, 3} },
151
 
        {68179000,
152
 
                {19, 4, 0},
153
 
                {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
154
 
                {190, 5, 3},
155
 
                {191, 5, 3} },
156
 
        {69924000,
157
 
                {83, 17, 0},
158
 
                {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
159
 
                {195, 5, 3},
160
 
                {195, 5, 3} },
161
 
        {70159000,
162
 
                {98, 20, 0},
163
 
                {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
164
 
                {196, 5, 3},
165
 
                {195, 5, 3} },
166
 
        {72000000,
167
 
                {121, 24, 0},
168
 
                {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
169
 
                {161, 4, 3},
170
 
                {161, 4, 3} },
171
 
        {78750000,
172
 
                {33, 3, 1},
173
 
                {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
174
 
                {110, 5, 2},
175
 
                {110, 5, 2} },
176
 
        {80136000,
177
 
                {28, 5, 0},
178
 
                {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
179
 
                {112, 5, 2},
180
 
                {112, 5, 2} },
181
 
        {83375000,
182
 
                {93, 2, 3},
183
 
                {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
184
 
                {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
185
 
                {117, 5, 2} },
186
 
        {83950000,
187
 
                {41, 7, 0},
188
 
                {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
189
 
                {117, 5, 2},
190
 
                {117, 5, 2} },
191
 
        {84750000,
192
 
                {118, 5, 2},
193
 
                {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
194
 
                {118, 5, 2},
195
 
                {118, 5, 2} },
196
 
        {85860000,
197
 
                {84, 7, 1},
198
 
                {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
199
 
                {120, 5, 2},
200
 
                {118, 5, 2} },
201
 
        {88750000,
202
 
                {31, 5, 0},
203
 
                {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
204
 
                {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
205
 
                {124, 5, 2} },
206
 
        {94500000,
207
 
                {33, 5, 0},
208
 
                {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
209
 
                {132, 5, 2},
210
 
                {132, 5, 2} },
211
 
        {97750000,
212
 
                {82, 6, 1},
213
 
                {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
214
 
                {137, 5, 2},
215
 
                {137, 5, 2} },
216
 
        {101000000,
217
 
                {127, 9, 1},
218
 
                {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
219
 
                {141, 5, 2},
220
 
                {141, 5, 2} },
221
 
        {106500000,
222
 
                {119, 4, 2},
223
 
                {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
224
 
                {119, 4, 2},
225
 
                {149, 5, 2} },
226
 
        {108000000,
227
 
                {121, 4, 2},
228
 
                {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
229
 
                {151, 5, 2},
230
 
                {151, 5, 2} },
231
 
        {113309000,
232
 
                {95, 12, 0},
233
 
                {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
234
 
                {95, 3, 2},
235
 
                {159, 5, 2} },
236
 
        {118840000,
237
 
                {83, 5, 1},
238
 
                {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
239
 
                {166, 5, 2},
240
 
                {166, 5, 2} },
241
 
        {119000000,
242
 
                {108, 13, 0},
243
 
                {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
244
 
                {133, 4, 2},
245
 
                {167, 5, 2} },
246
 
        {121750000,
247
 
                {85, 5, 1},
248
 
                {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
249
 
                {68, 2, 2},
250
 
                {0, 0, 0} },
251
 
        {125104000,
252
 
                {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
253
 
                {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
254
 
                {175, 5, 2},
255
 
                {0, 0, 0} },
256
 
        {135000000,
257
 
                {94, 5, 1},
258
 
                {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
259
 
                {151, 4, 2},
260
 
                {189, 5, 2} },
261
 
        {136700000,
262
 
                {115, 12, 0},
263
 
                {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
264
 
                {191, 5, 2},
265
 
                {191, 5, 2} },
266
 
        {138400000,
267
 
                {87, 9, 0},
268
 
                {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
269
 
                {116, 3, 2},
270
 
                {194, 5, 2} },
271
 
        {146760000,
272
 
                {103, 5, 1},
273
 
                {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
274
 
                {206, 5, 2},
275
 
                {206, 5, 2} },
276
 
        {153920000,
277
 
                {86, 8, 0},
278
 
                {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
279
 
                {86, 4, 1},
280
 
                {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
281
 
        {156000000,
282
 
                {109, 5, 1},
283
 
                {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
284
 
                {109, 5, 1},
285
 
                {108, 5, 1} },
286
 
        {157500000,
287
 
                {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
288
 
                {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
289
 
                {110, 5, 1},
290
 
                {110, 5, 1} },
291
 
        {162000000,
292
 
                {113, 5, 1},
293
 
                {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
294
 
                {113, 5, 1},
295
 
                {113, 5, 1} },
296
 
        {187000000,
297
 
                {118, 9, 0},
298
 
                {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
299
 
                {131, 5, 1},
300
 
                {131, 5, 1} },
301
 
        {193295000,
302
 
                {108, 8, 0},
303
 
                {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
304
 
                {135, 5, 1},
305
 
                {135, 5, 1} },
306
 
        {202500000,
307
 
                {99, 7, 0},
308
 
                {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
309
 
                {142, 5, 1},
310
 
                {142, 5, 1} },
311
 
        {204000000,
312
 
                {100, 7, 0},
313
 
                {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
314
 
                {143, 5, 1},
315
 
                {143, 5, 1} },
316
 
        {218500000,
317
 
                {92, 6, 0},
318
 
                {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
319
 
                {153, 5, 1},
320
 
                {153, 5, 1} },
321
 
        {234000000,
322
 
                {98, 6, 0},
323
 
                {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
324
 
                {98, 3, 1},
325
 
                {164, 5, 1} },
326
 
        {267250000,
327
 
                {112, 6, 0},
328
 
                {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
329
 
                {187, 5, 1},
330
 
                {187, 5, 1} },
331
 
        {297500000,
332
 
                {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
333
 
                {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
334
 
                {208, 5, 1},
335
 
                {208, 5, 1} },
336
 
        {74481000,
337
 
                {26, 5, 0},
338
 
                {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
339
 
                {208, 5, 3},
340
 
                {209, 5, 3} },
341
 
        {172798000,
342
 
                {121, 5, 1},
343
 
                {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
344
 
                {121, 5, 1},
345
 
                {121, 5, 1} },
346
 
        {122614000,
347
 
                {60, 7, 0},
348
 
                {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
349
 
                {137, 4, 2},
350
 
                {172, 5, 2} },
351
 
        {74270000,
352
 
                {83, 8, 1},
353
 
                {208, 5, 3},
354
 
                {208, 5, 3},
355
 
                {0, 0, 0} },
356
 
        {148500000,
357
 
                {83, 8, 0},
358
 
                {208, 5, 2},
359
 
                {166, 4, 2},
360
 
                {208, 5, 2} }
 
25
#include "via_clock.h"
 
26
 
 
27
static struct pll_limit cle266_pll_limits[] = {
 
28
        {19, 19, 4, 0},
 
29
        {26, 102, 5, 0},
 
30
        {53, 112, 6, 0},
 
31
        {41, 100, 7, 0},
 
32
        {83, 108, 8, 0},
 
33
        {87, 118, 9, 0},
 
34
        {95, 115, 12, 0},
 
35
        {108, 108, 13, 0},
 
36
        {83, 83, 17, 0},
 
37
        {67, 98, 20, 0},
 
38
        {121, 121, 24, 0},
 
39
        {99, 99, 29, 0},
 
40
        {33, 33, 3, 1},
 
41
        {15, 23, 4, 1},
 
42
        {37, 121, 5, 1},
 
43
        {82, 82, 6, 1},
 
44
        {31, 84, 7, 1},
 
45
        {83, 83, 8, 1},
 
46
        {76, 127, 9, 1},
 
47
        {33, 121, 4, 2},
 
48
        {91, 118, 5, 2},
 
49
        {83, 109, 6, 2},
 
50
        {90, 90, 7, 2},
 
51
        {93, 93, 2, 3},
 
52
        {53, 53, 3, 3},
 
53
        {73, 117, 4, 3},
 
54
        {101, 127, 5, 3},
 
55
        {99, 99, 7, 3}
 
56
};
 
57
 
 
58
static struct pll_limit k800_pll_limits[] = {
 
59
        {22, 22, 2, 0},
 
60
        {28, 28, 3, 0},
 
61
        {81, 112, 3, 1},
 
62
        {86, 166, 4, 1},
 
63
        {109, 153, 5, 1},
 
64
        {66, 116, 3, 2},
 
65
        {93, 137, 4, 2},
 
66
        {117, 208, 5, 2},
 
67
        {30, 30, 2, 3},
 
68
        {69, 125, 3, 3},
 
69
        {89, 161, 4, 3},
 
70
        {121, 208, 5, 3},
 
71
        {66, 66, 2, 4},
 
72
        {85, 85, 3, 4},
 
73
        {141, 161, 4, 4},
 
74
        {177, 177, 5, 4}
 
75
};
 
76
 
 
77
static struct pll_limit cx700_pll_limits[] = {
 
78
        {98, 98, 3, 1},
 
79
        {86, 86, 4, 1},
 
80
        {109, 208, 5, 1},
 
81
        {68, 68, 2, 2},
 
82
        {95, 116, 3, 2},
 
83
        {93, 166, 4, 2},
 
84
        {110, 206, 5, 2},
 
85
        {174, 174, 7, 2},
 
86
        {82, 109, 3, 3},
 
87
        {117, 161, 4, 3},
 
88
        {112, 208, 5, 3},
 
89
        {141, 202, 5, 4}
 
90
};
 
91
 
 
92
static struct pll_limit vx855_pll_limits[] = {
 
93
        {86, 86, 4, 1},
 
94
        {108, 208, 5, 1},
 
95
        {110, 208, 5, 2},
 
96
        {83, 112, 3, 3},
 
97
        {103, 161, 4, 3},
 
98
        {112, 209, 5, 3},
 
99
        {142, 161, 4, 4},
 
100
        {141, 176, 5, 4}
 
101
};
 
102
 
 
103
/* according to VIA Technologies these values are based on experiment */
 
104
static struct io_reg scaling_parameters[] = {
 
105
        {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1 */
 
106
        {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2 */
 
107
        {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3 */
 
108
        {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4 */
 
109
        {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5 */
 
110
        {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6 */
 
111
        {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7 */
 
112
        {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8 */
 
113
        {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9 */
 
114
        {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10 */
 
115
        {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11 */
 
116
        {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12 */
 
117
        {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13 */
 
118
        {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14 */
 
119
};
 
120
 
 
121
static struct io_reg common_vga[] = {
 
122
        {VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
 
123
                                        [1] vertical display end (bit 8)
 
124
                                        [2] vertical retrace start (bit 8)
 
125
                                        [3] start vertical blanking (bit 8)
 
126
                                        [4] line compare (bit 8)
 
127
                                        [5] vertical total (bit 9)
 
128
                                        [6] vertical display end (bit 9)
 
129
                                        [7] vertical retrace start (bit 9) */
 
130
        {VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
 
131
                                        [5-6] byte panning */
 
132
        {VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
 
133
                                        [5] start vertical blanking (bit 9)
 
134
                                        [6] line compare (bit 9)
 
135
                                        [7] scan doubling */
 
136
        {VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
 
137
                                        [5] cursor disable */
 
138
        {VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
 
139
                                        [5-6] cursor skew */
 
140
        {VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
 
141
        {VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
 
142
        {VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
 
143
                                        [6] memory refresh bandwidth
 
144
                                        [7] CRTC register protect enable */
 
145
        {VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
 
146
                                        [5] divide memory address clock by 4
 
147
                                        [6] double word addressing */
 
148
        {VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
 
149
                                        [2] divide scan line clock by 2
 
150
                                        [3] divide memory address clock by 2
 
151
                                        [5] address wrap
 
152
                                        [6] byte mode select
 
153
                                        [7] sync enable */
 
154
        {VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
361
155
};
362
156
 
363
157
static struct fifo_depth_select display_fifo_depth_reg = {
728
522
        {VIA_LVDS2, "LVDS2"}
729
523
};
730
524
 
 
525
/* structure with function pointers to support clock control */
 
526
static struct via_clock clock;
 
527
 
731
528
static void load_fix_bit_crtc_reg(void);
732
529
static void __devinit init_gfx_chip_info(int chip_type);
733
530
static void __devinit init_tmds_chip_info(void);
751
548
        viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
752
549
}
753
550
 
754
 
void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 
551
static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
755
552
{
756
553
        outb(index, LUT_INDEX_WRITE);
757
554
        outb(r, LUT_DATA);
822
619
/*Set IGA path for each device*/
823
620
void viafb_set_iga_path(void)
824
621
{
 
622
        int crt_iga_path = 0;
825
623
 
826
624
        if (viafb_SAMM_ON == 1) {
827
625
                if (viafb_CRT_ON) {
828
626
                        if (viafb_primary_dev == CRT_Device)
829
 
                                viaparinfo->crt_setting_info->iga_path = IGA1;
 
627
                                crt_iga_path = IGA1;
830
628
                        else
831
 
                                viaparinfo->crt_setting_info->iga_path = IGA2;
 
629
                                crt_iga_path = IGA2;
832
630
                }
833
631
 
834
632
                if (viafb_DVI_ON) {
845
643
                                        UNICHROME_CLE266)) {
846
644
                                        viaparinfo->
847
645
                                        lvds_setting_info->iga_path = IGA2;
848
 
                                        viaparinfo->
849
 
                                        crt_setting_info->iga_path = IGA1;
 
646
                                        crt_iga_path = IGA1;
850
647
                                        viaparinfo->
851
648
                                        tmds_setting_info->iga_path = IGA1;
852
649
                                } else
866
663
                viafb_SAMM_ON = 0;
867
664
 
868
665
                if (viafb_CRT_ON && viafb_LCD_ON) {
869
 
                        viaparinfo->crt_setting_info->iga_path = IGA1;
 
666
                        crt_iga_path = IGA1;
870
667
                        viaparinfo->lvds_setting_info->iga_path = IGA2;
871
668
                } else if (viafb_CRT_ON && viafb_DVI_ON) {
872
 
                        viaparinfo->crt_setting_info->iga_path = IGA1;
 
669
                        crt_iga_path = IGA1;
873
670
                        viaparinfo->tmds_setting_info->iga_path = IGA2;
874
671
                } else if (viafb_LCD_ON && viafb_DVI_ON) {
875
672
                        viaparinfo->tmds_setting_info->iga_path = IGA1;
878
675
                        viaparinfo->lvds_setting_info->iga_path = IGA2;
879
676
                        viaparinfo->lvds_setting_info2->iga_path = IGA2;
880
677
                } else if (viafb_CRT_ON) {
881
 
                        viaparinfo->crt_setting_info->iga_path = IGA1;
 
678
                        crt_iga_path = IGA1;
882
679
                } else if (viafb_LCD_ON) {
883
680
                        viaparinfo->lvds_setting_info->iga_path = IGA2;
884
681
                } else if (viafb_DVI_ON) {
889
686
        viaparinfo->shared->iga1_devices = 0;
890
687
        viaparinfo->shared->iga2_devices = 0;
891
688
        if (viafb_CRT_ON) {
892
 
                if (viaparinfo->crt_setting_info->iga_path == IGA1)
 
689
                if (crt_iga_path == IGA1)
893
690
                        viaparinfo->shared->iga1_devices |= VIA_CRT;
894
691
                else
895
692
                        viaparinfo->shared->iga2_devices |= VIA_CRT;
927
724
                                viaparinfo->chip_info->
928
725
                                lvds_chip_info2.output_interface);
929
726
        }
 
727
 
 
728
        /* looks like the OLPC has its display wired to DVP1 and LVDS2 */
 
729
        if (machine_is_olpc())
 
730
                viaparinfo->shared->iga2_devices = VIA_DVP1 | VIA_LVDS2;
930
731
}
931
732
 
932
733
static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
1214
1015
 
1215
1016
static void load_fix_bit_crtc_reg(void)
1216
1017
{
 
1018
        viafb_unlock_crt();
 
1019
 
1217
1020
        /* always set to 1 */
1218
1021
        viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1219
1022
        /* line compare should set all bits = 1 (extend modes) */
1220
 
        viafb_write_reg(CR18, VIACR, 0xff);
1221
 
        /* line compare should set all bits = 1 (extend modes) */
1222
 
        viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1223
 
        /* line compare should set all bits = 1 (extend modes) */
1224
 
        viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1225
 
        /* line compare should set all bits = 1 (extend modes) */
1226
1023
        viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1227
1024
        /* line compare should set all bits = 1 (extend modes) */
1228
1025
        viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1229
1026
        /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1230
 
        /* extend mode always set to e3h */
1231
 
        viafb_write_reg(CR17, VIACR, 0xe3);
1232
 
        /* extend mode always set to 0h */
1233
 
        viafb_write_reg(CR08, VIACR, 0x00);
1234
 
        /* extend mode always set to 0h */
1235
 
        viafb_write_reg(CR14, VIACR, 0x00);
 
1027
 
 
1028
        viafb_lock_crt();
1236
1029
 
1237
1030
        /* If K8M800, enable Prefetch Mode. */
1238
1031
        if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1653
1446
 
1654
1447
}
1655
1448
 
1656
 
static u32 cle266_encode_pll(struct pll_config pll)
1657
 
{
1658
 
        return (pll.multiplier << 8)
1659
 
                | (pll.rshift << 6)
1660
 
                | pll.divisor;
1661
 
}
1662
 
 
1663
 
static u32 k800_encode_pll(struct pll_config pll)
1664
 
{
1665
 
        return ((pll.divisor - 2) << 16)
1666
 
                | (pll.rshift << 10)
1667
 
                | (pll.multiplier - 2);
1668
 
}
1669
 
 
1670
 
static u32 vx855_encode_pll(struct pll_config pll)
1671
 
{
1672
 
        return (pll.divisor << 16)
1673
 
                | (pll.rshift << 10)
1674
 
                | pll.multiplier;
1675
 
}
1676
 
 
1677
 
u32 viafb_get_clk_value(int clk)
1678
 
{
1679
 
        u32 value = 0;
1680
 
        int i = 0;
1681
 
 
1682
 
        while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1683
 
                i++;
1684
 
 
1685
 
        if (i == NUM_TOTAL_PLL_TABLE) {
1686
 
                printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1687
 
        } else {
1688
 
                switch (viaparinfo->chip_info->gfx_chip_name) {
1689
 
                case UNICHROME_CLE266:
1690
 
                case UNICHROME_K400:
1691
 
                        value = cle266_encode_pll(pll_value[i].cle266_pll);
1692
 
                        break;
1693
 
 
1694
 
                case UNICHROME_K800:
1695
 
                case UNICHROME_PM800:
1696
 
                case UNICHROME_CN700:
1697
 
                        value = k800_encode_pll(pll_value[i].k800_pll);
1698
 
                        break;
1699
 
 
1700
 
                case UNICHROME_CX700:
1701
 
                case UNICHROME_CN750:
1702
 
                case UNICHROME_K8M890:
1703
 
                case UNICHROME_P4M890:
1704
 
                case UNICHROME_P4M900:
1705
 
                case UNICHROME_VX800:
1706
 
                        value = k800_encode_pll(pll_value[i].cx700_pll);
1707
 
                        break;
1708
 
 
1709
 
                case UNICHROME_VX855:
1710
 
                case UNICHROME_VX900:
1711
 
                        value = vx855_encode_pll(pll_value[i].vx855_pll);
1712
 
                        break;
1713
 
                }
1714
 
        }
1715
 
 
1716
 
        return value;
 
1449
static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
 
1450
        int clk)
 
1451
{
 
1452
        struct via_pll_config cur, up, down, best = {0, 1, 0};
 
1453
        const u32 f0 = 14318180; /* X1 frequency */
 
1454
        int i, f;
 
1455
 
 
1456
        for (i = 0; i < size; i++) {
 
1457
                cur.rshift = limits[i].rshift;
 
1458
                cur.divisor = limits[i].divisor;
 
1459
                cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
 
1460
                f = abs(get_pll_output_frequency(f0, cur) - clk);
 
1461
                up = down = cur;
 
1462
                up.multiplier++;
 
1463
                down.multiplier--;
 
1464
                if (abs(get_pll_output_frequency(f0, up) - clk) < f)
 
1465
                        cur = up;
 
1466
                else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
 
1467
                        cur = down;
 
1468
 
 
1469
                if (cur.multiplier < limits[i].multiplier_min)
 
1470
                        cur.multiplier = limits[i].multiplier_min;
 
1471
                else if (cur.multiplier > limits[i].multiplier_max)
 
1472
                        cur.multiplier = limits[i].multiplier_max;
 
1473
 
 
1474
                f = abs(get_pll_output_frequency(f0, cur) - clk);
 
1475
                if (f < abs(get_pll_output_frequency(f0, best) - clk))
 
1476
                        best = cur;
 
1477
        }
 
1478
 
 
1479
        return best;
 
1480
}
 
1481
 
 
1482
static struct via_pll_config get_best_pll_config(int clk)
 
1483
{
 
1484
        struct via_pll_config config;
 
1485
 
 
1486
        switch (viaparinfo->chip_info->gfx_chip_name) {
 
1487
        case UNICHROME_CLE266:
 
1488
        case UNICHROME_K400:
 
1489
                config = get_pll_config(cle266_pll_limits,
 
1490
                        ARRAY_SIZE(cle266_pll_limits), clk);
 
1491
                break;
 
1492
        case UNICHROME_K800:
 
1493
        case UNICHROME_PM800:
 
1494
        case UNICHROME_CN700:
 
1495
                config = get_pll_config(k800_pll_limits,
 
1496
                        ARRAY_SIZE(k800_pll_limits), clk);
 
1497
                break;
 
1498
        case UNICHROME_CX700:
 
1499
        case UNICHROME_CN750:
 
1500
        case UNICHROME_K8M890:
 
1501
        case UNICHROME_P4M890:
 
1502
        case UNICHROME_P4M900:
 
1503
        case UNICHROME_VX800:
 
1504
                config = get_pll_config(cx700_pll_limits,
 
1505
                        ARRAY_SIZE(cx700_pll_limits), clk);
 
1506
                break;
 
1507
        case UNICHROME_VX855:
 
1508
        case UNICHROME_VX900:
 
1509
                config = get_pll_config(vx855_pll_limits,
 
1510
                        ARRAY_SIZE(vx855_pll_limits), clk);
 
1511
                break;
 
1512
        }
 
1513
 
 
1514
        return config;
1717
1515
}
1718
1516
 
1719
1517
/* Set VCLK*/
1720
1518
void viafb_set_vclock(u32 clk, int set_iga)
1721
1519
{
1722
 
        /* H.W. Reset : ON */
1723
 
        viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1724
 
 
1725
 
        if (set_iga == IGA1) {
1726
 
                /* Change D,N FOR VCLK */
1727
 
                switch (viaparinfo->chip_info->gfx_chip_name) {
1728
 
                case UNICHROME_CLE266:
1729
 
                case UNICHROME_K400:
1730
 
                        via_write_reg(VIASR, SR46, (clk & 0x00FF));
1731
 
                        via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1732
 
                        break;
1733
 
 
1734
 
                case UNICHROME_K800:
1735
 
                case UNICHROME_PM800:
1736
 
                case UNICHROME_CN700:
1737
 
                case UNICHROME_CX700:
1738
 
                case UNICHROME_CN750:
1739
 
                case UNICHROME_K8M890:
1740
 
                case UNICHROME_P4M890:
1741
 
                case UNICHROME_P4M900:
1742
 
                case UNICHROME_VX800:
1743
 
                case UNICHROME_VX855:
1744
 
                case UNICHROME_VX900:
1745
 
                        via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1746
 
                        via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1747
 
                        via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1748
 
                        break;
1749
 
                }
1750
 
        }
1751
 
 
1752
 
        if (set_iga == IGA2) {
1753
 
                /* Change D,N FOR LCK */
1754
 
                switch (viaparinfo->chip_info->gfx_chip_name) {
1755
 
                case UNICHROME_CLE266:
1756
 
                case UNICHROME_K400:
1757
 
                        via_write_reg(VIASR, SR44, (clk & 0x00FF));
1758
 
                        via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1759
 
                        break;
1760
 
 
1761
 
                case UNICHROME_K800:
1762
 
                case UNICHROME_PM800:
1763
 
                case UNICHROME_CN700:
1764
 
                case UNICHROME_CX700:
1765
 
                case UNICHROME_CN750:
1766
 
                case UNICHROME_K8M890:
1767
 
                case UNICHROME_P4M890:
1768
 
                case UNICHROME_P4M900:
1769
 
                case UNICHROME_VX800:
1770
 
                case UNICHROME_VX855:
1771
 
                case UNICHROME_VX900:
1772
 
                        via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1773
 
                        via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1774
 
                        via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1775
 
                        break;
1776
 
                }
1777
 
        }
1778
 
 
1779
 
        /* H.W. Reset : OFF */
1780
 
        viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1781
 
 
1782
 
        /* Reset PLL */
1783
 
        if (set_iga == IGA1) {
1784
 
                viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1785
 
                viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1786
 
        }
1787
 
 
1788
 
        if (set_iga == IGA2) {
1789
 
                viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1790
 
                viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1791
 
        }
 
1520
        struct via_pll_config config = get_best_pll_config(clk);
 
1521
 
 
1522
        if (set_iga == IGA1)
 
1523
                clock.set_primary_pll(config);
 
1524
        if (set_iga == IGA2)
 
1525
                clock.set_secondary_pll(config);
1792
1526
 
1793
1527
        /* Fire! */
1794
1528
        via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
2034
1768
        int i;
2035
1769
        int index = 0;
2036
1770
        int h_addr, v_addr;
2037
 
        u32 pll_D_N;
 
1771
        u32 clock, refresh = viafb_refresh;
 
1772
 
 
1773
        if (viafb_SAMM_ON && set_iga == IGA2)
 
1774
                refresh = viafb_refresh1;
2038
1775
 
2039
1776
        for (i = 0; i < video_mode->mode_array; i++) {
2040
1777
                index = i;
2041
1778
 
2042
 
                if (crt_table[i].refresh_rate == viaparinfo->
2043
 
                        crt_setting_info->refresh_rate)
 
1779
                if (crt_table[i].refresh_rate == refresh)
2044
1780
                        break;
2045
1781
        }
2046
1782
 
2051
1787
        if ((viafb_LCD_ON | viafb_DVI_ON)
2052
1788
            && video_mode->crtc[0].crtc.hor_addr == 640
2053
1789
            && video_mode->crtc[0].crtc.ver_addr == 480
2054
 
            && viaparinfo->crt_setting_info->refresh_rate == 60) {
 
1790
            && refresh == 60) {
2055
1791
                /* The border is 8 pixels. */
2056
1792
                crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
2057
1793
 
2063
1799
        v_addr = crt_reg.ver_addr;
2064
1800
        if (set_iga == IGA1) {
2065
1801
                viafb_unlock_crt();
2066
 
                viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
2067
 
                viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
2068
1802
                viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
2069
1803
        }
2070
1804
 
2077
1811
                break;
2078
1812
        }
2079
1813
 
2080
 
        load_fix_bit_crtc_reg();
2081
1814
        viafb_lock_crt();
2082
1815
        viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
2083
1816
        viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
2087
1820
            && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
2088
1821
                viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
2089
1822
 
2090
 
        pll_D_N = viafb_get_clk_value(crt_table[index].clk);
2091
 
        DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2092
 
        viafb_set_vclock(pll_D_N, set_iga);
 
1823
        clock = crt_reg.hor_total * crt_reg.ver_total
 
1824
                * crt_table[index].refresh_rate;
 
1825
        viafb_set_vclock(clock, set_iga);
2093
1826
 
2094
1827
}
2095
1828
 
2096
1829
void __devinit viafb_init_chip_info(int chip_type)
2097
1830
{
 
1831
        via_clock_init(&clock, chip_type);
2098
1832
        init_gfx_chip_info(chip_type);
2099
1833
        init_tmds_chip_info();
2100
1834
        init_lvds_chip_info();
2101
1835
 
2102
 
        viaparinfo->crt_setting_info->iga_path = IGA1;
2103
 
        viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
2104
 
 
2105
1836
        /*Set IGA path for each device */
2106
1837
        viafb_set_iga_path();
2107
1838
 
2113
1844
                viaparinfo->lvds_setting_info->lcd_mode;
2114
1845
}
2115
1846
 
2116
 
void viafb_update_device_setting(int hres, int vres,
2117
 
        int bpp, int vmode_refresh, int flag)
 
1847
void viafb_update_device_setting(int hres, int vres, int bpp, int flag)
2118
1848
{
2119
1849
        if (flag == 0) {
2120
 
                viaparinfo->crt_setting_info->h_active = hres;
2121
 
                viaparinfo->crt_setting_info->v_active = vres;
2122
 
                viaparinfo->crt_setting_info->bpp = bpp;
2123
 
                viaparinfo->crt_setting_info->refresh_rate =
2124
 
                        vmode_refresh;
2125
 
 
2126
1850
                viaparinfo->tmds_setting_info->h_active = hres;
2127
1851
                viaparinfo->tmds_setting_info->v_active = vres;
2128
1852
 
2129
1853
                viaparinfo->lvds_setting_info->h_active = hres;
2130
1854
                viaparinfo->lvds_setting_info->v_active = vres;
2131
1855
                viaparinfo->lvds_setting_info->bpp = bpp;
2132
 
                viaparinfo->lvds_setting_info->refresh_rate =
2133
 
                        vmode_refresh;
2134
1856
                viaparinfo->lvds_setting_info2->h_active = hres;
2135
1857
                viaparinfo->lvds_setting_info2->v_active = vres;
2136
1858
                viaparinfo->lvds_setting_info2->bpp = bpp;
2137
 
                viaparinfo->lvds_setting_info2->refresh_rate =
2138
 
                        vmode_refresh;
2139
1859
        } else {
2140
1860
 
2141
1861
                if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2147
1867
                        viaparinfo->lvds_setting_info->h_active = hres;
2148
1868
                        viaparinfo->lvds_setting_info->v_active = vres;
2149
1869
                        viaparinfo->lvds_setting_info->bpp = bpp;
2150
 
                        viaparinfo->lvds_setting_info->refresh_rate =
2151
 
                                vmode_refresh;
2152
1870
                }
2153
1871
                if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2154
1872
                        viaparinfo->lvds_setting_info2->h_active = hres;
2155
1873
                        viaparinfo->lvds_setting_info2->v_active = vres;
2156
1874
                        viaparinfo->lvds_setting_info2->bpp = bpp;
2157
 
                        viaparinfo->lvds_setting_info2->refresh_rate =
2158
 
                                vmode_refresh;
2159
1875
                }
2160
1876
        }
2161
1877
}
2398
2114
        outb(0x00, VIAAR);
2399
2115
 
2400
2116
        /* Write Common Setting for Video Mode */
 
2117
        viafb_write_regx(common_vga, ARRAY_SIZE(common_vga));
2401
2118
        switch (viaparinfo->chip_info->gfx_chip_name) {
2402
2119
        case UNICHROME_CLE266:
2403
2120
                viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2430
2147
                break;
2431
2148
        }
2432
2149
 
 
2150
        viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
2433
2151
        device_off();
2434
2152
        via_set_state(devices, VIA_STATE_OFF);
2435
2153
 
2443
2161
 
2444
2162
        viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2445
2163
 
2446
 
        /* Write CRTC */
2447
 
        viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2448
 
 
2449
2164
        /* Write Graphic Controller */
2450
2165
        for (i = 0; i < StdGR; i++)
2451
2166
                via_write_reg(VIAGR, i, VPIT.GR[i]);
2475
2190
                }
2476
2191
        }
2477
2192
 
 
2193
        load_fix_bit_crtc_reg();
2478
2194
        via_set_primary_pitch(viafbinfo->fix.line_length);
2479
2195
        via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2480
2196
                : viafbinfo->fix.line_length);
2494
2210
 
2495
2211
        /* CRT set mode */
2496
2212
        if (viafb_CRT_ON) {
2497
 
                if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2498
 
                        IGA2)) {
 
2213
                if (viafb_SAMM_ON &&
 
2214
                        viaparinfo->shared->iga2_devices & VIA_CRT) {
2499
2215
                        viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2500
 
                                video_bpp1 / 8,
2501
 
                                viaparinfo->crt_setting_info->iga_path);
 
2216
                                video_bpp1 / 8, IGA2);
2502
2217
                } else {
2503
2218
                        viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2504
2219
                                video_bpp / 8,
2505
 
                                viaparinfo->crt_setting_info->iga_path);
 
2220
                                (viaparinfo->shared->iga1_devices & VIA_CRT)
 
2221
                                ? IGA1 : IGA2);
2506
2222
                }
2507
2223
 
2508
2224
                /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2600
2316
                        get_sync(viafbinfo1));
2601
2317
        }
2602
2318
 
 
2319
        clock.set_engine_pll_state(VIA_STATE_ON);
 
2320
        clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
 
2321
        clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
 
2322
 
 
2323
#ifdef CONFIG_FB_VIA_X_COMPATIBILITY
 
2324
        clock.set_primary_pll_state(VIA_STATE_ON);
 
2325
        clock.set_primary_clock_state(VIA_STATE_ON);
 
2326
        clock.set_secondary_pll_state(VIA_STATE_ON);
 
2327
        clock.set_secondary_clock_state(VIA_STATE_ON);
 
2328
#else
 
2329
        if (viaparinfo->shared->iga1_devices) {
 
2330
                clock.set_primary_pll_state(VIA_STATE_ON);
 
2331
                clock.set_primary_clock_state(VIA_STATE_ON);
 
2332
        } else {
 
2333
                clock.set_primary_pll_state(VIA_STATE_OFF);
 
2334
                clock.set_primary_clock_state(VIA_STATE_OFF);
 
2335
        }
 
2336
 
 
2337
        if (viaparinfo->shared->iga2_devices) {
 
2338
                clock.set_secondary_pll_state(VIA_STATE_ON);
 
2339
                clock.set_secondary_clock_state(VIA_STATE_ON);
 
2340
        } else {
 
2341
                clock.set_secondary_pll_state(VIA_STATE_OFF);
 
2342
                clock.set_secondary_clock_state(VIA_STATE_OFF);
 
2343
        }
 
2344
#endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/
 
2345
 
2603
2346
        via_set_state(devices, VIA_STATE_ON);
2604
2347
        device_screen_on();
2605
2348
        return 1;
2608
2351
int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2609
2352
{
2610
2353
        int i;
2611
 
 
2612
 
        for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2613
 
                if ((hres == res_map_refresh_tbl[i].hres)
2614
 
                    && (vres == res_map_refresh_tbl[i].vres)
2615
 
                    && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2616
 
                        return res_map_refresh_tbl[i].pixclock;
 
2354
        struct crt_mode_table *best;
 
2355
        struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
 
2356
 
 
2357
        if (!vmode)
 
2358
                return RES_640X480_60HZ_PIXCLOCK;
 
2359
 
 
2360
        best = &vmode->crtc[0];
 
2361
        for (i = 1; i < vmode->mode_array; i++) {
 
2362
                if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)
 
2363
                        < abs(best->refresh_rate - vmode_refresh))
 
2364
                        best = &vmode->crtc[i];
2617
2365
        }
2618
 
        return RES_640X480_60HZ_PIXCLOCK;
2619
2366
 
 
2367
        return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)
 
2368
                * 1000 / best->refresh_rate;
2620
2369
}
2621
2370
 
2622
2371
int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2623
2372
{
2624
 
#define REFRESH_TOLERANCE 3
2625
 
        int i, nearest = -1, diff = REFRESH_TOLERANCE;
2626
 
        for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2627
 
                if ((hres == res_map_refresh_tbl[i].hres)
2628
 
                    && (vres == res_map_refresh_tbl[i].vres)
2629
 
                    && (diff > (abs(long_refresh -
2630
 
                    res_map_refresh_tbl[i].vmode_refresh)))) {
2631
 
                        diff = abs(long_refresh - res_map_refresh_tbl[i].
2632
 
                                vmode_refresh);
2633
 
                        nearest = i;
2634
 
                }
2635
 
        }
2636
 
#undef REFRESH_TOLERANCE
2637
 
        if (nearest > 0)
2638
 
                return res_map_refresh_tbl[nearest].vmode_refresh;
2639
 
        return 60;
 
2373
        int i;
 
2374
        struct crt_mode_table *best;
 
2375
        struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
 
2376
 
 
2377
        if (!vmode)
 
2378
                return 60;
 
2379
 
 
2380
        best = &vmode->crtc[0];
 
2381
        for (i = 1; i < vmode->mode_array; i++) {
 
2382
                if (abs(vmode->crtc[i].refresh_rate - long_refresh)
 
2383
                        < abs(best->refresh_rate - long_refresh))
 
2384
                        best = &vmode->crtc[i];
 
2385
        }
 
2386
 
 
2387
        if (abs(best->refresh_rate - long_refresh) > 3) {
 
2388
                if (hres == 1200 && vres == 900)
 
2389
                        return 49; /* OLPC DCON only supports 50 Hz */
 
2390
                else
 
2391
                        return 60;
 
2392
        }
 
2393
 
 
2394
        return best->refresh_rate;
2640
2395
}
2641
2396
 
2642
2397
static void device_off(void)