113
132
HARDWARE_TYPE_RTL8192CU,
114
133
HARDWARE_TYPE_RTL8192DE,
115
134
HARDWARE_TYPE_RTL8192DU,
135
HARDWARE_TYPE_RTL8723E,
136
HARDWARE_TYPE_RTL8723U,
118
139
HARDWARE_TYPE_NUM
142
#define IS_HARDWARE_TYPE_8192SU(rtlhal) \
143
(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
144
#define IS_HARDWARE_TYPE_8192SE(rtlhal) \
145
(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
146
#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
147
(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
148
#define IS_HARDWARE_TYPE_8192CU(rtlhal) \
149
(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
150
#define IS_HARDWARE_TYPE_8192DE(rtlhal) \
151
(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
152
#define IS_HARDWARE_TYPE_8192DU(rtlhal) \
153
(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
154
#define IS_HARDWARE_TYPE_8723E(rtlhal) \
155
(rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
156
#define IS_HARDWARE_TYPE_8723U(rtlhal) \
157
(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
158
#define IS_HARDWARE_TYPE_8192S(rtlhal) \
159
(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
160
#define IS_HARDWARE_TYPE_8192C(rtlhal) \
161
(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
162
#define IS_HARDWARE_TYPE_8192D(rtlhal) \
163
(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
164
#define IS_HARDWARE_TYPE_8723(rtlhal) \
165
(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
166
#define IS_HARDWARE_TYPE_8723U(rtlhal) \
167
(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
121
169
enum scan_operation_backup_opt {
122
170
SCAN_OPT_BACKUP = 0,
123
171
SCAN_OPT_RESTORE,
779
907
void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
780
908
void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
781
909
void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
910
int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
783
u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
784
u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
785
u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
913
u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
914
u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
915
u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
916
int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
853
997
enum intf_type interface;
854
998
u16 hw_type; /*92c or 92d or 92s and so on */
856
u8 version; /*version of chip */
1001
u32 version; /*version of chip */
857
1002
u8 state; /*stop 0, start 1 */
861
bool b_h2c_setinprogress;
1009
bool h2c_setinprogress;
862
1010
u8 last_hmeboxnum;
864
1012
/*Reserve page start offset except beacon in TxQ. */
865
1013
u8 fw_rsvdpage_startoffset;
1016
/* FW Cmd IO related */
1019
bool set_fwcmd_inprogress;
1020
u8 current_fwcmd_io;
1023
bool driver_going2unload;
1025
/*AMPDU init min space*/
1026
u8 minspace_cfg; /*For Min spacing configurations */
1029
enum macphy_mode macphymode;
1030
enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1031
enum band_type current_bandtypebackup;
1032
enum band_type bandset;
1033
/* dual MAC 0--Mac0 1--Mac1 */
1035
/* just for DualMac S3S4 */
1037
bool earlymode_enable;
1039
bool during_mac0init_radiob;
1040
bool during_mac1init_radioa;
1041
bool reloadtxpowerindex;
1042
/* True if IMR or IQK have done
1043
for 2.4G in scan progress */
1044
bool load_imrandiqk_setting_for2g;
1046
bool disable_amsdu_8k;
868
1049
struct rtl_security {
890
/*PHY status for DM */
1073
/*PHY status for Dynamic Management */
891
1074
long entry_min_undecoratedsmoothed_pwdb;
892
1075
long undecorated_smoothed_pwdb; /*out dm */
893
1076
long entry_max_undecoratedsmoothed_pwdb;
894
bool b_dm_initialgain_enable;
895
bool bdynamic_txpower_enable;
896
bool bcurrent_turbo_edca;
897
bool bis_any_nonbepkts; /*out dm */
898
bool bis_cur_rdlstate;
899
bool btxpower_trackingInit;
900
bool b_disable_framebursting;
902
bool btxpower_tracking;
904
bool brfpath_rxenable[4];
1077
bool dm_initialgain_enable;
1078
bool dynamic_txpower_enable;
1079
bool current_turbo_edca;
1080
bool is_any_nonbepkts; /*out dm */
1081
bool is_cur_rdlstate;
1082
bool txpower_trackinginit;
1083
bool disable_framebursting;
1085
bool txpower_tracking;
1087
bool rfpath_rxenable[4];
1088
bool inform_fw_driverctrldm;
1089
bool current_mrc_switch;
1092
u8 thermalvalue_rxgain;
906
1093
u8 thermalvalue_iqk;
907
1094
u8 thermalvalue_lck;
908
1095
u8 thermalvalue;
909
1096
u8 last_dtp_lvl;
1097
u8 thermalvalue_avg[AVG_THERMAL_NUM];
1098
u8 thermalvalue_avg_index;
910
1100
u8 dynamic_txhighpower_lvl; /*Tx high power level */
911
u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
1101
u8 dm_flag; /*Indicate each dynamic mechanism's status. */
913
1103
u8 txpower_track_control;
1104
bool interrupt_migration;
1105
bool disable_tx_int;
915
1106
char ofdm_index[2];
919
#define EFUSE_MAX_LOGICAL_SIZE 128
1110
#define EFUSE_MAX_LOGICAL_SIZE 256
921
1112
struct rtl_efuse {
923
1114
bool bootfromefuse;
924
1115
u16 max_physical_size;
925
u8 contents[EFUSE_MAX_LOGICAL_SIZE];
927
1117
u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
928
1118
u16 efuse_usedbytes;
929
1119
u8 efuse_usedpercentage;
1120
#ifdef EFUSE_REPG_WORKAROUND
1121
bool efuse_re_pg_sec1flag;
1122
u8 efuse_re_pg_data[8];
931
1125
u8 autoload_failflag;
933
1128
short epromtype;
938
1133
u8 eeprom_oemid;
939
1134
u16 eeprom_channelplan;
940
1135
u8 eeprom_version;
944
bool b_txpwr_fromeprom;
1141
bool txpwr_fromeprom;
1142
u8 eeprom_crystalcap;
945
1143
u8 eeprom_tssi[2];
946
u8 eeprom_pwrlimit_ht20[3];
947
u8 eeprom_pwrlimit_ht40[3];
948
u8 eeprom_chnlarea_txpwr_cck[2][3];
949
u8 eeprom_chnlarea_txpwr_ht40_1s[2][3];
950
u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3];
951
u8 txpwrlevel_cck[2][14];
952
u8 txpwrlevel_ht40_1s[2][14]; /*For HT 40MHZ pwr */
953
u8 txpwrlevel_ht40_2s[2][14]; /*For HT 40MHZ pwr */
1144
u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1145
u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1146
u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1147
u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1148
u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1149
u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1150
u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1151
u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1152
u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1154
u8 internal_pa_5g[2]; /* pathA / pathB */
955
1158
/*For power group */
956
u8 pwrgroup_ht20[2][14];
957
u8 pwrgroup_ht40[2][14];
1159
u8 eeprom_pwrgroup[2][3];
1160
u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1161
u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
959
char txpwr_ht20diff[2][14]; /*HT 20<->40 Pwr diff */
960
u8 txpwr_legacyhtdiff[2][14]; /*For HT<->legacy pwr diff */
1163
char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1164
/*For HT<->legacy pwr diff*/
1165
u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1166
u8 txpwr_safetyflag; /* Band edge enable flag */
1167
u16 eeprom_txpowerdiff;
1168
u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1169
u8 antenna_txpwdiff[3];
962
1171
u8 eeprom_regulatory;
963
1172
u8 eeprom_thermalmeter;
964
/*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
1173
u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1175
u8 crystalcap; /* CrystalCap. */
967
1179
u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
968
bool b_apk_thermalmeterignore;
1180
bool apk_thermalmeterignore;
1182
bool b1x1_recvcombine;
971
1189
struct rtl_ps_ctl {
1190
bool pwrdomain_protect;
972
1191
bool set_rfpowerstate_inprogress;
973
bool b_in_powersavemode;
1192
bool in_powersavemode;
974
1193
bool rfchange_inprogress;
975
bool b_swrf_processing;
978
u32 last_sleep_jiffies;
979
u32 last_awake_jiffies;
980
u32 last_delaylps_stamp_jiffies;
1194
bool swrf_processing;
983
1198
* just for PCIE ASPM
984
1199
* If it supports ASPM, Offset[560h] = 0x40,
985
1200
* otherwise Offset[560h] = 0x00.
988
bool b_support_backdoor;
1204
bool support_backdoor;
991
1207
enum rt_psmode dot11_psmode; /*Power save mode configured. */
994
1211
u8 fwctrl_psmode;
995
1212
/*For Fw control LPS mode */
997
1214
/*Record Fw PS mode status. */
998
bool b_fw_current_inpsmode;
1215
bool fw_current_inpsmode;
999
1216
u8 reg_max_lps_awakeintvl;
1000
1217
bool report_linked;
1005
1222
u32 rfoff_reason;
1345
/* The max value by HW */
1101
1349
struct rtl_hal_ops {
1102
1350
int (*init_sw_vars) (struct ieee80211_hw *hw);
1103
1351
void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1352
void (*read_chip_version)(struct ieee80211_hw *hw);
1104
1353
void (*read_eeprom_info) (struct ieee80211_hw *hw);
1105
1354
void (*interrupt_recognized) (struct ieee80211_hw *hw,
1106
1355
u32 *p_inta, u32 *p_intb);
1107
1356
int (*hw_init) (struct ieee80211_hw *hw);
1108
1357
void (*hw_disable) (struct ieee80211_hw *hw);
1358
void (*hw_suspend) (struct ieee80211_hw *hw);
1359
void (*hw_resume) (struct ieee80211_hw *hw);
1109
1360
void (*enable_interrupt) (struct ieee80211_hw *hw);
1110
1361
void (*disable_interrupt) (struct ieee80211_hw *hw);
1111
1362
int (*set_network_type) (struct ieee80211_hw *hw,
1112
1363
enum nl80211_iftype type);
1364
void (*set_chk_bssid)(struct ieee80211_hw *hw,
1113
1366
void (*set_bw_mode) (struct ieee80211_hw *hw,
1114
1367
enum nl80211_channel_type ch_type);
1115
1368
u8(*switch_channel) (struct ieee80211_hw *hw);
1120
1373
u32 add_msr, u32 rm_msr);
1121
1374
void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1122
1375
void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1123
void (*update_rate_table) (struct ieee80211_hw *hw);
1376
void (*update_rate_tbl) (struct ieee80211_hw *hw,
1377
struct ieee80211_sta *sta, u8 rssi_level);
1124
1378
void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1125
1379
void (*fill_tx_desc) (struct ieee80211_hw *hw,
1126
1380
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1127
1381
struct ieee80211_tx_info *info,
1128
struct sk_buff *skb, unsigned int queue_index);
1382
struct sk_buff *skb, u8 hw_queue,
1383
struct rtl_tcb_desc *ptcb_desc);
1384
void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1385
u32 buffer_len, bool bIsPsPoll);
1129
1386
void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1130
bool b_firstseg, bool b_lastseg,
1387
bool firstseg, bool lastseg,
1131
1388
struct sk_buff *skb);
1132
bool(*query_rx_desc) (struct ieee80211_hw *hw,
1389
bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1390
bool (*query_rx_desc) (struct ieee80211_hw *hw,
1133
1391
struct rtl_stats *stats,
1134
1392
struct ieee80211_rx_status *rx_status,
1135
1393
u8 *pdesc, struct sk_buff *skb);
1136
1394
void (*set_channel_access) (struct ieee80211_hw *hw);
1137
bool(*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1395
bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1138
1396
void (*dm_watchdog) (struct ieee80211_hw *hw);
1139
1397
void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1140
bool(*set_rf_power_state) (struct ieee80211_hw *hw,
1398
bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1141
1399
enum rf_pwrstate rfpwr_state);
1142
1400
void (*led_control) (struct ieee80211_hw *hw,
1143
1401
enum led_ctl_mode ledaction);
1144
1402
void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1145
u32(*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1146
void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
1403
u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1404
void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1147
1405
void (*enable_hw_sec) (struct ieee80211_hw *hw);
1148
1406
void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1149
u8 *p_macaddr, bool is_group, u8 enc_algo,
1407
u8 *macaddr, bool is_group, u8 enc_algo,
1150
1408
bool is_wepkey, bool clear_all);
1151
1409
void (*init_sw_leds) (struct ieee80211_hw *hw);
1152
1410
void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1153
u32(*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1411
u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1154
1412
void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1156
u32(*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1414
u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1157
1415
u32 regaddr, u32 bitmask);
1158
1416
void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1159
1417
u32 regaddr, u32 bitmask, u32 data);
1418
void (*linked_set_reg) (struct ieee80211_hw *hw);
1419
bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1420
void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1422
void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1423
u8 *ppowerlevel, u8 channel);
1424
bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1426
bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1428
void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1429
void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1430
void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1162
1433
struct rtl_intf_ops {
1435
void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1164
1436
int (*adapter_start) (struct ieee80211_hw *hw);
1165
1437
void (*adapter_stop) (struct ieee80211_hw *hw);
1167
int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
1439
int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1440
struct rtl_tcb_desc *ptcb_desc);
1441
void (*flush)(struct ieee80211_hw *hw, bool drop);
1168
1442
int (*reset_trx_ring) (struct ieee80211_hw *hw);
1443
bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1171
1446
void (*disable_aspm) (struct ieee80211_hw *hw);
1177
1452
struct rtl_mod_params {
1178
1453
/* default: 0 = using hardware encryption */
1456
/* default: 1 = using no linked power save */
1459
/* default: 1 = using linked sw power save */
1462
/* default: 1 = using linked fw power save */
1466
struct rtl_hal_usbint_cfg {
1473
void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1474
void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1475
struct sk_buff_head *);
1478
void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1479
int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1481
struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1482
struct sk_buff_head *);
1484
/* endpoint mapping */
1485
int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1486
u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1182
1489
struct rtl_hal_cfg {
1491
bool write_readback;
1185
1494
struct rtl_hal_ops *ops;
1186
1495
struct rtl_mod_params *mod_params;
1496
struct rtl_hal_usbint_cfg *usb_interface_cfg;
1188
1498
/*this map used for some registers or vars
1189
1499
defined int HAL but used in MAIN */
1300
1708
/* Write data to memory */
1301
1709
#define WRITEEF1BYTE(_ptr, _val) \
1302
1710
(*((u8 *)(_ptr))) = EF1BYTE(_val)
1711
/* Write le16 data to memory in host ordering */
1303
1712
#define WRITEEF2BYTE(_ptr, _val) \
1304
1713
(*((u16 *)(_ptr))) = EF2BYTE(_val)
1305
1714
#define WRITEEF4BYTE(_ptr, _val) \
1306
(*((u32 *)(_ptr))) = EF4BYTE(_val)
1715
(*((u16 *)(_ptr))) = EF2BYTE(_val)
1309
BIT_LEN_MASK_32(0) => 0x00000000
1310
BIT_LEN_MASK_32(1) => 0x00000001
1311
BIT_LEN_MASK_32(2) => 0x00000003
1312
BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
1717
/* Create a bit mask
1719
* BIT_LEN_MASK_32(0) => 0x00000000
1720
* BIT_LEN_MASK_32(1) => 0x00000001
1721
* BIT_LEN_MASK_32(2) => 0x00000003
1722
* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1313
1724
#define BIT_LEN_MASK_32(__bitlen) \
1314
1725
(0xFFFFFFFF >> (32 - (__bitlen)))
1315
1726
#define BIT_LEN_MASK_16(__bitlen) \
1396
1812
((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1815
#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1816
(__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1399
1818
/****************************************
1400
1819
mem access macro define end
1401
1820
****************************************/
1822
#define byte(x, n) ((x >> (8 * n)) & 0xff)
1403
1824
#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1404
1825
#define RTL_WATCH_DOG_TIME 2000
1405
1826
#define MSECS(t) msecs_to_jiffies(t)
1406
#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
1407
#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
1408
#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
1409
#define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA)
1827
#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1828
#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1829
#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1830
#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1410
1831
#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1411
1832
#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1412
1833
#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1460
1883
static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1462
1885
rtlpriv->io.write8_async(rtlpriv, addr, val8);
1887
if (rtlpriv->cfg->write_readback)
1888
rtlpriv->io.read8_sync(rtlpriv, addr);
1465
1891
static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1467
1893
rtlpriv->io.write16_async(rtlpriv, addr, val16);
1895
if (rtlpriv->cfg->write_readback)
1896
rtlpriv->io.read16_sync(rtlpriv, addr);
1470
1899
static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1471
1900
u32 addr, u32 val32)
1473
1902
rtlpriv->io.write32_async(rtlpriv, addr, val32);
1904
if (rtlpriv->cfg->write_readback)
1905
rtlpriv->io.read32_sync(rtlpriv, addr);
1476
1908
static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,