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Viewing changes to ubuntu/rtl8192se/rtllib/rtl819x_HT.h

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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ubuntu/rtl8192se/rtllib/rtl819x_HT.h
1
 
/******************************************************************************
2
 
 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3
 
 *
4
 
 * This program is distributed in the hope that it will be useful, but WITHOUT
5
 
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6
 
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
7
 
 * more details.
8
 
 *
9
 
 * You should have received a copy of the GNU General Public License along with
10
 
 * this program; if not, write to the Free Software Foundation, Inc.,
11
 
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12
 
 *
13
 
 * The full GNU General Public License is included in this distribution in the
14
 
 * file called LICENSE.
15
 
 *
16
 
 * Contact Information:
17
 
 * wlanfae <wlanfae@realtek.com>
18
 
******************************************************************************/
19
 
#ifndef _RTL819XU_HTTYPE_H_
20
 
#define _RTL819XU_HTTYPE_H_
21
 
 
22
 
 
23
 
#define HT_OPMODE_NO_PROTECT            0
24
 
#define HT_OPMODE_OPTIONAL              1
25
 
#define HT_OPMODE_40MHZ_PROTECT 2
26
 
#define HT_OPMODE_MIXED                 3
27
 
 
28
 
#define MIMO_PS_STATIC                          0
29
 
#define MIMO_PS_DYNAMIC                 1
30
 
#define MIMO_PS_NOLIMIT                 3
31
 
 
32
 
 
33
 
 
34
 
#define sHTCLng 4
35
 
 
36
 
 
37
 
#define HT_SUPPORTED_MCS_1SS_BITMAP                                     0x000000ff
38
 
#define HT_SUPPORTED_MCS_2SS_BITMAP                                     0x0000ff00
39
 
#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP                 HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP
40
 
 
41
 
 
42
 
typedef enum _HT_MCS_RATE{
43
 
        HT_MCS0   = 0x00000001,
44
 
        HT_MCS1   = 0x00000002,
45
 
        HT_MCS2   = 0x00000004,
46
 
        HT_MCS3   = 0x00000008,
47
 
        HT_MCS4   = 0x00000010,
48
 
        HT_MCS5   = 0x00000020,
49
 
        HT_MCS6   = 0x00000040,
50
 
        HT_MCS7   = 0x00000080,
51
 
        HT_MCS8   = 0x00000100,
52
 
        HT_MCS9   = 0x00000200,
53
 
        HT_MCS10 = 0x00000400,
54
 
        HT_MCS11 = 0x00000800,
55
 
        HT_MCS12 = 0x00001000,
56
 
        HT_MCS13 = 0x00002000,
57
 
        HT_MCS14 = 0x00004000,
58
 
        HT_MCS15 = 0x00008000,  
59
 
}HT_MCS_RATE,*PHT_MCS_RATE;
60
 
 
61
 
typedef enum _HT_CHANNEL_WIDTH{
62
 
        HT_CHANNEL_WIDTH_20 = 0,
63
 
        HT_CHANNEL_WIDTH_20_40 = 1,
64
 
}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
65
 
 
66
 
typedef enum _HT_EXTCHNL_OFFSET{
67
 
        HT_EXTCHNL_OFFSET_NO_EXT = 0,
68
 
        HT_EXTCHNL_OFFSET_UPPER = 1,
69
 
        HT_EXTCHNL_OFFSET_NO_DEF = 2,
70
 
        HT_EXTCHNL_OFFSET_LOWER = 3,
71
 
}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
72
 
 
73
 
typedef enum _CHNLOP{
74
 
        CHNLOP_NONE = 0, 
75
 
        CHNLOP_SCAN = 1, 
76
 
        CHNLOP_SWBW = 2, 
77
 
        CHNLOP_SWCHNL = 3, 
78
 
} CHNLOP, *PCHNLOP;
79
 
 
80
 
#define CHHLOP_IN_PROGRESS(_pHTInfo)    \
81
 
                ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? true : false
82
 
 
83
 
/*
84
 
typedef union _HT_CAPABILITY{
85
 
        u16     ShortData;
86
 
        u8      CharData[2];
87
 
        struct
88
 
        {
89
 
                u16     AdvCoding:1;
90
 
                u16     ChlWidth:1;
91
 
                u16     MimoPwrSave:2;
92
 
                u16     GreenField:1;
93
 
                u16     ShortGI20Mhz:1;
94
 
                u16     ShortGI40Mhz:1;
95
 
                u16     STBC:1;
96
 
                u16     BeamForm:1;
97
 
                u16     DelayBA:1;
98
 
                u16     MaxAMSDUSize:1;
99
 
                u16     DssCCk:1;
100
 
                u16     PSMP:1;
101
 
                u16     Rsvd:3;
102
 
        }Field;
103
 
}HT_CAPABILITY, *PHT_CAPABILITY;
104
 
 
105
 
typedef union _HT_CAPABILITY_MACPARA{
106
 
        u8      ShortData;
107
 
        u8      CharData[1];
108
 
        struct
109
 
        {
110
 
                u8      MaxRxAMPDU:2;
111
 
                u8      MPDUDensity:2;
112
 
                u8      Rsvd:4;
113
 
        }Field;
114
 
}HT_CAPABILITY_MACPARA, *PHT_CAPABILITY_MACPARA;
115
 
*/
116
 
 
117
 
typedef enum _HT_ACTION{
118
 
        ACT_RECOMMAND_WIDTH             = 0,
119
 
        ACT_MIMO_PWR_SAVE               = 1,
120
 
        ACT_PSMP                                        = 2,
121
 
        ACT_SET_PCO_PHASE               = 3,
122
 
        ACT_MIMO_CHL_MEASURE    = 4,
123
 
        ACT_RECIPROCITY_CORRECT = 5,
124
 
        ACT_MIMO_CSI_MATRICS            = 6,
125
 
        ACT_MIMO_NOCOMPR_STEER  = 7,
126
 
        ACT_MIMO_COMPR_STEER            = 8,
127
 
        ACT_ANTENNA_SELECT              = 9,
128
 
} HT_ACTION, *PHT_ACTION;
129
 
 
130
 
 
131
 
typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{
132
 
        SC_MODE_DUPLICATE = 0,
133
 
        SC_MODE_LOWER = 1,
134
 
        SC_MODE_UPPER = 2,
135
 
        SC_MODE_FULL40MHZ = 3,
136
 
}HT_BW40_SC_E;
137
 
 
138
 
typedef struct _HT_CAPABILITY_ELE{
139
 
 
140
 
        u8      AdvCoding:1;
141
 
        u8      ChlWidth:1;
142
 
        u8      MimoPwrSave:2;
143
 
        u8      GreenField:1;
144
 
        u8      ShortGI20Mhz:1;
145
 
        u8      ShortGI40Mhz:1;
146
 
        u8      TxSTBC:1;
147
 
        u8      RxSTBC:2;
148
 
        u8      DelayBA:1;
149
 
        u8      MaxAMSDUSize:1;
150
 
        u8      DssCCk:1;
151
 
        u8      PSMP:1;
152
 
        u8      Rsvd1:1;
153
 
        u8      LSigTxopProtect:1;
154
 
 
155
 
        u8      MaxRxAMPDUFactor:2;
156
 
        u8      MPDUDensity:3;
157
 
        u8      Rsvd2:3;
158
 
 
159
 
        u8      MCS[16];
160
 
                        
161
 
 
162
 
        u16     ExtHTCapInfo;
163
 
 
164
 
        u8      TxBFCap[4];
165
 
 
166
 
        u8      ASCap;
167
 
 
168
 
} __attribute__ ((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE;
169
 
 
170
 
 
171
 
typedef struct _HT_INFORMATION_ELE{
172
 
        u8      ControlChl;
173
 
 
174
 
        u8      ExtChlOffset:2;
175
 
        u8      RecommemdedTxWidth:1;
176
 
        u8      RIFS:1;
177
 
        u8      PSMPAccessOnly:1;
178
 
        u8      SrvIntGranularity:3;
179
 
 
180
 
        u8      OptMode:2;
181
 
        u8      NonGFDevPresent:1;
182
 
        u8      Revd1:5;
183
 
        u8      Revd2:8;
184
 
 
185
 
        u8      Rsvd3:6;
186
 
        u8      DualBeacon:1;
187
 
        u8      DualCTSProtect:1;
188
 
 
189
 
        u8      SecondaryBeacon:1;
190
 
        u8      LSigTxopProtectFull:1;
191
 
        u8      PcoActive:1;
192
 
        u8      PcoPhase:1;
193
 
        u8      Rsvd4:4;
194
 
 
195
 
        u8      BasicMSC[16];
196
 
} __attribute__ ((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE;
197
 
 
198
 
typedef struct _MIMOPS_CTRL{
199
 
        u8      MimoPsEnable:1;
200
 
        u8      MimoPsMode:1;
201
 
        u8      Reserved:6;
202
 
} MIMOPS_CTRL, *PMIMOPS_CTRL;
203
 
 
204
 
typedef enum _HT_SPEC_VER{
205
 
        HT_SPEC_VER_IEEE = 0,
206
 
        HT_SPEC_VER_EWC = 1,
207
 
}HT_SPEC_VER, *PHT_SPEC_VER;
208
 
 
209
 
typedef enum _HT_AGGRE_MODE_E{
210
 
        HT_AGG_AUTO = 0,
211
 
        HT_AGG_FORCE_ENABLE = 1,
212
 
        HT_AGG_FORCE_DISABLE = 2,
213
 
}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
214
 
 
215
 
 
216
 
typedef struct _RT_HIGH_THROUGHPUT{
217
 
        u8                              bEnableHT;
218
 
        u8                              bCurrentHTSupport;
219
 
 
220
 
        u8                              bRegBW40MHz;                            
221
 
        u8                              bCurBW40MHz;                            
222
 
 
223
 
        u8                              bRegShortGI40MHz;                       
224
 
        u8                              bCurShortGI40MHz;                       
225
 
 
226
 
        u8                              bRegShortGI20MHz;                       
227
 
        u8                              bCurShortGI20MHz;                       
228
 
 
229
 
        u8                              bRegSuppCCK;                            
230
 
        u8                              bCurSuppCCK;                            
231
 
 
232
 
        HT_SPEC_VER                     ePeerHTSpecVer;
233
 
        
234
 
 
235
 
        HT_CAPABILITY_ELE       SelfHTCap;              
236
 
        HT_INFORMATION_ELE      SelfHTInfo;             
237
 
 
238
 
        u8                              PeerHTCapBuf[32];
239
 
        u8                              PeerHTInfoBuf[32];
240
 
 
241
 
 
242
 
        u8                              bAMSDU_Support;                 
243
 
        u16                             nAMSDU_MaxSize;                 
244
 
        u8                              bCurrent_AMSDU_Support; 
245
 
        u16                             nCurrent_AMSDU_MaxSize; 
246
 
#ifdef _RTL8192_EXT_PATCH_
247
 
        u8                              bCurrent_Mesh_AMSDU_Support;    
248
 
#endif  
249
 
 
250
 
        u8                              bAMPDUEnable;                           
251
 
        u8                              bCurrentAMPDUEnable;            
252
 
        u8                              AMPDU_Factor;                           
253
 
        u8                              CurrentAMPDUFactor;             
254
 
        u8                              MPDU_Density;                           
255
 
        u8                              CurrentMPDUDensity;                     
256
 
#ifdef _RTL8192_EXT_PATCH_
257
 
        u8                              bCurrentMeshAMPDUEnable;                
258
 
#endif  
259
 
 
260
 
        HT_AGGRE_MODE_E ForcedAMPDUMode;
261
 
        u8                              ForcedAMPDUFactor;
262
 
        u8                              ForcedMPDUDensity;
263
 
 
264
 
        HT_AGGRE_MODE_E ForcedAMSDUMode;
265
 
        u16                             ForcedAMSDUMaxSize;
266
 
 
267
 
        u8                              bForcedShortGI;
268
 
 
269
 
        u8                              CurrentOpMode;
270
 
 
271
 
        u8                              SelfMimoPs;
272
 
        u8                              PeerMimoPs;
273
 
        
274
 
        HT_EXTCHNL_OFFSET       CurSTAExtChnlOffset;
275
 
        u8                              bCurTxBW40MHz;  
276
 
        u8                              PeerBandwidth;
277
 
 
278
 
        u8                              bSwBwInProgress;
279
 
        CHNLOP                          ChnlOp; 
280
 
        u8                              SwBwStep;
281
 
 
282
 
        u8                              bRegRT2RTAggregation;
283
 
        u8                              RT2RT_HT_Mode;  
284
 
        u8                              bCurrentRT2RTAggregation;
285
 
        u8                              bCurrentRT2RTLongSlotTime;
286
 
        u8                              szRT2RTAggBuffer[10];
287
 
 
288
 
        u8                              bRegRxReorderEnable;
289
 
        u8                              bCurRxReorderEnable;
290
 
        u8                              RxReorderWinSize;
291
 
        u8                              RxReorderPendingTime;
292
 
        u16                             RxReorderDropCounter;
293
 
 
294
 
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
295
 
        u8                              UsbTxAggrNum;
296
 
#endif
297
 
#ifdef USB_RX_AGGREGATION_SUPPORT
298
 
        u8                              UsbRxFwAggrEn;
299
 
        u8                              UsbRxFwAggrPageNum;
300
 
        u8                              UsbRxFwAggrPacketNum;
301
 
        u8                              UsbRxFwAggrTimeout;
302
 
        u8                              UsbRxPageSize;
303
 
#endif
304
 
 
305
 
        u8                              bIsPeerBcm;
306
 
 
307
 
        u8                              IOTPeer;
308
 
        u32                             IOTAction;
309
 
        u8                              IOTRaFunc;
310
 
 
311
 
        u8      bWAIotBroadcom;
312
 
        u8      WAIotTH;
313
 
 
314
 
#ifdef RTL8192CE
315
 
        u8                              bRDGEnable;
316
 
#endif
317
 
 
318
 
        u8                              bAcceptAddbaReq;
319
 
} __attribute__ ((packed)) RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT;
320
 
 
321
 
 
322
 
 
323
 
typedef struct _RT_HTINFO_STA_ENTRY{
324
 
        u8                      bEnableHT;
325
 
        
326
 
        u8                      bSupportCck;
327
 
        
328
 
        u16                     AMSDU_MaxSize;
329
 
        
330
 
        u8                      AMPDU_Factor;
331
 
        u8                      MPDU_Density;
332
 
        
333
 
        u8                      HTHighestOperaRate;
334
 
 
335
 
        u8                      bBw40MHz;
336
 
 
337
 
        u8                      bCurTxBW40MHz;
338
 
 
339
 
        u8                      bCurShortGI20MHz;
340
 
 
341
 
        u8                      bCurShortGI40MHz;
342
 
 
343
 
        u8                      MimoPs;
344
 
 
345
 
        u8                      McsRateSet[16];
346
 
        
347
 
        u8                      bCurRxReorderEnable;
348
 
 
349
 
        u16                     nAMSDU_MaxSize;
350
 
        
351
 
}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY;
352
 
 
353
 
 
354
 
 
355
 
 
356
 
 
357
 
 
358
 
typedef struct _BSS_HT{
359
 
 
360
 
        u8                              bdSupportHT;
361
 
 
362
 
        u8                                      bdHTCapBuf[32];
363
 
        u16                                     bdHTCapLen;
364
 
        u8                                      bdHTInfoBuf[32];
365
 
        u16                                     bdHTInfoLen;
366
 
 
367
 
        HT_SPEC_VER                             bdHTSpecVer;
368
 
        HT_CHANNEL_WIDTH                        bdBandWidth;
369
 
 
370
 
        u8                                      bdRT2RTAggregation;
371
 
        u8                                      bdRT2RTLongSlotTime;
372
 
        u8                                      RT2RT_HT_Mode;
373
 
        u8                                      bdHT1R;
374
 
} __attribute__ ((packed)) BSS_HT, *PBSS_HT;
375
 
 
376
 
typedef struct _MIMO_RSSI{
377
 
        u32     EnableAntenna;
378
 
        u32     AntennaA;
379
 
        u32     AntennaB;
380
 
        u32     AntennaC;
381
 
        u32     AntennaD;
382
 
        u32     Average;
383
 
}MIMO_RSSI, *PMIMO_RSSI;
384
 
 
385
 
typedef struct _MIMO_EVM{
386
 
        u32     EVM1;
387
 
        u32    EVM2;
388
 
}MIMO_EVM, *PMIMO_EVM;
389
 
 
390
 
typedef struct _FALSE_ALARM_STATISTICS{
391
 
        u32     Cnt_Parity_Fail;
392
 
        u32     Cnt_Rate_Illegal;
393
 
        u32     Cnt_Crc8_fail;
394
 
        u32     Cnt_Mcs_fail;
395
 
        u32     Cnt_Ofdm_fail;
396
 
        u32     Cnt_Cck_fail;
397
 
        u32     Cnt_all;
398
 
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
399
 
 
400
 
 
401
 
extern u8 MCS_FILTER_ALL[16];
402
 
extern u8 MCS_FILTER_1SS[16];
403
 
 
404
 
#define PICK_RATE(_nLegacyRate, _nMcsRate)      \
405
 
                (_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
406
 
#define LEGACY_WIRELESS_MODE    IEEE_MODE_MASK
407
 
 
408
 
#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate)  \
409
 
                                        ((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
410
 
                                                (LegacyRate):\
411
 
                                                (PICK_RATE(LegacyRate, HTRate))
412
 
 
413
 
 
414
 
 
415
 
#define RATE_ADPT_1SS_MASK              0xFF
416
 
#define RATE_ADPT_2SS_MASK              0xF0 
417
 
#define RATE_ADPT_MCS32_MASK            0x01
418
 
 
419
 
#define         IS_11N_MCS_RATE(rate)           (rate&0x80)
420
 
 
421
 
typedef enum _HT_AGGRE_SIZE{
422
 
        HT_AGG_SIZE_8K = 0,
423
 
        HT_AGG_SIZE_16K = 1,
424
 
        HT_AGG_SIZE_32K = 2,
425
 
        HT_AGG_SIZE_64K = 3,
426
 
}HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
427
 
 
428
 
typedef enum _HT_IOT_PEER
429
 
{
430
 
        HT_IOT_PEER_UNKNOWN = 0,
431
 
        HT_IOT_PEER_REALTEK = 1,
432
 
        HT_IOT_PEER_REALTEK_92SE = 2,
433
 
        HT_IOT_PEER_BROADCOM = 3,
434
 
        HT_IOT_PEER_RALINK = 4,
435
 
        HT_IOT_PEER_ATHEROS = 5,
436
 
        HT_IOT_PEER_CISCO= 6,
437
 
        HT_IOT_PEER_MARVELL=7,
438
 
        HT_IOT_PEER_92U_SOFTAP = 8,
439
 
        HT_IOT_PEER_SELF_SOFTAP = 9,
440
 
        HT_IOT_PEER_AIRGO = 10,
441
 
        HT_IOT_PEER_MAX = 11,
442
 
}HT_IOT_PEER_E, *PHTIOT_PEER_E;
443
 
 
444
 
typedef enum _HT_IOT_PEER_SUBTYPE
445
 
{
446
 
        HT_IOT_PEER_ATHEROS_DIR635 = 0,
447
 
}HT_IOT_PEER_SUBTYPE_E, *PHTIOT_PEER_SUBTYPE_E;
448
 
 
449
 
typedef enum _HT_IOT_ACTION{
450
 
        HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
451
 
        HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,        
452
 
        HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
453
 
        HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
454
 
        HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
455
 
        HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
456
 
        HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
457
 
        HT_IOT_ACT_CDD_FSYNC = 0x00000080,
458
 
        HT_IOT_ACT_PURE_N_MODE = 0x00000100,
459
 
        HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
460
 
        HT_IOT_ACT_FORCED_RTS = 0x00000400,
461
 
        HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
462
 
        HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
463
 
        HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
464
 
        HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
465
 
 
466
 
        HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
467
 
        HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
468
 
        HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
469
 
        HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
470
 
        HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
471
 
        HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
472
 
        
473
 
        HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
474
 
        HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
475
 
        
476
 
        HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
477
 
        HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
478
 
        HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
479
 
        HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
480
 
 
481
 
        HT_IOT_ACT_IPTIME_704 = 0x10000000,
482
 
 
483
 
}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
484
 
 
485
 
typedef enum _HT_IOT_RAFUNC{
486
 
        HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
487
 
        HT_IOT_RAFUNC_PEER_1R = 0x01,
488
 
        HT_IOT_RAFUNC_TX_AMSDU = 0x02,
489
 
}HT_IOT_RAFUNC, *PHT_IOT_RAFUNC;
490
 
 
491
 
typedef enum _RT_HT_CAP{
492
 
        RT_HT_CAP_USE_TURBO_AGGR = 0x01,
493
 
        RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
494
 
        RT_HT_CAP_USE_AMPDU = 0x04,
495
 
        RT_HT_CAP_USE_WOW = 0x8,        
496
 
        RT_HT_CAP_USE_SOFTAP = 0x10,    
497
 
        RT_HT_CAP_USE_92SE = 0x20,
498
 
}RT_HT_CAPBILITY, *PRT_HT_CAPBILITY;
499
 
 
500
 
#endif 
501