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Viewing changes to drivers/mtd/nand/s3c2410.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/mtd/nand/s3c2410.c
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#endif
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#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
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static int clock_stop = 1;
 
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static const int clock_stop = 1;
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#else
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static const int clock_stop = 0;
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#endif
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        TYPE_S3C2440,
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};
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enum s3c_nand_clk_state {
 
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        CLOCK_DISABLE   = 0,
 
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        CLOCK_ENABLE,
 
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        CLOCK_SUSPEND,
 
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};
 
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/* overview of the s3c2410 nand state */
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/**
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 * @mtd_count: The number of MTDs created from this controller.
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 * @save_sel: The contents of @sel_reg to be saved over suspend.
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 * @clk_rate: The clock rate from @clk.
 
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 * @clk_state: The current clock state.
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 * @cpu_type: The exact type of this controller.
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 */
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struct s3c2410_nand_info {
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        int                             mtd_count;
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        unsigned long                   save_sel;
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        unsigned long                   clk_rate;
 
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        enum s3c_nand_clk_state         clk_state;
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        enum s3c_cpu_type               cpu_type;
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        return dev->dev.platform_data;
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}
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static inline int allow_clk_stop(struct s3c2410_nand_info *info)
 
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static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
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{
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        return clock_stop;
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}
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/**
 
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 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
 
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 * @info: The controller instance.
 
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 * @new_state: State to which clock should be set.
 
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 */
 
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static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
 
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                enum s3c_nand_clk_state new_state)
 
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{
 
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        if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
 
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                return;
 
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        if (info->clk_state == CLOCK_ENABLE) {
 
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                if (new_state != CLOCK_ENABLE)
 
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                        clk_disable(info->clk);
 
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        } else {
 
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                if (new_state == CLOCK_ENABLE)
 
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                        clk_enable(info->clk);
 
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        }
 
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        info->clk_state = new_state;
 
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}
 
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/* timing calculations */
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#define NS_IN_KHZ 1000000
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        nmtd = this->priv;
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        info = nmtd->info;
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        if (chip != -1 && allow_clk_stop(info))
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                clk_enable(info->clk);
 
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        if (chip != -1)
 
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                s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
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        cur = readl(info->sel_reg);
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        writel(cur, info->sel_reg);
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        if (chip == -1 && allow_clk_stop(info))
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                clk_disable(info->clk);
 
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        if (chip == -1)
 
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                s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
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}
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/* s3c2410_nand_hwcontrol
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        /* free the common resources */
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        if (info->clk != NULL && !IS_ERR(info->clk)) {
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                if (!allow_clk_stop(info))
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                        clk_disable(info->clk);
 
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                s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
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                clk_put(info->clk);
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        }
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        return 0;
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}
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#ifdef CONFIG_MTD_PARTITIONS
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const char *part_probes[] = { "cmdlinepart", NULL };
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static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
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                                      struct s3c2410_nand_mtd *mtd,
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        int nr_part = 0;
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        if (set == NULL)
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                return add_mtd_device(&mtd->mtd);
 
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                return mtd_device_register(&mtd->mtd, NULL, 0);
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        mtd->mtd.name = set->name;
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        nr_part = parse_mtd_partitions(&mtd->mtd, part_probes, &part_info, 0);
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                part_info = set->partitions;
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        }
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        if (nr_part > 0 && part_info)
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                return add_mtd_partitions(&mtd->mtd, part_info, nr_part);
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        return add_mtd_device(&mtd->mtd);
742
 
}
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#else
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static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
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                                      struct s3c2410_nand_mtd *mtd,
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                                      struct s3c2410_nand_set *set)
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{
748
 
        return add_mtd_device(&mtd->mtd);
749
 
}
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#endif
 
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        return mtd_device_register(&mtd->mtd, part_info, nr_part);
 
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}
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/**
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 * s3c2410_nand_init_chip - initialise a single instance of an chip
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                goto exit_error;
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        }
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        clk_enable(info->clk);
 
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        s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
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        /* allocate and map the resource */
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                goto exit_error;
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        }
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1029
 
        if (allow_clk_stop(info)) {
 
1046
        if (allow_clk_suspend(info)) {
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                dev_info(&pdev->dev, "clock idle support enabled\n");
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                clk_disable(info->clk);
 
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                s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
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        }
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        pr_debug("initialised ok\n");
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                writel(info->save_sel | info->sel_bit, info->sel_reg);
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1062
 
                if (!allow_clk_stop(info))
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                        clk_disable(info->clk);
 
1079
                s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
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        }
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        return 0;
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        unsigned long sel;
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        if (info) {
1075
 
                clk_enable(info->clk);
 
1091
                s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
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                s3c2410_nand_inithw(info);
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                /* Restore the state of the nFCE line. */
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                sel |= info->save_sel & info->sel_bit;
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                writel(sel, info->sel_reg);
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1085
 
                if (allow_clk_stop(info))
1086
 
                        clk_disable(info->clk);
 
1101
                s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
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        }
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        return 0;