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Viewing changes to drivers/net/igb/e1000_82575.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/net/igb/e1000_82575.c
64
64
static s32  igb_read_mac_addr_82575(struct e1000_hw *);
65
65
static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
66
66
static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
67
 
 
 
67
static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
 
68
static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
 
69
static s32  igb_update_nvm_checksum_with_offset(struct e1000_hw *hw,
 
70
                                                u16 offset);
 
71
static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 
72
                                                u16 offset);
 
73
static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
 
74
static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
68
75
static const u16 e1000_82580_rxpbs_table[] =
69
76
        { 36, 72, 144, 1, 2, 4, 8, 16,
70
77
          35, 70, 140 };
129
136
                break;
130
137
        case E1000_DEV_ID_82580_COPPER:
131
138
        case E1000_DEV_ID_82580_FIBER:
 
139
        case E1000_DEV_ID_82580_QUAD_FIBER:
132
140
        case E1000_DEV_ID_82580_SERDES:
133
141
        case E1000_DEV_ID_82580_SGMII:
134
142
        case E1000_DEV_ID_82580_COPPER_DUAL:
194
202
        mac->arc_subsystem_valid =
195
203
                (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
196
204
                        ? true : false;
197
 
 
 
205
        /* enable EEE on i350 parts */
 
206
        if (mac->type == e1000_i350)
 
207
                dev_spec->eee_disable = false;
 
208
        else
 
209
                dev_spec->eee_disable = true;
198
210
        /* physical interface link setup */
199
211
        mac->ops.setup_physical_interface =
200
212
                (hw->phy.media_type == e1000_media_type_copper)
232
244
         */
233
245
        size += NVM_WORD_SIZE_BASE_SHIFT;
234
246
 
235
 
        /* EEPROM access above 16k is unsupported */
236
 
        if (size > 14)
237
 
                size = 14;
 
247
        /*
 
248
         * Check for invalid size
 
249
         */
 
250
        if ((hw->mac.type == e1000_82576) && (size > 15)) {
 
251
                printk("igb: The NVM size is not valid, "
 
252
                        "defaulting to 32K.\n");
 
253
                size = 15;
 
254
        }
238
255
        nvm->word_size = 1 << size;
239
 
 
240
 
        /* if 82576 then initialize mailbox parameters */
241
 
        if (mac->type == e1000_82576)
 
256
        if (nvm->word_size == (1 << 15))
 
257
                nvm->page_size = 128;
 
258
 
 
259
        /* NVM Function Pointers */
 
260
        nvm->ops.acquire = igb_acquire_nvm_82575;
 
261
        if (nvm->word_size < (1 << 15))
 
262
                nvm->ops.read = igb_read_nvm_eerd;
 
263
        else
 
264
                nvm->ops.read = igb_read_nvm_spi;
 
265
 
 
266
        nvm->ops.release = igb_release_nvm_82575;
 
267
        switch (hw->mac.type) {
 
268
        case e1000_82580:
 
269
                nvm->ops.validate = igb_validate_nvm_checksum_82580;
 
270
                nvm->ops.update = igb_update_nvm_checksum_82580;
 
271
                break;
 
272
        case e1000_i350:
 
273
                nvm->ops.validate = igb_validate_nvm_checksum_i350;
 
274
                nvm->ops.update = igb_update_nvm_checksum_i350;
 
275
                break;
 
276
        default:
 
277
                nvm->ops.validate = igb_validate_nvm_checksum;
 
278
                nvm->ops.update = igb_update_nvm_checksum;
 
279
        }
 
280
        nvm->ops.write = igb_write_nvm_spi;
 
281
 
 
282
        /* if part supports SR-IOV then initialize mailbox parameters */
 
283
        switch (mac->type) {
 
284
        case e1000_82576:
 
285
        case e1000_i350:
242
286
                igb_init_mbx_params_pf(hw);
 
287
                break;
 
288
        default:
 
289
                break;
 
290
        }
243
291
 
244
292
        /* setup PHY parameters */
245
293
        if (phy->media_type != e1000_media_type_copper) {
1747
1795
        return ret_val;
1748
1796
}
1749
1797
 
 
1798
/**
 
1799
 *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
 
1800
 *  checksum
 
1801
 *  @hw: pointer to the HW structure
 
1802
 *  @offset: offset in words of the checksum protected region
 
1803
 *
 
1804
 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 
1805
 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 
1806
 **/
 
1807
s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
 
1808
{
 
1809
        s32 ret_val = 0;
 
1810
        u16 checksum = 0;
 
1811
        u16 i, nvm_data;
 
1812
 
 
1813
        for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
 
1814
                ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
 
1815
                if (ret_val) {
 
1816
                        hw_dbg("NVM Read Error\n");
 
1817
                        goto out;
 
1818
                }
 
1819
                checksum += nvm_data;
 
1820
        }
 
1821
 
 
1822
        if (checksum != (u16) NVM_SUM) {
 
1823
                hw_dbg("NVM Checksum Invalid\n");
 
1824
                ret_val = -E1000_ERR_NVM;
 
1825
                goto out;
 
1826
        }
 
1827
 
 
1828
out:
 
1829
        return ret_val;
 
1830
}
 
1831
 
 
1832
/**
 
1833
 *  igb_update_nvm_checksum_with_offset - Update EEPROM
 
1834
 *  checksum
 
1835
 *  @hw: pointer to the HW structure
 
1836
 *  @offset: offset in words of the checksum protected region
 
1837
 *
 
1838
 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 
1839
 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 
1840
 *  value to the EEPROM.
 
1841
 **/
 
1842
s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
 
1843
{
 
1844
        s32 ret_val;
 
1845
        u16 checksum = 0;
 
1846
        u16 i, nvm_data;
 
1847
 
 
1848
        for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
 
1849
                ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
 
1850
                if (ret_val) {
 
1851
                        hw_dbg("NVM Read Error while updating checksum.\n");
 
1852
                        goto out;
 
1853
                }
 
1854
                checksum += nvm_data;
 
1855
        }
 
1856
        checksum = (u16) NVM_SUM - checksum;
 
1857
        ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
 
1858
                                &checksum);
 
1859
        if (ret_val)
 
1860
                hw_dbg("NVM Write Error while updating checksum.\n");
 
1861
 
 
1862
out:
 
1863
        return ret_val;
 
1864
}
 
1865
 
 
1866
/**
 
1867
 *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
 
1868
 *  @hw: pointer to the HW structure
 
1869
 *
 
1870
 *  Calculates the EEPROM section checksum by reading/adding each word of
 
1871
 *  the EEPROM and then verifies that the sum of the EEPROM is
 
1872
 *  equal to 0xBABA.
 
1873
 **/
 
1874
static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
 
1875
{
 
1876
        s32 ret_val = 0;
 
1877
        u16 eeprom_regions_count = 1;
 
1878
        u16 j, nvm_data;
 
1879
        u16 nvm_offset;
 
1880
 
 
1881
        ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
 
1882
        if (ret_val) {
 
1883
                hw_dbg("NVM Read Error\n");
 
1884
                goto out;
 
1885
        }
 
1886
 
 
1887
        if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
 
1888
                /* if checksums compatibility bit is set validate checksums
 
1889
                 * for all 4 ports. */
 
1890
                eeprom_regions_count = 4;
 
1891
        }
 
1892
 
 
1893
        for (j = 0; j < eeprom_regions_count; j++) {
 
1894
                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 
1895
                ret_val = igb_validate_nvm_checksum_with_offset(hw,
 
1896
                                                                nvm_offset);
 
1897
                if (ret_val != 0)
 
1898
                        goto out;
 
1899
        }
 
1900
 
 
1901
out:
 
1902
        return ret_val;
 
1903
}
 
1904
 
 
1905
/**
 
1906
 *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
 
1907
 *  @hw: pointer to the HW structure
 
1908
 *
 
1909
 *  Updates the EEPROM section checksums for all 4 ports by reading/adding
 
1910
 *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
 
1911
 *  checksum and writes the value to the EEPROM.
 
1912
 **/
 
1913
static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
 
1914
{
 
1915
        s32 ret_val;
 
1916
        u16 j, nvm_data;
 
1917
        u16 nvm_offset;
 
1918
 
 
1919
        ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
 
1920
        if (ret_val) {
 
1921
                hw_dbg("NVM Read Error while updating checksum"
 
1922
                        " compatibility bit.\n");
 
1923
                goto out;
 
1924
        }
 
1925
 
 
1926
        if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
 
1927
                /* set compatibility bit to validate checksums appropriately */
 
1928
                nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
 
1929
                ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
 
1930
                                        &nvm_data);
 
1931
                if (ret_val) {
 
1932
                        hw_dbg("NVM Write Error while updating checksum"
 
1933
                                " compatibility bit.\n");
 
1934
                        goto out;
 
1935
                }
 
1936
        }
 
1937
 
 
1938
        for (j = 0; j < 4; j++) {
 
1939
                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 
1940
                ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
 
1941
                if (ret_val)
 
1942
                        goto out;
 
1943
        }
 
1944
 
 
1945
out:
 
1946
        return ret_val;
 
1947
}
 
1948
 
 
1949
/**
 
1950
 *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
 
1951
 *  @hw: pointer to the HW structure
 
1952
 *
 
1953
 *  Calculates the EEPROM section checksum by reading/adding each word of
 
1954
 *  the EEPROM and then verifies that the sum of the EEPROM is
 
1955
 *  equal to 0xBABA.
 
1956
 **/
 
1957
static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
 
1958
{
 
1959
        s32 ret_val = 0;
 
1960
        u16 j;
 
1961
        u16 nvm_offset;
 
1962
 
 
1963
        for (j = 0; j < 4; j++) {
 
1964
                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 
1965
                ret_val = igb_validate_nvm_checksum_with_offset(hw,
 
1966
                                                                nvm_offset);
 
1967
                if (ret_val != 0)
 
1968
                        goto out;
 
1969
        }
 
1970
 
 
1971
out:
 
1972
        return ret_val;
 
1973
}
 
1974
 
 
1975
/**
 
1976
 *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
 
1977
 *  @hw: pointer to the HW structure
 
1978
 *
 
1979
 *  Updates the EEPROM section checksums for all 4 ports by reading/adding
 
1980
 *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
 
1981
 *  checksum and writes the value to the EEPROM.
 
1982
 **/
 
1983
static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
 
1984
{
 
1985
        s32 ret_val = 0;
 
1986
        u16 j;
 
1987
        u16 nvm_offset;
 
1988
 
 
1989
        for (j = 0; j < 4; j++) {
 
1990
                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 
1991
                ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
 
1992
                if (ret_val != 0)
 
1993
                        goto out;
 
1994
        }
 
1995
 
 
1996
out:
 
1997
        return ret_val;
 
1998
}
 
1999
 
 
2000
/**
 
2001
 *  igb_set_eee_i350 - Enable/disable EEE support
 
2002
 *  @hw: pointer to the HW structure
 
2003
 *
 
2004
 *  Enable/disable EEE based on setting in dev_spec structure.
 
2005
 *
 
2006
 **/
 
2007
s32 igb_set_eee_i350(struct e1000_hw *hw)
 
2008
{
 
2009
        s32 ret_val = 0;
 
2010
        u32 ipcnfg, eeer, ctrl_ext;
 
2011
 
 
2012
        ctrl_ext = rd32(E1000_CTRL_EXT);
 
2013
        if ((hw->mac.type != e1000_i350) ||
 
2014
            (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
 
2015
                goto out;
 
2016
        ipcnfg = rd32(E1000_IPCNFG);
 
2017
        eeer = rd32(E1000_EEER);
 
2018
 
 
2019
        /* enable or disable per user setting */
 
2020
        if (!(hw->dev_spec._82575.eee_disable)) {
 
2021
                ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
 
2022
                        E1000_IPCNFG_EEE_100M_AN);
 
2023
                eeer |= (E1000_EEER_TX_LPI_EN |
 
2024
                        E1000_EEER_RX_LPI_EN |
 
2025
                        E1000_EEER_LPI_FC);
 
2026
 
 
2027
        } else {
 
2028
                ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
 
2029
                        E1000_IPCNFG_EEE_100M_AN);
 
2030
                eeer &= ~(E1000_EEER_TX_LPI_EN |
 
2031
                        E1000_EEER_RX_LPI_EN |
 
2032
                        E1000_EEER_LPI_FC);
 
2033
        }
 
2034
        wr32(E1000_IPCNFG, ipcnfg);
 
2035
        wr32(E1000_EEER, eeer);
 
2036
out:
 
2037
 
 
2038
        return ret_val;
 
2039
}
 
2040
 
1750
2041
static struct e1000_mac_operations e1000_mac_ops_82575 = {
1751
2042
        .init_hw              = igb_init_hw_82575,
1752
2043
        .check_for_link       = igb_check_for_link_82575,