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* QEMU PC System Emulator
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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#include "qemu/osdep.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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#include "hw/i386/apic.h"
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#include "hw/i386/topology.h"
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#include "sysemu/cpus.h"
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#include "hw/block/fdc.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/timer/hpet.h"
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#include "hw/smbios/smbios.h"
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#include "hw/loader.h"
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#include "multiboot.h"
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#include "hw/timer/mc146818rtc.h"
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#include "hw/timer/i8254.h"
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#include "hw/audio/pcspk.h"
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#include "hw/pci/msi.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/numa.h"
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#include "sysemu/kvm.h"
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#include "sysemu/qtest.h"
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#include "hw/xen/xen.h"
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#include "sysemu/block-backend.h"
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#include "hw/block/block.h"
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#include "ui/qemu-spice.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "sysemu/arch_init.h"
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#include "qemu/bitmap.h"
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#include "qemu/config-file.h"
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#include "qemu/error-report.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/cpu_hotplug.h"
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#include "hw/boards.h"
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#include "hw/pci/pci_host.h"
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#include "acpi-build.h"
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#include "hw/mem/pc-dimm.h"
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#include "qapi/visitor.h"
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#include "qapi-visit.h"
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#include "hw/i386/intel_iommu.h"
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/* debug PC/ISA interrupts */
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#define DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
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#define DPRINTF(fmt, ...)
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
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#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
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#define E820_NR_ENTRIES 16
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} QEMU_PACKED __attribute((__aligned__(4)));
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struct e820_entry entry[E820_NR_ENTRIES];
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} QEMU_PACKED __attribute((__aligned__(4)));
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static struct e820_table e820_reserve;
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static struct e820_entry *e820_table;
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static unsigned e820_entries;
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struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
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void gsi_handler(void *opaque, int n, int level)
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GSIState *s = opaque;
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DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
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if (n < ISA_NUM_IRQS) {
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qemu_set_irq(s->i8259_irq[n], level);
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qemu_set_irq(s->ioapic_irq[n], level);
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static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
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static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
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return 0xffffffffffffffffULL;
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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void pc_register_ferr_irq(qemu_irq irq)
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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qemu_irq_raise(ferr_irq);
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static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
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qemu_irq_lower(ferr_irq);
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static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
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return 0xffffffffffffffffULL;
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uint64_t cpu_get_tsc(CPUX86State *env)
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return cpu_get_ticks();
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int cpu_get_pic_interrupt(CPUX86State *env)
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X86CPU *cpu = x86_env_get_cpu(env);
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if (!kvm_irqchip_in_kernel()) {
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intno = apic_get_interrupt(cpu->apic_state);
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(cpu->apic_state)) {
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intno = pic_read_irq(isa_pic);
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static void pic_irq_request(void *opaque, int irq, int level)
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CPUState *cs = first_cpu;
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X86CPU *cpu = X86_CPU(cs);
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DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
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if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
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if (apic_accept_pic_intr(cpu->apic_state)) {
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apic_deliver_pic_intr(cpu->apic_state, level);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14
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int cmos_get_fd_drive_type(FloppyDriveType fd0)
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case FLOPPY_DRIVE_TYPE_144:
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/* 1.44 Mb 3"5 drive */
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case FLOPPY_DRIVE_TYPE_288:
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/* 2.88 Mb 3"5 drive */
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case FLOPPY_DRIVE_TYPE_120:
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/* 1.2 Mb 5"5 drive */
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case FLOPPY_DRIVE_TYPE_NONE:
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static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
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int16_t cylinders, int8_t heads, int8_t sectors)
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rtc_set_memory(s, type_ofs, 47);
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rtc_set_memory(s, info_ofs, cylinders);
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rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
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rtc_set_memory(s, info_ofs + 2, heads);
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rtc_set_memory(s, info_ofs + 3, 0xff);
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rtc_set_memory(s, info_ofs + 4, 0xff);
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rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
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rtc_set_memory(s, info_ofs + 6, cylinders);
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rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
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rtc_set_memory(s, info_ofs + 8, sectors);
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device)
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switch(boot_device) {
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return 0x01; /* floppy boot */
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return 0x02; /* hard drive boot */
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return 0x03; /* CD-ROM boot */
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return 0x04; /* Network boot */
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static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
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#define PC_MAX_BOOT_DEVICES 3
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int nbds, bds[3] = { 0, };
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nbds = strlen(boot_device);
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if (nbds > PC_MAX_BOOT_DEVICES) {
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error_setg(errp, "Too many boot devices for PC");
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for (i = 0; i < nbds; i++) {
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bds[i] = boot_device2nibble(boot_device[i]);
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error_setg(errp, "Invalid boot device for PC: '%c'",
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
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rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
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static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
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set_boot_dev(opaque, boot_device, errp);
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static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
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FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
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FLOPPY_DRIVE_TYPE_NONE };
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for (i = 0; i < 2; i++) {
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fd_type[i] = isa_fdc_get_drive_type(floppy, i);
303
val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
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cmos_get_fd_drive_type(fd_type[1]);
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rtc_set_memory(rtc_state, 0x10, val);
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val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
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if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
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if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
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val |= 0x01; /* 1 drive, ready for boot */
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val |= 0x41; /* 2 drives, ready for boot */
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rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
328
typedef struct pc_cmos_init_late_arg {
329
ISADevice *rtc_state;
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} pc_cmos_init_late_arg;
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typedef struct check_fdc_state {
338
static int check_fdc(Object *obj, void *opaque)
340
CheckFdcState *state = opaque;
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Error *local_err = NULL;
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fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
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iobase = object_property_get_int(obj, "iobase", &local_err);
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if (local_err || iobase != 0x3f0) {
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error_free(local_err);
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state->multiple = true;
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state->floppy = ISA_DEVICE(obj);
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static const char * const fdc_container_path[] = {
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"/unattached", "/peripheral", "/peripheral-anon"
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* Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
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ISADevice *pc_find_fdc0(void)
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CheckFdcState state = { 0 };
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for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
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container = container_get(qdev_get_machine(), fdc_container_path[i]);
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object_child_foreach(container, check_fdc, &state);
383
if (state.multiple) {
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error_report("warning: multiple floppy disk controllers with "
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"iobase=0x3f0 have been found");
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error_printf("the one being picked for CMOS setup might not reflect "
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static void pc_cmos_init_late(void *opaque)
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pc_cmos_init_late_arg *arg = opaque;
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ISADevice *s = arg->rtc_state;
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int8_t heads, sectors;
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if (ide_get_geometry(arg->idebus[0], 0,
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&cylinders, &heads, §ors) >= 0) {
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cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
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if (ide_get_geometry(arg->idebus[0], 1,
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&cylinders, &heads, §ors) >= 0) {
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cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
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rtc_set_memory(s, 0x12, val);
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for (i = 0; i < 4; i++) {
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/* NOTE: ide_get_geometry() returns the physical
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geometry. It is always such that: 1 <= sects <= 63, 1
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<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
420
geometry can be different if a translation is done. */
421
if (ide_get_geometry(arg->idebus[i / 2], i % 2,
422
&cylinders, &heads, §ors) >= 0) {
423
trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
424
assert((trans & ~3) == 0);
425
val |= trans << (i * 2);
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rtc_set_memory(s, 0x39, val);
430
pc_cmos_init_floppy(s, pc_find_fdc0());
432
qemu_unregister_reset(pc_cmos_init_late, opaque);
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void pc_cmos_init(PCMachineState *pcms,
436
BusState *idebus0, BusState *idebus1,
440
static pc_cmos_init_late_arg arg;
442
/* various important CMOS locations needed by PC/Bochs bios */
445
/* base memory (first MiB) */
446
val = MIN(pcms->below_4g_mem_size / 1024, 640);
447
rtc_set_memory(s, 0x15, val);
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rtc_set_memory(s, 0x16, val >> 8);
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/* extended memory (next 64MiB) */
450
if (pcms->below_4g_mem_size > 1024 * 1024) {
451
val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
457
rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8);
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rtc_set_memory(s, 0x30, val);
460
rtc_set_memory(s, 0x31, val >> 8);
461
/* memory between 16MiB and 4GiB */
462
if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
463
val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
469
rtc_set_memory(s, 0x34, val);
470
rtc_set_memory(s, 0x35, val >> 8);
471
/* memory above 4GiB */
472
val = pcms->above_4g_mem_size / 65536;
473
rtc_set_memory(s, 0x5b, val);
474
rtc_set_memory(s, 0x5c, val >> 8);
475
rtc_set_memory(s, 0x5d, val >> 16);
477
object_property_add_link(OBJECT(pcms), "rtc_state",
479
(Object **)&pcms->rtc,
480
object_property_allow_set_link,
481
OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
482
object_property_set_link(OBJECT(pcms), OBJECT(s),
483
"rtc_state", &error_abort);
485
set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
488
val |= 0x02; /* FPU is there */
489
val |= 0x04; /* PS/2 mouse installed */
490
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
492
/* hard drives and FDC */
494
arg.idebus[0] = idebus0;
495
arg.idebus[1] = idebus1;
496
qemu_register_reset(pc_cmos_init_late, &arg);
499
#define TYPE_PORT92 "port92"
500
#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
502
/* port 92 stuff: could be split off */
503
typedef struct Port92State {
504
ISADevice parent_obj;
511
static void port92_write(void *opaque, hwaddr addr, uint64_t val,
514
Port92State *s = opaque;
515
int oldval = s->outport;
517
DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
519
qemu_set_irq(s->a20_out, (val >> 1) & 1);
520
if ((val & 1) && !(oldval & 1)) {
521
qemu_system_reset_request();
525
static uint64_t port92_read(void *opaque, hwaddr addr,
528
Port92State *s = opaque;
532
DPRINTF("port92: read 0x%02x\n", ret);
536
static void port92_init(ISADevice *dev, qemu_irq a20_out)
538
qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
541
static const VMStateDescription vmstate_port92_isa = {
544
.minimum_version_id = 1,
545
.fields = (VMStateField[]) {
546
VMSTATE_UINT8(outport, Port92State),
547
VMSTATE_END_OF_LIST()
551
static void port92_reset(DeviceState *d)
553
Port92State *s = PORT92(d);
558
static const MemoryRegionOps port92_ops = {
560
.write = port92_write,
562
.min_access_size = 1,
563
.max_access_size = 1,
565
.endianness = DEVICE_LITTLE_ENDIAN,
568
static void port92_initfn(Object *obj)
570
Port92State *s = PORT92(obj);
572
memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
576
qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
579
static void port92_realizefn(DeviceState *dev, Error **errp)
581
ISADevice *isadev = ISA_DEVICE(dev);
582
Port92State *s = PORT92(dev);
584
isa_register_ioport(isadev, &s->io, 0x92);
587
static void port92_class_initfn(ObjectClass *klass, void *data)
589
DeviceClass *dc = DEVICE_CLASS(klass);
591
dc->realize = port92_realizefn;
592
dc->reset = port92_reset;
593
dc->vmsd = &vmstate_port92_isa;
595
* Reason: unlike ordinary ISA devices, this one needs additional
596
* wiring: its A20 output line needs to be wired up by
599
dc->cannot_instantiate_with_device_add_yet = true;
602
static const TypeInfo port92_info = {
604
.parent = TYPE_ISA_DEVICE,
605
.instance_size = sizeof(Port92State),
606
.instance_init = port92_initfn,
607
.class_init = port92_class_initfn,
610
static void port92_register_types(void)
612
type_register_static(&port92_info);
615
type_init(port92_register_types)
617
static void handle_a20_line_change(void *opaque, int irq, int level)
619
X86CPU *cpu = opaque;
621
/* XXX: send to all CPUs ? */
622
/* XXX: add logic to handle multiple A20 line sources */
623
x86_cpu_set_a20(cpu, level);
626
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
628
int index = le32_to_cpu(e820_reserve.count);
629
struct e820_entry *entry;
631
if (type != E820_RAM) {
632
/* old FW_CFG_E820_TABLE entry -- reservations only */
633
if (index >= E820_NR_ENTRIES) {
636
entry = &e820_reserve.entry[index++];
638
entry->address = cpu_to_le64(address);
639
entry->length = cpu_to_le64(length);
640
entry->type = cpu_to_le32(type);
642
e820_reserve.count = cpu_to_le32(index);
645
/* new "etc/e820" file -- include ram too */
646
e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
647
e820_table[e820_entries].address = cpu_to_le64(address);
648
e820_table[e820_entries].length = cpu_to_le64(length);
649
e820_table[e820_entries].type = cpu_to_le32(type);
655
int e820_get_num_entries(void)
660
bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
662
if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
663
*address = le64_to_cpu(e820_table[idx].address);
664
*length = le64_to_cpu(e820_table[idx].length);
670
/* Enables contiguous-apic-ID mode, for compatibility */
671
static bool compat_apic_id_mode;
673
void enable_compat_apic_id_mode(void)
675
compat_apic_id_mode = true;
678
/* Calculates initial APIC ID for a specific CPU index
680
* Currently we need to be able to calculate the APIC ID from the CPU index
681
* alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
682
* no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
683
* all CPUs up to max_cpus.
685
static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
690
correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
691
if (compat_apic_id_mode) {
692
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
693
error_report("APIC IDs set in compatibility mode, "
694
"CPU topology won't match the configuration");
703
static void pc_build_smbios(FWCfgState *fw_cfg)
705
uint8_t *smbios_tables, *smbios_anchor;
706
size_t smbios_tables_len, smbios_anchor_len;
707
struct smbios_phys_mem_area *mem_array;
708
unsigned i, array_count;
710
smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
712
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
713
smbios_tables, smbios_tables_len);
716
/* build the array of physical mem area from e820 table */
717
mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
718
for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
721
if (e820_get_entry(i, E820_RAM, &addr, &len)) {
722
mem_array[array_count].address = addr;
723
mem_array[array_count].length = len;
727
smbios_get_tables(mem_array, array_count,
728
&smbios_tables, &smbios_tables_len,
729
&smbios_anchor, &smbios_anchor_len);
733
fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
734
smbios_tables, smbios_tables_len);
735
fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
736
smbios_anchor, smbios_anchor_len);
740
static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
743
uint64_t *numa_fw_cfg;
746
fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
747
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
749
/* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
751
* For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
752
* building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
753
* that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
754
* for CPU hotplug also uses APIC ID and not "CPU index".
755
* This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
756
* but the "limit to the APIC ID values SeaBIOS may see".
758
* So for compatibility reasons with old BIOSes we are stuck with
759
* "etc/max-cpus" actually being apic_id_limit
761
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
762
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
763
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
764
acpi_tables, acpi_tables_len);
765
fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
767
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
768
&e820_reserve, sizeof(e820_reserve));
769
fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
770
sizeof(struct e820_entry) * e820_entries);
772
fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
773
/* allocate memory for the NUMA channel: one (64bit) word for the number
774
* of nodes, one word for each VCPU->node and one word for each node to
775
* hold the amount of memory.
777
numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
778
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
779
for (i = 0; i < max_cpus; i++) {
780
unsigned int apic_id = x86_cpu_apic_id_from_index(i);
781
assert(apic_id < pcms->apic_id_limit);
782
j = numa_get_node_for_cpu(i);
783
if (j < nb_numa_nodes) {
784
numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
787
for (i = 0; i < nb_numa_nodes; i++) {
788
numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
789
cpu_to_le64(numa_info[i].node_mem);
791
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
792
(1 + pcms->apic_id_limit + nb_numa_nodes) *
793
sizeof(*numa_fw_cfg));
798
static long get_file_size(FILE *f)
802
/* XXX: on Unix systems, using fstat() probably makes more sense */
805
fseek(f, 0, SEEK_END);
807
fseek(f, where, SEEK_SET);
812
/* setup_data types */
814
#define SETUP_E820_EXT 1
824
} __attribute__((packed));
826
static void load_linux(PCMachineState *pcms,
830
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
831
int dtb_size, setup_data_offset;
833
uint8_t header[8192], *setup, *kernel, *initrd_data;
834
hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
837
MachineState *machine = MACHINE(pcms);
838
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
839
struct setup_data *setup_data;
840
const char *kernel_filename = machine->kernel_filename;
841
const char *initrd_filename = machine->initrd_filename;
842
const char *dtb_filename = machine->dtb;
843
const char *kernel_cmdline = machine->kernel_cmdline;
845
/* Align to 16 bytes as a paranoia measure */
846
cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
848
/* load the kernel header */
849
f = fopen(kernel_filename, "rb");
850
if (!f || !(kernel_size = get_file_size(f)) ||
851
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
852
MIN(ARRAY_SIZE(header), kernel_size)) {
853
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
854
kernel_filename, strerror(errno));
858
/* kernel protocol version */
860
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
862
if (ldl_p(header+0x202) == 0x53726448) {
863
protocol = lduw_p(header+0x206);
865
/* This looks like a multiboot kernel. If it is, let's stop
866
treating it like a Linux kernel. */
867
if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
868
kernel_cmdline, kernel_size, header)) {
874
if (protocol < 0x200 || !(header[0x211] & 0x01)) {
877
cmdline_addr = 0x9a000 - cmdline_size;
879
} else if (protocol < 0x202) {
880
/* High but ancient kernel */
882
cmdline_addr = 0x9a000 - cmdline_size;
883
prot_addr = 0x100000;
885
/* High and recent kernel */
887
cmdline_addr = 0x20000;
888
prot_addr = 0x100000;
893
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
894
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
895
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
901
/* highest address for loading the initrd */
902
if (protocol >= 0x203) {
903
initrd_max = ldl_p(header+0x22c);
905
initrd_max = 0x37ffffff;
908
if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
909
initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
912
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
913
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
914
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
916
if (protocol >= 0x202) {
917
stl_p(header+0x228, cmdline_addr);
919
stw_p(header+0x20, 0xA33F);
920
stw_p(header+0x22, cmdline_addr-real_addr);
923
/* handle vga= parameter */
924
vmode = strstr(kernel_cmdline, "vga=");
926
unsigned int video_mode;
929
if (!strncmp(vmode, "normal", 6)) {
931
} else if (!strncmp(vmode, "ext", 3)) {
933
} else if (!strncmp(vmode, "ask", 3)) {
936
video_mode = strtol(vmode, NULL, 0);
938
stw_p(header+0x1fa, video_mode);
942
/* High nybble = B reserved for QEMU; low nybble is revision number.
943
If this code is substantially changed, you may want to consider
944
incrementing the revision. */
945
if (protocol >= 0x200) {
946
header[0x210] = 0xB0;
949
if (protocol >= 0x201) {
950
header[0x211] |= 0x80; /* CAN_USE_HEAP */
951
stw_p(header+0x224, cmdline_addr-real_addr-0x200);
955
if (initrd_filename) {
956
if (protocol < 0x200) {
957
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
961
initrd_size = get_image_size(initrd_filename);
962
if (initrd_size < 0) {
963
fprintf(stderr, "qemu: error reading initrd %s: %s\n",
964
initrd_filename, strerror(errno));
968
initrd_addr = (initrd_max-initrd_size) & ~4095;
970
initrd_data = g_malloc(initrd_size);
971
load_image(initrd_filename, initrd_data);
973
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
974
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
975
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
977
stl_p(header+0x218, initrd_addr);
978
stl_p(header+0x21c, initrd_size);
981
/* load kernel and setup */
982
setup_size = header[0x1f1];
983
if (setup_size == 0) {
986
setup_size = (setup_size+1)*512;
987
if (setup_size > kernel_size) {
988
fprintf(stderr, "qemu: invalid kernel header\n");
991
kernel_size -= setup_size;
993
setup = g_malloc(setup_size);
994
kernel = g_malloc(kernel_size);
995
fseek(f, 0, SEEK_SET);
996
if (fread(setup, 1, setup_size, f) != setup_size) {
997
fprintf(stderr, "fread() failed\n");
1000
if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1001
fprintf(stderr, "fread() failed\n");
1006
/* append dtb to kernel */
1008
if (protocol < 0x209) {
1009
fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1013
dtb_size = get_image_size(dtb_filename);
1014
if (dtb_size <= 0) {
1015
fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1016
dtb_filename, strerror(errno));
1020
setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1021
kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1022
kernel = g_realloc(kernel, kernel_size);
1024
stq_p(header+0x250, prot_addr + setup_data_offset);
1026
setup_data = (struct setup_data *)(kernel + setup_data_offset);
1027
setup_data->next = 0;
1028
setup_data->type = cpu_to_le32(SETUP_DTB);
1029
setup_data->len = cpu_to_le32(dtb_size);
1031
load_image_size(dtb_filename, setup_data->data, dtb_size);
1034
memcpy(setup, header, MIN(sizeof(header), setup_size));
1036
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1037
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1038
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1040
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1041
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1042
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1044
if (fw_cfg_dma_enabled(fw_cfg)) {
1045
option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1046
option_rom[nb_option_roms].bootindex = 0;
1048
option_rom[nb_option_roms].name = "linuxboot.bin";
1049
option_rom[nb_option_roms].bootindex = 0;
1054
#define NE2000_NB_MAX 6
1056
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1058
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1060
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1062
static int nb_ne2k = 0;
1064
if (nb_ne2k == NE2000_NB_MAX)
1066
isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1067
ne2000_irq[nb_ne2k], nd);
1071
DeviceState *cpu_get_current_apic(void)
1074
X86CPU *cpu = X86_CPU(current_cpu);
1075
return cpu->apic_state;
1081
void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1083
X86CPU *cpu = opaque;
1086
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1090
static X86CPU *pc_new_cpu(const char *typename, int64_t apic_id,
1094
Error *local_err = NULL;
1096
cpu = X86_CPU(object_new(typename));
1098
object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
1099
object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
1102
error_propagate(errp, local_err);
1103
object_unref(OBJECT(cpu));
1109
void pc_hot_add_cpu(const int64_t id, Error **errp)
1113
PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1114
int64_t apic_id = x86_cpu_apic_id_from_index(id);
1115
Error *local_err = NULL;
1118
error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1122
if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1123
error_setg(errp, "Unable to add CPU: %" PRIi64
1124
", resulting APIC ID (%" PRIi64 ") is too large",
1129
assert(pcms->possible_cpus->cpus[0].cpu); /* BSP is always present */
1130
oc = OBJECT_CLASS(CPU_GET_CLASS(pcms->possible_cpus->cpus[0].cpu));
1131
cpu = pc_new_cpu(object_class_get_name(oc), apic_id, &local_err);
1133
error_propagate(errp, local_err);
1136
object_unref(OBJECT(cpu));
1139
void pc_cpus_init(PCMachineState *pcms)
1144
const char *typename;
1145
gchar **model_pieces;
1147
MachineState *machine = MACHINE(pcms);
1150
if (machine->cpu_model == NULL) {
1151
#ifdef TARGET_X86_64
1152
machine->cpu_model = "qemu64";
1154
machine->cpu_model = "qemu32";
1158
model_pieces = g_strsplit(machine->cpu_model, ",", 2);
1159
if (!model_pieces[0]) {
1160
error_report("Invalid/empty CPU model name");
1164
oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]);
1166
error_report("Unable to find CPU definition: %s", model_pieces[0]);
1169
typename = object_class_get_name(oc);
1171
cc->parse_features(typename, model_pieces[1], &error_fatal);
1172
g_strfreev(model_pieces);
1174
/* Calculates the limit to CPU APIC ID values
1176
* Limit for the APIC ID value, so that all
1177
* CPU APIC IDs are < pcms->apic_id_limit.
1179
* This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1181
pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1182
pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1183
sizeof(CPUArchId) * max_cpus);
1184
for (i = 0; i < max_cpus; i++) {
1185
pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
1186
pcms->possible_cpus->len++;
1188
cpu = pc_new_cpu(typename, x86_cpu_apic_id_from_index(i),
1190
object_unref(OBJECT(cpu));
1194
/* tell smbios about cpuid version and features */
1195
smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1198
static void pc_build_feature_control_file(PCMachineState *pcms)
1200
X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu);
1201
CPUX86State *env = &cpu->env;
1202
uint32_t unused, ecx, edx;
1203
uint64_t feature_control_bits = 0;
1206
cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1207
if (ecx & CPUID_EXT_VMX) {
1208
feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1211
if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1212
(CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1213
(env->mcg_cap & MCG_LMCE_P)) {
1214
feature_control_bits |= FEATURE_CONTROL_LMCE;
1217
if (!feature_control_bits) {
1221
val = g_malloc(sizeof(*val));
1222
*val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1223
fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1226
static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1228
if (cpus_count > 0xff) {
1229
/* If the number of CPUs can't be represented in 8 bits, the
1230
* BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1231
* to make old BIOSes fail more predictably.
1233
rtc_set_memory(rtc, 0x5f, 0);
1235
rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1240
void pc_machine_done(Notifier *notifier, void *data)
1242
PCMachineState *pcms = container_of(notifier,
1243
PCMachineState, machine_done);
1244
PCIBus *bus = pcms->bus;
1246
/* set the number of CPUs */
1247
rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1250
int extra_hosts = 0;
1252
QLIST_FOREACH(bus, &bus->child, sibling) {
1253
/* look for expander root buses */
1254
if (pci_bus_is_root(bus)) {
1258
if (extra_hosts && pcms->fw_cfg) {
1259
uint64_t *val = g_malloc(sizeof(*val));
1260
*val = cpu_to_le64(extra_hosts);
1261
fw_cfg_add_file(pcms->fw_cfg,
1262
"etc/extra-pci-roots", val, sizeof(*val));
1268
pc_build_smbios(pcms->fw_cfg);
1269
pc_build_feature_control_file(pcms);
1270
/* update FW_CFG_NB_CPUS to account for -device added CPUs */
1271
fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1274
if (pcms->apic_id_limit > 255) {
1275
IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1277
if (!iommu || !iommu->x86_iommu.intr_supported ||
1278
iommu->intr_eim != ON_OFF_AUTO_ON) {
1279
error_report("current -smp configuration requires "
1280
"Extended Interrupt Mode enabled. "
1281
"You can add an IOMMU using: "
1282
"-device intel-iommu,intremap=on,eim=on");
1288
void pc_guest_info_init(PCMachineState *pcms)
1292
pcms->apic_xrupt_override = kvm_allows_irq0_override();
1293
pcms->numa_nodes = nb_numa_nodes;
1294
pcms->node_mem = g_malloc0(pcms->numa_nodes *
1295
sizeof *pcms->node_mem);
1296
for (i = 0; i < nb_numa_nodes; i++) {
1297
pcms->node_mem[i] = numa_info[i].node_mem;
1300
pcms->machine_done.notify = pc_machine_done;
1301
qemu_add_machine_init_done_notifier(&pcms->machine_done);
1304
/* setup pci memory address space mapping into system address space */
1305
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1306
MemoryRegion *pci_address_space)
1308
/* Set to lower priority than RAM */
1309
memory_region_add_subregion_overlap(system_memory, 0x0,
1310
pci_address_space, -1);
1313
void pc_acpi_init(const char *default_dsdt)
1317
if (acpi_tables != NULL) {
1318
/* manually set via -acpitable, leave it alone */
1322
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1323
if (filename == NULL) {
1324
fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1326
QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1330
qemu_opt_set(opts, "file", filename, &error_abort);
1332
acpi_table_add_builtin(opts, &err);
1334
error_reportf_err(err, "WARNING: failed to load %s: ",
1341
void xen_load_linux(PCMachineState *pcms)
1346
assert(MACHINE(pcms)->kernel_filename != NULL);
1348
fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1349
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1352
load_linux(pcms, fw_cfg);
1353
for (i = 0; i < nb_option_roms; i++) {
1354
assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1355
!strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1356
!strcmp(option_rom[i].name, "multiboot.bin"));
1357
rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1359
pcms->fw_cfg = fw_cfg;
1362
void pc_memory_init(PCMachineState *pcms,
1363
MemoryRegion *system_memory,
1364
MemoryRegion *rom_memory,
1365
MemoryRegion **ram_memory)
1368
MemoryRegion *ram, *option_rom_mr;
1369
MemoryRegion *ram_below_4g, *ram_above_4g;
1371
MachineState *machine = MACHINE(pcms);
1372
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1374
assert(machine->ram_size == pcms->below_4g_mem_size +
1375
pcms->above_4g_mem_size);
1377
linux_boot = (machine->kernel_filename != NULL);
1379
/* Allocate RAM. We allocate it as a single memory region and use
1380
* aliases to address portions of it, mostly for backwards compatibility
1381
* with older qemus that used qemu_ram_alloc().
1383
ram = g_malloc(sizeof(*ram));
1384
memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1387
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1388
memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1389
0, pcms->below_4g_mem_size);
1390
memory_region_add_subregion(system_memory, 0, ram_below_4g);
1391
e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1392
if (pcms->above_4g_mem_size > 0) {
1393
ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1394
memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1395
pcms->below_4g_mem_size,
1396
pcms->above_4g_mem_size);
1397
memory_region_add_subregion(system_memory, 0x100000000ULL,
1399
e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1402
if (!pcmc->has_reserved_memory &&
1403
(machine->ram_slots ||
1404
(machine->maxram_size > machine->ram_size))) {
1405
MachineClass *mc = MACHINE_GET_CLASS(machine);
1407
error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1412
/* initialize hotplug memory address space */
1413
if (pcmc->has_reserved_memory &&
1414
(machine->ram_size < machine->maxram_size)) {
1415
ram_addr_t hotplug_mem_size =
1416
machine->maxram_size - machine->ram_size;
1418
if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1419
error_report("unsupported amount of memory slots: %"PRIu64,
1420
machine->ram_slots);
1424
if (QEMU_ALIGN_UP(machine->maxram_size,
1425
TARGET_PAGE_SIZE) != machine->maxram_size) {
1426
error_report("maximum memory size must by aligned to multiple of "
1427
"%d bytes", TARGET_PAGE_SIZE);
1431
pcms->hotplug_memory.base =
1432
ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
1434
if (pcmc->enforce_aligned_dimm) {
1435
/* size hotplug region assuming 1G page max alignment per slot */
1436
hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
1439
if ((pcms->hotplug_memory.base + hotplug_mem_size) <
1441
error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1442
machine->maxram_size);
1446
memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms),
1447
"hotplug-memory", hotplug_mem_size);
1448
memory_region_add_subregion(system_memory, pcms->hotplug_memory.base,
1449
&pcms->hotplug_memory.mr);
1452
/* Initialize PC system firmware */
1453
pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1455
option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1456
memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1458
vmstate_register_ram_global(option_rom_mr);
1459
memory_region_add_subregion_overlap(rom_memory,
1464
fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1468
if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) {
1469
uint64_t *val = g_malloc(sizeof(*val));
1470
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1471
uint64_t res_mem_end = pcms->hotplug_memory.base;
1473
if (!pcmc->broken_reserved_end) {
1474
res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
1476
*val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
1477
fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1481
load_linux(pcms, fw_cfg);
1484
for (i = 0; i < nb_option_roms; i++) {
1485
rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1487
pcms->fw_cfg = fw_cfg;
1489
/* Init default IOAPIC address space */
1490
pcms->ioapic_as = &address_space_memory;
1493
qemu_irq pc_allocate_cpu_irq(void)
1495
return qemu_allocate_irq(pic_irq_request, NULL, 0);
1498
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1500
DeviceState *dev = NULL;
1502
rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1504
PCIDevice *pcidev = pci_vga_init(pci_bus);
1505
dev = pcidev ? &pcidev->qdev : NULL;
1506
} else if (isa_bus) {
1507
ISADevice *isadev = isa_vga_init(isa_bus);
1508
dev = isadev ? DEVICE(isadev) : NULL;
1510
rom_reset_order_override();
1514
static const MemoryRegionOps ioport80_io_ops = {
1515
.write = ioport80_write,
1516
.read = ioport80_read,
1517
.endianness = DEVICE_NATIVE_ENDIAN,
1519
.min_access_size = 1,
1520
.max_access_size = 1,
1524
static const MemoryRegionOps ioportF0_io_ops = {
1525
.write = ioportF0_write,
1526
.read = ioportF0_read,
1527
.endianness = DEVICE_NATIVE_ENDIAN,
1529
.min_access_size = 1,
1530
.max_access_size = 1,
1534
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1535
ISADevice **rtc_state,
1541
DriveInfo *fd[MAX_FD];
1542
DeviceState *hpet = NULL;
1543
int pit_isa_irq = 0;
1544
qemu_irq pit_alt_irq = NULL;
1545
qemu_irq rtc_irq = NULL;
1547
ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1548
MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1549
MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1551
memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1552
memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1554
memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1555
memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1558
* Check if an HPET shall be created.
1560
* Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1561
* when the HPET wants to take over. Thus we have to disable the latter.
1563
if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1564
/* In order to set property, here not using sysbus_try_create_simple */
1565
hpet = qdev_try_create(NULL, TYPE_HPET);
1567
/* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1568
* and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1571
uint8_t compat = object_property_get_int(OBJECT(hpet),
1574
qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1576
qdev_init_nofail(hpet);
1577
sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1579
for (i = 0; i < GSI_NUM_PINS; i++) {
1580
sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1583
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1584
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1587
*rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1589
qemu_register_boot_set(pc_boot_set, *rtc_state);
1591
if (!xen_enabled()) {
1592
if (kvm_pit_in_kernel()) {
1593
pit = kvm_pit_init(isa_bus, 0x40);
1595
pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1598
/* connect PIT to output control line of the HPET */
1599
qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1601
pcspk_init(isa_bus, pit);
1604
serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS);
1605
parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1607
a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1608
i8042 = isa_create_simple(isa_bus, "i8042");
1609
i8042_setup_a20_line(i8042, a20_line[0]);
1611
vmport_init(isa_bus);
1612
vmmouse = isa_try_create(isa_bus, "vmmouse");
1617
DeviceState *dev = DEVICE(vmmouse);
1618
qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1619
qdev_init_nofail(dev);
1621
port92 = isa_create_simple(isa_bus, "port92");
1622
port92_init(port92, a20_line[1]);
1625
DMA_init(isa_bus, 0);
1627
for(i = 0; i < MAX_FD; i++) {
1628
fd[i] = drive_get(IF_FLOPPY, 0, i);
1629
create_fdctrl |= !!fd[i];
1631
if (create_fdctrl) {
1632
fdctrl_init_isa(isa_bus, fd);
1636
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1640
rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1641
for (i = 0; i < nb_nics; i++) {
1642
NICInfo *nd = &nd_table[i];
1644
if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1645
pc_init_ne2k_isa(isa_bus, nd);
1647
pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1650
rom_reset_order_override();
1653
void pc_pci_device_init(PCIBus *pci_bus)
1658
max_bus = drive_get_max_bus(IF_SCSI);
1659
for (bus = 0; bus <= max_bus; bus++) {
1660
pci_create_simple(pci_bus, -1, "lsi53c895a");
1664
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1670
if (kvm_ioapic_in_kernel()) {
1671
dev = qdev_create(NULL, "kvm-ioapic");
1673
dev = qdev_create(NULL, "ioapic");
1676
object_property_add_child(object_resolve_path(parent_name, NULL),
1677
"ioapic", OBJECT(dev), NULL);
1679
qdev_init_nofail(dev);
1680
d = SYS_BUS_DEVICE(dev);
1681
sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1683
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1684
gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1688
static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1689
DeviceState *dev, Error **errp)
1691
HotplugHandlerClass *hhc;
1692
Error *local_err = NULL;
1693
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1694
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1695
PCDIMMDevice *dimm = PC_DIMM(dev);
1696
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1697
MemoryRegion *mr = ddc->get_memory_region(dimm);
1698
uint64_t align = TARGET_PAGE_SIZE;
1700
if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) {
1701
align = memory_region_get_alignment(mr);
1704
if (!pcms->acpi_dev) {
1705
error_setg(&local_err,
1706
"memory hotplug is not enabled: missing acpi device");
1710
pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err);
1715
if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1716
nvdimm_plug(&pcms->acpi_nvdimm_state);
1719
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1720
hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1722
error_propagate(errp, local_err);
1725
static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev,
1726
DeviceState *dev, Error **errp)
1728
HotplugHandlerClass *hhc;
1729
Error *local_err = NULL;
1730
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1732
if (!pcms->acpi_dev) {
1733
error_setg(&local_err,
1734
"memory hotplug is not enabled: missing acpi device");
1738
if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1739
error_setg(&local_err,
1740
"nvdimm device hot unplug is not supported yet.");
1744
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1745
hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1748
error_propagate(errp, local_err);
1751
static void pc_dimm_unplug(HotplugHandler *hotplug_dev,
1752
DeviceState *dev, Error **errp)
1754
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1755
PCDIMMDevice *dimm = PC_DIMM(dev);
1756
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1757
MemoryRegion *mr = ddc->get_memory_region(dimm);
1758
HotplugHandlerClass *hhc;
1759
Error *local_err = NULL;
1761
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1762
hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1768
pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr);
1769
object_unparent(OBJECT(dev));
1772
error_propagate(errp, local_err);
1775
static int pc_apic_cmp(const void *a, const void *b)
1777
CPUArchId *apic_a = (CPUArchId *)a;
1778
CPUArchId *apic_b = (CPUArchId *)b;
1780
return apic_a->arch_id - apic_b->arch_id;
1783
/* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1784
* in pcms->possible_cpus->cpus, if pcms->possible_cpus->cpus has no
1785
* entry correponding to CPU's apic_id returns NULL.
1787
static CPUArchId *pc_find_cpu_slot(PCMachineState *pcms, CPUState *cpu,
1790
CPUClass *cc = CPU_GET_CLASS(cpu);
1791
CPUArchId apic_id, *found_cpu;
1793
apic_id.arch_id = cc->get_arch_id(CPU(cpu));
1794
found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus,
1795
pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus),
1797
if (found_cpu && idx) {
1798
*idx = found_cpu - pcms->possible_cpus->cpus;
1803
static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1804
DeviceState *dev, Error **errp)
1806
CPUArchId *found_cpu;
1807
HotplugHandlerClass *hhc;
1808
Error *local_err = NULL;
1809
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1811
if (pcms->acpi_dev) {
1812
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1813
hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1819
/* increment the number of CPUs */
1821
if (dev->hotplugged) {
1822
rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1823
fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1826
found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL);
1827
found_cpu->cpu = CPU(dev);
1829
error_propagate(errp, local_err);
1831
static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1832
DeviceState *dev, Error **errp)
1835
HotplugHandlerClass *hhc;
1836
Error *local_err = NULL;
1837
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1839
pc_find_cpu_slot(pcms, CPU(dev), &idx);
1842
error_setg(&local_err, "Boot CPU is unpluggable");
1846
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1847
hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1854
error_propagate(errp, local_err);
1858
static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1859
DeviceState *dev, Error **errp)
1861
CPUArchId *found_cpu;
1862
HotplugHandlerClass *hhc;
1863
Error *local_err = NULL;
1864
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1866
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1867
hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1873
found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL);
1874
found_cpu->cpu = NULL;
1875
object_unparent(OBJECT(dev));
1877
/* decrement the number of CPUs */
1879
/* Update the number of CPUs in CMOS */
1880
rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1881
fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1883
error_propagate(errp, local_err);
1886
static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1887
DeviceState *dev, Error **errp)
1891
CPUArchId *cpu_slot;
1892
X86CPUTopoInfo topo;
1893
X86CPU *cpu = X86_CPU(dev);
1894
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1896
/* if APIC ID is not set, set it based on socket/core/thread properties */
1897
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1898
int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1900
if (cpu->socket_id < 0) {
1901
error_setg(errp, "CPU socket-id is not set");
1903
} else if (cpu->socket_id > max_socket) {
1904
error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1905
cpu->socket_id, max_socket);
1908
if (cpu->core_id < 0) {
1909
error_setg(errp, "CPU core-id is not set");
1911
} else if (cpu->core_id > (smp_cores - 1)) {
1912
error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1913
cpu->core_id, smp_cores - 1);
1916
if (cpu->thread_id < 0) {
1917
error_setg(errp, "CPU thread-id is not set");
1919
} else if (cpu->thread_id > (smp_threads - 1)) {
1920
error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1921
cpu->thread_id, smp_threads - 1);
1925
topo.pkg_id = cpu->socket_id;
1926
topo.core_id = cpu->core_id;
1927
topo.smt_id = cpu->thread_id;
1928
cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
1931
cpu_slot = pc_find_cpu_slot(pcms, CPU(dev), &idx);
1933
x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1934
error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1935
" APIC ID %" PRIu32 ", valid index range 0:%d",
1936
topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
1937
pcms->possible_cpus->len - 1);
1941
if (cpu_slot->cpu) {
1942
error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1947
/* if 'address' properties socket-id/core-id/thread-id are not set, set them
1948
* so that query_hotpluggable_cpus would show correct values
1950
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1951
* once -smp refactoring is complete and there will be CPU private
1952
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1953
x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1954
if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1955
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1956
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1959
cpu->socket_id = topo.pkg_id;
1961
if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1962
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1963
" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1966
cpu->core_id = topo.core_id;
1968
if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1969
error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1970
" 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1973
cpu->thread_id = topo.smt_id;
1976
cs->cpu_index = idx;
1979
static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1980
DeviceState *dev, Error **errp)
1982
if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1983
pc_cpu_pre_plug(hotplug_dev, dev, errp);
1987
static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1988
DeviceState *dev, Error **errp)
1990
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1991
pc_dimm_plug(hotplug_dev, dev, errp);
1992
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1993
pc_cpu_plug(hotplug_dev, dev, errp);
1997
static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1998
DeviceState *dev, Error **errp)
2000
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2001
pc_dimm_unplug_request(hotplug_dev, dev, errp);
2002
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2003
pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2005
error_setg(errp, "acpi: device unplug request for not supported device"
2006
" type: %s", object_get_typename(OBJECT(dev)));
2010
static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2011
DeviceState *dev, Error **errp)
2013
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2014
pc_dimm_unplug(hotplug_dev, dev, errp);
2015
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2016
pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2018
error_setg(errp, "acpi: device unplug for not supported device"
2019
" type: %s", object_get_typename(OBJECT(dev)));
2023
static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2026
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
2028
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2029
object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2030
return HOTPLUG_HANDLER(machine);
2033
return pcmc->get_hotplug_handler ?
2034
pcmc->get_hotplug_handler(machine, dev) : NULL;
2038
pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v,
2039
const char *name, void *opaque,
2042
PCMachineState *pcms = PC_MACHINE(obj);
2043
int64_t value = memory_region_size(&pcms->hotplug_memory.mr);
2045
visit_type_int(v, name, &value, errp);
2048
static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2049
const char *name, void *opaque,
2052
PCMachineState *pcms = PC_MACHINE(obj);
2053
uint64_t value = pcms->max_ram_below_4g;
2055
visit_type_size(v, name, &value, errp);
2058
static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2059
const char *name, void *opaque,
2062
PCMachineState *pcms = PC_MACHINE(obj);
2063
Error *error = NULL;
2066
visit_type_size(v, name, &value, &error);
2068
error_propagate(errp, error);
2071
if (value > (1ULL << 32)) {
2073
"Machine option 'max-ram-below-4g=%"PRIu64
2074
"' expects size less than or equal to 4G", value);
2075
error_propagate(errp, error);
2079
if (value < (1ULL << 20)) {
2080
error_report("Warning: small max_ram_below_4g(%"PRIu64
2081
") less than 1M. BIOS may not work..",
2085
pcms->max_ram_below_4g = value;
2088
static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2089
void *opaque, Error **errp)
2091
PCMachineState *pcms = PC_MACHINE(obj);
2092
OnOffAuto vmport = pcms->vmport;
2094
visit_type_OnOffAuto(v, name, &vmport, errp);
2097
static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2098
void *opaque, Error **errp)
2100
PCMachineState *pcms = PC_MACHINE(obj);
2102
visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2105
bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2107
bool smm_available = false;
2109
if (pcms->smm == ON_OFF_AUTO_OFF) {
2113
if (tcg_enabled() || qtest_enabled()) {
2114
smm_available = true;
2115
} else if (kvm_enabled()) {
2116
smm_available = kvm_has_smm();
2119
if (smm_available) {
2123
if (pcms->smm == ON_OFF_AUTO_ON) {
2124
error_report("System Management Mode not supported by this hypervisor.");
2130
static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2131
void *opaque, Error **errp)
2133
PCMachineState *pcms = PC_MACHINE(obj);
2134
OnOffAuto smm = pcms->smm;
2136
visit_type_OnOffAuto(v, name, &smm, errp);
2139
static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2140
void *opaque, Error **errp)
2142
PCMachineState *pcms = PC_MACHINE(obj);
2144
visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2147
static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2149
PCMachineState *pcms = PC_MACHINE(obj);
2151
return pcms->acpi_nvdimm_state.is_enabled;
2154
static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2156
PCMachineState *pcms = PC_MACHINE(obj);
2158
pcms->acpi_nvdimm_state.is_enabled = value;
2161
static void pc_machine_initfn(Object *obj)
2163
PCMachineState *pcms = PC_MACHINE(obj);
2165
pcms->max_ram_below_4g = 0; /* use default */
2166
pcms->smm = ON_OFF_AUTO_AUTO;
2167
pcms->vmport = ON_OFF_AUTO_AUTO;
2168
/* nvdimm is disabled on default. */
2169
pcms->acpi_nvdimm_state.is_enabled = false;
2170
/* acpi build is enabled by default if machine supports it */
2171
pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2174
static void pc_machine_reset(void)
2179
qemu_devices_reset();
2181
/* Reset APIC after devices have been reset to cancel
2182
* any changes that qemu_devices_reset() might have done.
2187
if (cpu->apic_state) {
2188
device_reset(cpu->apic_state);
2193
static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index)
2195
X86CPUTopoInfo topo;
2196
x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index,
2201
static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine)
2203
PCMachineState *pcms = PC_MACHINE(machine);
2204
int len = sizeof(CPUArchIdList) +
2205
sizeof(CPUArchId) * (pcms->possible_cpus->len);
2206
CPUArchIdList *list = g_malloc(len);
2208
memcpy(list, pcms->possible_cpus, len);
2212
static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
2216
HotpluggableCPUList *head = NULL;
2217
PCMachineState *pcms = PC_MACHINE(machine);
2218
const char *cpu_type;
2220
cpu = pcms->possible_cpus->cpus[0].cpu;
2221
assert(cpu); /* BSP is always present */
2222
cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu)));
2224
for (i = 0; i < pcms->possible_cpus->len; i++) {
2225
X86CPUTopoInfo topo;
2226
HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2227
HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2228
CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2229
const uint32_t apic_id = pcms->possible_cpus->cpus[i].arch_id;
2231
x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo);
2233
cpu_item->type = g_strdup(cpu_type);
2234
cpu_item->vcpus_count = 1;
2235
cpu_props->has_socket_id = true;
2236
cpu_props->socket_id = topo.pkg_id;
2237
cpu_props->has_core_id = true;
2238
cpu_props->core_id = topo.core_id;
2239
cpu_props->has_thread_id = true;
2240
cpu_props->thread_id = topo.smt_id;
2241
cpu_item->props = cpu_props;
2243
cpu = pcms->possible_cpus->cpus[i].cpu;
2245
cpu_item->has_qom_path = true;
2246
cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu));
2249
list_item->value = cpu_item;
2250
list_item->next = head;
2256
static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2258
/* cpu index isn't used */
2262
X86CPU *cpu = X86_CPU(cs);
2264
if (!cpu->apic_state) {
2265
cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2267
apic_deliver_nmi(cpu->apic_state);
2272
static void pc_machine_class_init(ObjectClass *oc, void *data)
2274
MachineClass *mc = MACHINE_CLASS(oc);
2275
PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2276
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2277
NMIClass *nc = NMI_CLASS(oc);
2279
pcmc->get_hotplug_handler = mc->get_hotplug_handler;
2280
pcmc->pci_enabled = true;
2281
pcmc->has_acpi_build = true;
2282
pcmc->rsdp_in_ram = true;
2283
pcmc->smbios_defaults = true;
2284
pcmc->smbios_uuid_encoded = true;
2285
pcmc->gigabyte_align = true;
2286
pcmc->has_reserved_memory = true;
2287
pcmc->kvmclock_enabled = true;
2288
pcmc->enforce_aligned_dimm = true;
2289
/* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2290
* to be used at the moment, 32K should be enough for a while. */
2291
pcmc->acpi_data_size = 0x20000 + 0x8000;
2292
pcmc->save_tsc_khz = true;
2293
mc->get_hotplug_handler = pc_get_hotpug_handler;
2294
mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
2295
mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2296
mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus;
2297
mc->default_boot_order = "cad";
2298
mc->hot_add_cpu = pc_hot_add_cpu;
2300
mc->reset = pc_machine_reset;
2301
hc->pre_plug = pc_machine_device_pre_plug_cb;
2302
hc->plug = pc_machine_device_plug_cb;
2303
hc->unplug_request = pc_machine_device_unplug_request_cb;
2304
hc->unplug = pc_machine_device_unplug_cb;
2305
nc->nmi_monitor_handler = x86_nmi;
2307
object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int",
2308
pc_machine_get_hotplug_memory_region_size, NULL,
2309
NULL, NULL, &error_abort);
2311
object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2312
pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2313
NULL, NULL, &error_abort);
2315
object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2316
"Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2318
object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2319
pc_machine_get_smm, pc_machine_set_smm,
2320
NULL, NULL, &error_abort);
2321
object_class_property_set_description(oc, PC_MACHINE_SMM,
2322
"Enable SMM (pc & q35)", &error_abort);
2324
object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2325
pc_machine_get_vmport, pc_machine_set_vmport,
2326
NULL, NULL, &error_abort);
2327
object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2328
"Enable vmport (pc & q35)", &error_abort);
2330
object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2331
pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2334
static const TypeInfo pc_machine_info = {
2335
.name = TYPE_PC_MACHINE,
2336
.parent = TYPE_MACHINE,
2338
.instance_size = sizeof(PCMachineState),
2339
.instance_init = pc_machine_initfn,
2340
.class_size = sizeof(PCMachineClass),
2341
.class_init = pc_machine_class_init,
2342
.interfaces = (InterfaceInfo[]) {
2343
{ TYPE_HOTPLUG_HANDLER },
2349
static void pc_machine_register_types(void)
2351
type_register_static(&pc_machine_info);
2354
type_init(pc_machine_register_types)