~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

reserved-names = "ibm,slw-image", "ibm,slw-image", "ibm,firmware-stacks", "ibm,firmware-data", "ibm,firmware-heap", "ibm,firmware-code", "memory@400000000";

131

reserved-ranges = <0x7 0xfe600000 0x0 0x100000 0x7 0xfe200000 0x0 0x100000 0x0 0x31e00000 0x0 0x3e0000 0x0 0x31000000 0x0 0xe00000 0x0 0x30400000 0x0 0xc00000 0x0 0x30000000 0x0 0x400000 0x4 0x0 0x0 0x600450>;

132

133

/* Mandatory */

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cpus {

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#address-cells = <0x1>;

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#size-cells = <0x0>;

137

138

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* The following node must exist for each *core* in the system. The unit

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* address (number after the @) is the hexadecimal HW CPU number (PIR value)

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* of thread 0 of that core.

142

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PowerPC,POWER8@20 {

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/* mandatory/standard properties */

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device_type = "cpu";

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64-bit;

147

32-64-bridge;

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graphics;

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general-purpose;

150

151

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* The "status" property indicate whether the core is functional. It's

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* a string containing "okay" for a good core or "bad" for a non-functional

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* one. You can also just ommit the non-functional ones from the DT

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status = "okay";

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158

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* This is the same value as the PIR of thread 0 of that core

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* (ie same as the @xx part of the node name)

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reg = <0x20>;

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164

/* same as above */

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ibm,pir = <0x20>;

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/* chip ID of this core */

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ibm,chip-id = <0x0>;

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170

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* interrupt server numbers (aka HW processor numbers) of all threads

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* on that core. This should have 8 numbers and the first one should

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* have the same value as the above ibm,pir and reg properties

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ibm,ppc-interrupt-server#s = <0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27>;

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177

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* This is the "architected processor version" as defined in PAPR. Just

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* stick to 0x0f000004 for P8 and things will be fine

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cpu-version = <0x0f000004>;

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* These are various definitions of the page sizes and segment sizes

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* supported by the MMU, those values are fine for P8 for now

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ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>;

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ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>;

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ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>;

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* Similarly that might need to be reviewed later but will do for now...

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ibm,pa-features = [0x6 0x0 0xf6 0x3f 0xc7 0x0 0x80 0xc0];

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/* SLB size, use as-is */

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ibm,slb-size = <0x20>;

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/* VSX support, use as-is */

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ibm,vmx = <0x2>;

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/* DFP support, use as-is */

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ibm,dfp = <0x2>;

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/* PURR/SPURR support, use as-is */

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ibm,purr = <0x1>;

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ibm,spurr = <0x1>;

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* Old-style core clock frequency. Only create this property if the frequency fits

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* in a 32-bit number. Do not create it if it doesn't

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clock-frequency = <0xf5552d00>;

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* mandatory: 64-bit version of the core clock frequency, always create this

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* property.

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ibm,extended-clock-frequency = <0x0 0xf5552d00>;

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/* Timebase freq has a fixed value, always use that */

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timebase-frequency = <0x1e848000>;

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/* Same */

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ibm,extended-timebase-frequency = <0x0 0x1e848000>;

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/* Use as-is, values might need to be adjusted but that will do for now */

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reservation-granule-size = <0x80>;

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d-tlb-size = <0x800>;

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i-tlb-size = <0x0>;

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tlb-size = <0x800>;

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d-tlb-sets = <0x4>;

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i-tlb-sets = <0x0>;

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tlb-sets = <0x4>;

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d-cache-block-size = <0x80>;

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i-cache-block-size = <0x80>;

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d-cache-size = <0x10000>;

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i-cache-size = <0x8000>;

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i-cache-sets = <0x4>;

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d-cache-sets = <0x8>;

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performance-monitor = <0x0 0x1>;

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* optional: phandle of the node representing the L2 cache for this core,

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* note: it can also be named "next-level-cache", Linux will support both

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* and Sapphire doesn't currently use those properties, just passes them

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* along to Linux

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l2-cache = < 0x4 >;

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};

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* Cache nodes. Those are siblings of the processor nodes under /cpus and

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* represent the various level of caches.

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* The unit address (and reg property) is mostly free-for-all as long as

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* there is no collisions. On HDAT machines we use the following encoding

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* which I encourage you to also follow to limit surprises:

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* L2 : (0x20 << 24) | PIR (PIR is PIR value of thread 0 of core)

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* L3 : (0x30 << 24) | PIR

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* L3.5 : (0x35 << 24) | PIR

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* In addition, each cache points to the next level cache via its

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* own "l2-cache" (or "next-level-cache") property, so the core node

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* points to the L2, the L2 points to the L3 etc...

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l2-cache@20000020 {

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phandle = <0x4>;

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device_type = "cache";

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reg = <0x20000020>;

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status = "okay";

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cache-unified;

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d-cache-sets = <0x8>;

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i-cache-sets = <0x8>;

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d-cache-size = <0x80000>;

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i-cache-size = <0x80000>;

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l2-cache = <0x5>;

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};

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l3-cache@30000020 {

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phandle = <0x5>;

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device_type = "cache";

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reg = <0x30000020>;

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status = "bad";

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cache-unified;

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d-cache-sets = <0x8>;

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i-cache-sets = <0x8>;

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d-cache-size = <0x800000>;

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i-cache-size = <0x800000>;

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};

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};

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* Interrupt presentation controller (ICP) nodes

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* There is some flexibility as to how many of these are presents since

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* a given node can represent multiple ICPs. When generating from HDAT we

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* chose to create one per core

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interrupt-controller@3ffff80020000 {

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/* Mandatory */

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compatible = "IBM,ppc-xicp", "IBM,power8-icp";

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interrupt-controller;

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#address-cells = <0x0>;

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device_type = "PowerPC-External-Interrupt-Presentation";

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* Range of HW CPU IDs represented by that node. In this example

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* the core starting at PIR 0x20 and 8 threads, which corresponds

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* to the CPU node of the example above. The property in theory

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* supports multiple ranges but Linux doesn't.

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ibm,interrupt-server-ranges = <0x20 0x8>;

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* For each server in the above range, the physical address of the

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* ICP register block and its size. Since the root node #address-cells

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* and #size-cells properties are both "2", each entry is thus

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* 2 cells address and 2 cells size (64-bit each).

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reg = <0x3ffff 0x80020000 0x0 0x1000 0x3ffff 0x80021000 0x0 0x1000 0x3ffff 0x80022000 0x0 0x1000 0x3ffff 0x80023000 0x0 0x1000 0x3ffff 0x80024000 0x0 0x1000 0x3ffff 0x80025000 0x0 0x1000 0x3ffff 0x80026000 0x0 0x1000 0x3ffff 0x80027000 0x0 0x1000>;

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};

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* The "memory" nodes represent physical memory in the system. They

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* do not represent DIMMs, memory controllers or Centaurs, thus will

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* be expressed separately.

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* In order to be able to handle affinity properly, we require that

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* a memory node is created for each range of memory that has a different

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* "affinity", which in practice means for each chip since we don't

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* support memory interleaved across multiple chips on P8.

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* Additionally, it is *not* required that one chip = one memory node,

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* it is perfectly acceptable to break down the memory of one chip into

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* multiple memory nodes (typically skiboot does that if the two MCs

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* are not interlaved).

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memory@0 {

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device_type = "memory";

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* We support multiple entries in the ibm,chip-id property for

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* memory nodes in case the memory is interleaved across multiple

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* chips but that shouldn't happen on P8

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ibm,chip-id = <0x0>;

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/* The "reg" property is 4 cells, as usual for a child of

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* the root node, 2 cells of address and 2 cells of size

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reg = <0x0 0x0 0x4 0x0>;

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};

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* The XSCOM node. This is the closest thing to a "chip" node we have.

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* there must be one per chip in the system (thus a DCM has two) and

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* while it represents the "parent" of various devices on the PIB/PCB

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* that we want to expose, it is also used to store all sort of

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* miscellaneous per-chip information on HDAT based systems (such

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* as VPDs).

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xscom@3fc0000000000 {

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/* standard & mandatory */

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#address-cells = <0x1>;

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#size-cells = <0x1>;

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scom-controller;

371

compatible = "ibm,xscom", "ibm,power8-xscom";

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/* The chip ID as usual ... */

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ibm,chip-id = <0x0>;

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/* The base address of xscom for that chip */

377

reg = <0x3fc00 0x0 0x8 0x0>;

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* This comes from HDAT and I *think* is the raw content of the

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* module VPD eeprom (and thus doesn't have a standard ASCII keyword

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* VPD format). We don't currently use it though ...

383

384

ibm,module-vpd = < ... big pile of binary data ... >;

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/* PSI host bridge XSCOM register set */

387

psihb@2010900 {

388

reg = <0x2010900 0x20>;

389

compatible = "ibm,power8-psihb-x", "ibm,psihb-x";

390

};

391

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/* Chip TOD XSCOM register set */

393

chiptod@40000 {

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reg = <0x40000 0x34>;

395

compatible = "ibm,power-chiptod", "ibm,power8-chiptod";

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397

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* Create that property with no value if this chip has

399

* the Primary TOD in the topology. If it has the secondary

400

* one (backup master ?) use "secondary".

401

402

primary;

403

};

404

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/* NX XSCOM register set */

406

nx@2010000 {

407

reg = <0x2010000 0x4000>;

408

compatible = "ibm,power-nx", "ibm,power8-nx";

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};

410

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* PCI "PE Master" XSCOM register set for each active PHB

413

414

* For now, do *not* create these if the PHB isn't connected,

415

* clocked, or the PHY/HSS not configured.

416

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pbcq@2012000 {

418

reg = <0x2012000 0x20 0x9012000 0x5 0x9013c00 0x15>;

419

compatible = "ibm,power8-pbcq";

420

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/* Indicate the PHB index on the chip, ie, 0,1 or 2 */

422

ibm,phb-index = <0x0>;

423

424

/* Create that property to use the IBM-style "A/B" dual input

425

* slot presence detect mechanism.

426

427

ibm,use-ab-detect;

428

429

430

* TBD: Lane equalization values. Not currently used by

431

* skiboot but will have to be sorted out

432

433

ibm,lane_eq = <0x0>;

434

};

435

436

pbcq@2012400 {

437

reg = <0x2012400 0x20 0x9012400 0x5 0x9013c40 0x15>;

438

compatible = "ibm,power8-pbcq";

439

ibm,phb-index = <0x1>;

440

ibm,use-ab-detect;

441

ibm,lane_eq = <0x0>;

442

};

443

444

445

* Here's the LPC bus. Ideally each chip has one but in

446

* practice it's ok to only populate the ones actually

447

* used for something. This is not an exact representation

448

* of HW, in that case we would have eccb -> opb -> lpc,

449

* but instead we just have an lpc node and the address is

450

* the base of the ECCB register set for it

451

452

* Devices on the LPC are represented as children nodes,

453

* see example below for a standard UART.

454

455

lpc@b0020 {

456

457

* Empty property indicating this is the primary

458

* LPC bus. It will be used for the default UART

459

* if any and this is the bus that will be used

460

* by Linux as the virtual 64k of IO ports

461

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primary;

463

464

465

* 2 cells of address, the first one indicates the

466

* address type, see below

467

468

#address-cells = <0x2>;

469

#size-cells = <0x1>;

470

reg = <0xb0020 0x4>;

471

compatible = "ibm,power8-lpc";

472

473

474

* Example device: a UART on IO ports.

475

476

* LPC address have 2 cells. The first cell is the

477

* address type as follow:

478

479

* 0 : LPC memory space

480

* 1 : LPC IO space

481

* 2: LPC FW space

482

483

* (This corresponds to the OPAL_LPC_* arguments

484

* passed to the opal_lpc_read/write functions)

485

486

* The unit address follows the old ISA convention

487

* for open firmware which prefixes IO ports with "i".

488

489

* (This is not critical and can be 1,3f8 if that's

490

* problematic to generate)

491

492

serial@i3f8 {

493

reg = <0x1 0x3f8 8>;

494

compatible = "ns16550", "pnpPNP,501";

495

496

/* Baud rate generator base frequency */

497

clock-frequency = < 1843200 >;

498

499

/* Default speed to use */

500

current-speed = < 115200 >;

501

502

/* Historical, helps Linux */

503

device_type = "serial";

504

505

506

* Indicate which chip ID the interrupt

507

* is routed to (we assume it will always

508

* be the "host error interrupt" (aka

509

* "TPM interrupt" of that chip).

510

511

ibm,irq-chip-id = <0x0>;

512

}

513

};

514

};

515

};

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