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Viewing changes to roms/u-boot/arch/arm/cpu/armv7/am33xx/mem.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/arch/arm/cpu/armv7/am33xx/mem.c
 
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/*
 
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 * (C) Copyright 2010
 
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 * Texas Instruments, <www.ti.com>
 
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 *
 
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 * Author :
 
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 *     Mansoor Ahamed <mansoor.ahamed@ti.com>
 
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 *
 
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 * Initial Code from:
 
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 *     Manikandan Pillai <mani.pillai@ti.com>
 
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 *     Richard Woodruff <r-woodruff2@ti.com>
 
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 *     Syed Mohammed Khasim <khasim@ti.com>
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/io.h>
 
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#include <asm/arch/cpu.h>
 
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#include <asm/arch/mem.h>
 
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#include <asm/arch/sys_proto.h>
 
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#include <command.h>
 
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struct gpmc *gpmc_cfg;
 
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 
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                        u32 size)
 
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{
 
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        writel(0, &cs->config7);
 
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        sdelay(1000);
 
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        /* Delay for settling */
 
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        writel(gpmc_config[0], &cs->config1);
 
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        writel(gpmc_config[1], &cs->config2);
 
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        writel(gpmc_config[2], &cs->config3);
 
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        writel(gpmc_config[3], &cs->config4);
 
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        writel(gpmc_config[4], &cs->config5);
 
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        writel(gpmc_config[5], &cs->config6);
 
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        /* Enable the config */
 
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        writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
 
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                (1 << 6)), &cs->config7);
 
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        sdelay(2000);
 
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}
 
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/*****************************************************
 
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 * gpmc_init(): init gpmc bus
 
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 * Init GPMC for x16, MuxMode (SDRAM in x32).
 
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 * This code can only be executed from SRAM or SDRAM.
 
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 *****************************************************/
 
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void gpmc_init(void)
 
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{
 
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        /* putting a blanket check on GPMC based on ZeBu for now */
 
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        gpmc_cfg = (struct gpmc *)GPMC_BASE;
 
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#if defined(CONFIG_NOR)
 
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/* configure GPMC for NOR */
 
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        const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
 
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                                                STNOR_GPMC_CONFIG2,
 
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                                                STNOR_GPMC_CONFIG3,
 
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                                                STNOR_GPMC_CONFIG4,
 
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                                                STNOR_GPMC_CONFIG5,
 
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                                                STNOR_GPMC_CONFIG6,
 
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                                                STNOR_GPMC_CONFIG7
 
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                                                };
 
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        u32 size = GPMC_SIZE_16M;
 
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        u32 base = CONFIG_SYS_FLASH_BASE;
 
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#elif defined(CONFIG_NAND)
 
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/* configure GPMC for NAND */
 
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        const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
 
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                                                M_NAND_GPMC_CONFIG2,
 
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                                                M_NAND_GPMC_CONFIG3,
 
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                                                M_NAND_GPMC_CONFIG4,
 
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                                                M_NAND_GPMC_CONFIG5,
 
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                                                M_NAND_GPMC_CONFIG6,
 
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                                                0
 
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                                                };
 
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        u32 size = GPMC_SIZE_256M;
 
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        u32 base = CONFIG_SYS_NAND_BASE;
 
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#else
 
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        const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
 
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        u32 size = 0;
 
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        u32 base = 0;
 
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#endif
 
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        /* global settings */
 
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        writel(0x00000008, &gpmc_cfg->sysconfig);
 
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        writel(0x00000000, &gpmc_cfg->irqstatus);
 
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        writel(0x00000000, &gpmc_cfg->irqenable);
 
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#ifdef CONFIG_NOR
 
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        writel(0x00000200, &gpmc_cfg->config);
 
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#else
 
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        writel(0x00000012, &gpmc_cfg->config);
 
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#endif
 
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        /*
 
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         * Disable the GPMC0 config set by ROM code
 
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         */
 
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        writel(0, &gpmc_cfg->cs[0].config7);
 
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        sdelay(1000);
 
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        /* enable chip-select specific configurations */
 
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        enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 
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}