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Viewing changes to roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
 
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/*
 
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 * Copyright (C) 2013 Atmel Corporation
 
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 *                    Bo Shen <voice.shen@atmel.com>
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#ifndef __ATMEL_MPDDRC_H__
 
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#define __ATMEL_MPDDRC_H__
 
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/*
 
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 * Only define the needed register in mpddr
 
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 * If other register needed, will add them later
 
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 */
 
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struct atmel_mpddr {
 
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        u32 mr;
 
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        u32 rtr;
 
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        u32 cr;
 
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        u32 tpr0;
 
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        u32 tpr1;
 
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        u32 tpr2;
 
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        u32 reserved[2];
 
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        u32 md;
 
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};
 
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int ddr2_init(const unsigned int ram_address,
 
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               const struct atmel_mpddr *mpddr);
 
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/* Bit field in mode register */
 
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#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD         0x0
 
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#define ATMEL_MPDDRC_MR_MODE_NOP_CMD            0x1
 
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#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD        0x2
 
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#define ATMEL_MPDDRC_MR_MODE_LMR_CMD            0x3
 
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#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD           0x4
 
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#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD        0x5
 
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#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD           0x6
 
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#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD         0x7
 
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/* Bit field in configuration register */
 
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#define ATMEL_MPDDRC_CR_NC_MASK                 0x3
 
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#define ATMEL_MPDDRC_CR_NC_COL_9                0x0
 
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#define ATMEL_MPDDRC_CR_NC_COL_10               0x1
 
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#define ATMEL_MPDDRC_CR_NC_COL_11               0x2
 
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#define ATMEL_MPDDRC_CR_NC_COL_12               0x3
 
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#define ATMEL_MPDDRC_CR_NR_MASK                 (0x3 << 2)
 
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#define ATMEL_MPDDRC_CR_NR_ROW_11               (0x0 << 2)
 
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#define ATMEL_MPDDRC_CR_NR_ROW_12               (0x1 << 2)
 
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#define ATMEL_MPDDRC_CR_NR_ROW_13               (0x2 << 2)
 
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#define ATMEL_MPDDRC_CR_NR_ROW_14               (0x3 << 2)
 
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#define ATMEL_MPDDRC_CR_CAS_MASK                (0x7 << 4)
 
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#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2            (0x2 << 4)
 
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#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3            (0x3 << 4)
 
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#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4            (0x4 << 4)
 
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#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5            (0x5 << 4)
 
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#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6            (0x6 << 4)
 
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#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED       (0x1 << 7)
 
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#define ATMEL_MPDDRC_CR_DIC_DS                  (0x1 << 8)
 
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#define ATMEL_MPDDRC_CR_DIS_DLL                 (0x1 << 9)
 
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#define ATMEL_MPDDRC_CR_OCD_DEFAULT             (0x7 << 12)
 
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#define ATMEL_MPDDRC_CR_ENRDM_ON                (0x1 << 17)
 
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#define ATMEL_MPDDRC_CR_NB_8BANKS               (0x1 << 20)
 
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#define ATMEL_MPDDRC_CR_NDQS_DISABLED           (0x1 << 21)
 
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#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED       (0x1 << 22)
 
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#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED          (0x1 << 23)
 
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/* Bit field in timing parameter 0 register */
 
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#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET           0
 
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#define ATMEL_MPDDRC_TPR0_TRAS_MASK             0xf
 
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#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET           4
 
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#define ATMEL_MPDDRC_TPR0_TRCD_MASK             0xf
 
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#define ATMEL_MPDDRC_TPR0_TWR_OFFSET            8
 
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#define ATMEL_MPDDRC_TPR0_TWR_MASK              0xf
 
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#define ATMEL_MPDDRC_TPR0_TRC_OFFSET            12
 
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#define ATMEL_MPDDRC_TPR0_TRC_MASK              0xf
 
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#define ATMEL_MPDDRC_TPR0_TRP_OFFSET            16
 
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#define ATMEL_MPDDRC_TPR0_TRP_MASK              0xf
 
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#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET           20
 
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#define ATMEL_MPDDRC_TPR0_TRRD_MASK             0xf
 
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#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET           24
 
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#define ATMEL_MPDDRC_TPR0_TWTR_MASK             0x7
 
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#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET       27
 
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#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK         0x1
 
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#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET           28
 
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#define ATMEL_MPDDRC_TPR0_TMRD_MASK             0xf
 
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/* Bit field in timing parameter 1 register */
 
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#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET           0
 
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#define ATMEL_MPDDRC_TPR1_TRFC_MASK             0x7f
 
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#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET          8
 
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#define ATMEL_MPDDRC_TPR1_TXSNR_MASK            0xff
 
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#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET          16
 
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#define ATMEL_MPDDRC_TPR1_TXSRD_MASK            0xff
 
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#define ATMEL_MPDDRC_TPR1_TXP_OFFSET            24
 
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#define ATMEL_MPDDRC_TPR1_TXP_MASK              0xf
 
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/* Bit field in timing parameter 2 register */
 
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#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET          0
 
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#define ATMEL_MPDDRC_TPR2_TXARD_MASK            0xf
 
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#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET         4
 
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#define ATMEL_MPDDRC_TPR2_TXARDS_MASK           0xf
 
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#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET           8
 
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#define ATMEL_MPDDRC_TPR2_TRPA_MASK             0xf
 
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#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET           12
 
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#define ATMEL_MPDDRC_TPR2_TRTP_MASK             0x7
 
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#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET           16
 
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#define ATMEL_MPDDRC_TPR2_TFAW_MASK             0xf
 
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/* Bit field in Memory Device Register */
 
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#define ATMEL_MPDDRC_MD_LPDDR_SDRAM     0x3
 
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#define ATMEL_MPDDRC_MD_DDR2_SDRAM      0x6
 
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#define ATMEL_MPDDRC_MD_DBW_MASK        (0x1 << 4)
 
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#define ATMEL_MPDDRC_MD_DBW_32_BITS     (0x0 << 4)
 
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#define ATMEL_MPDDRC_MD_DBW_16_BITS     (0x1 << 4)
 
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#endif