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Viewing changes to roms/u-boot/board/freescale/p1023rdb/ddr.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/freescale/p1023rdb/ddr.c
 
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/*
 
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 * Copyright 2013 Freescale Semiconductor, Inc.
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/mmu.h>
 
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#include <asm/immap_85xx.h>
 
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#include <asm/processor.h>
 
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#include <fsl_ddr_sdram.h>
 
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#include <fsl_ddr_dimm_params.h>
 
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#include <asm/io.h>
 
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#include <asm/fsl_law.h>
 
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DECLARE_GLOBAL_DATA_PTR;
 
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/* CONFIG_SYS_DDR_RAW_TIMING */
 
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/*
 
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 * Hynix H5TQ1G83TFR-H9C
 
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 */
 
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dimm_params_t ddr_raw_timing = {
 
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        .n_ranks = 1,
 
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        .rank_density = 536870912u,
 
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        .capacity = 536870912u,
 
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        .primary_sdram_width = 32,
 
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        .ec_sdram_width = 0,
 
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        .registered_dimm = 0,
 
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        .mirrored_dimm = 0,
 
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        .n_row_addr = 14,
 
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        .n_col_addr = 10,
 
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        .n_banks_per_sdram_device = 8,
 
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        .edc_config = 0,
 
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        .burst_lengths_bitmask = 0x0c,
 
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        .tckmin_x_ps = 1875,
 
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        .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
 
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        .taa_ps = 13125,
 
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        .twr_ps = 18000,
 
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        .trcd_ps = 13125,
 
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        .trrd_ps = 7500,
 
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        .trp_ps = 13125,
 
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        .tras_ps = 37500,
 
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        .trc_ps = 50625,
 
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        .trfc_ps = 160000,
 
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        .twtr_ps = 7500,
 
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        .trtp_ps = 7500,
 
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        .refresh_rate_ps = 7800000,
 
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        .tfaw_ps = 37500,
 
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};
 
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 
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                unsigned int controller_number,
 
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                unsigned int dimm_number)
 
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{
 
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        const char dimm_model[] = "Fixed DDR on board";
 
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        if ((controller_number == 0) && (dimm_number == 0)) {
 
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                memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 
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                memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 
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                memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 
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        }
 
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        return 0;
 
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}
 
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void fsl_ddr_board_options(memctl_options_t *popts,
 
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                                dimm_params_t *pdimm,
 
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                                unsigned int ctrl_num)
 
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{
 
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        int i;
 
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        popts->clk_adjust = 6;
 
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        popts->cpo_override = 0x1f;
 
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        popts->write_data_delay = 2;
 
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        popts->half_strength_driver_enable = 1;
 
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        /* Write leveling override */
 
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        popts->wrlvl_en = 1;
 
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        popts->wrlvl_override = 1;
 
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        popts->wrlvl_sample = 0xf;
 
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        popts->wrlvl_start = 0x8;
 
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        popts->trwt_override = 1;
 
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        popts->trwt = 0;
 
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        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 
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                popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 
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                popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 
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        }
 
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}