← Back to branch summary

~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

« back to all changes in this revision

Viewing changes to roms/u-boot/board/xes/xpedite537x/tlb.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

Show diffs side-by-side

added added

removed removed

Lines of Context:
roms/u-boot/board/xes/xpedite537x/tlb.c
 
1
/*
 
2
 * Copyright 2008 Extreme Engineering Solutions, Inc.
 
3
 * Copyright 2008 Freescale Semiconductor, Inc.
 
4
 *
 
5
 * (C) Copyright 2000
 
6
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
7
 *
 
8
 * SPDX-License-Identifier:     GPL-2.0+
 
9
 */
 
10
 
 
11
#include <common.h>
 
12
#include <asm/mmu.h>
 
13
 
 
14
struct fsl_e_tlb_entry tlb_table[] = {
 
15
        /* TLB 0 - for temp stack in cache */
 
16
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 
17
                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
18
                0, 0, BOOKE_PAGESZ_4K, 0),
 
19
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 
20
                CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 
21
                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
22
                0, 0, BOOKE_PAGESZ_4K, 0),
 
23
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 
24
                CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 
25
                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
26
                0, 0, BOOKE_PAGESZ_4K, 0),
 
27
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 
28
                CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 
29
                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
30
                0, 0, BOOKE_PAGESZ_4K, 0),
 
31
 
 
32
        /* W**G* - NOR flashes */
 
33
        /* This will be changed to *I*G* after relocation to RAM. */
 
34
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
 
35
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 
36
                0, 0, BOOKE_PAGESZ_256M, 1),
 
37
 
 
38
        /* *I*G* - CCSRBAR */
 
39
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 
40
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
41
                0, 1, BOOKE_PAGESZ_1M, 1),
 
42
 
 
43
        /* *I*G* - NAND flash */
 
44
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
 
45
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
46
                0, 2, BOOKE_PAGESZ_1M, 1),
 
47
 
 
48
        /* **M** - Boot page for secondary processors */
 
49
        SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
 
50
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 
51
                0, 3, BOOKE_PAGESZ_4K, 1),
 
52
 
 
53
#ifdef CONFIG_PCIE1
 
54
        /* *I*G* - PCIe */
 
55
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
 
56
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
57
                0, 4, BOOKE_PAGESZ_1G, 1),
 
58
#endif
 
59
 
 
60
#ifdef CONFIG_PCIE2
 
61
        /* *I*G* - PCIe */
 
62
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
 
63
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
64
                0, 5, BOOKE_PAGESZ_256M, 1),
 
65
#endif
 
66
 
 
67
#ifdef CONFIG_PCIE3
 
68
        /* *I*G* - PCIe */
 
69
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
 
70
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
71
                0, 6, BOOKE_PAGESZ_256M, 1),
 
72
#endif
 
73
 
 
74
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
 
75
        /* *I*G* - PCIe */
 
76
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
 
77
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
78
                0, 7, BOOKE_PAGESZ_64M, 1),
 
79
#endif
 
80
 
 
81
};
 
82
 
 
83
int num_tlb_entries = ARRAY_SIZE(tlb_table);