2
* Copyright (c) 2011 The Chromium OS Authors.
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* SPDX-License-Identifier: GPL-2.0+
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#include "usb_ether.h"
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/* ASIX AX8817X based USB 2.0 Ethernet Devices */
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#define AX_CMD_SET_SW_MII 0x06
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#define AX_CMD_READ_MII_REG 0x07
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#define AX_CMD_WRITE_MII_REG 0x08
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#define AX_CMD_SET_HW_MII 0x0a
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#define AX_CMD_READ_EEPROM 0x0b
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#define AX_CMD_READ_RX_CTL 0x0f
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#define AX_CMD_WRITE_RX_CTL 0x10
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#define AX_CMD_WRITE_IPG0 0x12
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#define AX_CMD_READ_NODE_ID 0x13
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#define AX_CMD_WRITE_NODE_ID 0x14
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#define AX_CMD_READ_PHY_ID 0x19
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#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
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#define AX_CMD_WRITE_GPIOS 0x1f
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#define AX_CMD_SW_RESET 0x20
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#define AX_CMD_SW_PHY_SELECT 0x22
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#define AX_SWRESET_CLEAR 0x00
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#define AX_SWRESET_PRTE 0x04
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#define AX_SWRESET_PRL 0x08
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#define AX_SWRESET_IPRL 0x20
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#define AX_SWRESET_IPPD 0x40
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#define AX88772_IPG0_DEFAULT 0x15
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#define AX88772_IPG1_DEFAULT 0x0c
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#define AX88772_IPG2_DEFAULT 0x12
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/* AX88772 & AX88178 Medium Mode Register */
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#define AX_MEDIUM_PF 0x0080
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#define AX_MEDIUM_JFE 0x0040
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#define AX_MEDIUM_TFC 0x0020
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#define AX_MEDIUM_RFC 0x0010
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#define AX_MEDIUM_ENCK 0x0008
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#define AX_MEDIUM_AC 0x0004
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#define AX_MEDIUM_FD 0x0002
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#define AX_MEDIUM_GM 0x0001
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#define AX_MEDIUM_SM 0x1000
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#define AX_MEDIUM_SBP 0x0800
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#define AX_MEDIUM_PS 0x0200
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#define AX_MEDIUM_RE 0x0100
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#define AX88178_MEDIUM_DEFAULT \
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(AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
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AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
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#define AX88772_MEDIUM_DEFAULT \
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(AX_MEDIUM_FD | AX_MEDIUM_RFC | \
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AX_MEDIUM_TFC | AX_MEDIUM_PS | \
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AX_MEDIUM_AC | AX_MEDIUM_RE)
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/* AX88772 & AX88178 RX_CTL values */
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#define AX_RX_CTL_SO 0x0080
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#define AX_RX_CTL_AB 0x0008
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#define AX_DEFAULT_RX_CTL \
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(AX_RX_CTL_SO | AX_RX_CTL_AB)
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#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
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#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
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#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
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#define ASIX_BASE_NAME "asx"
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#define USB_CTRL_SET_TIMEOUT 5000
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#define USB_CTRL_GET_TIMEOUT 5000
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#define USB_BULK_SEND_TIMEOUT 5000
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#define USB_BULK_RECV_TIMEOUT 5000
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#define AX_RX_URB_SIZE 2048
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#define PHY_CONNECT_TIMEOUT 5000
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/* asix_flags defines */
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#define FLAG_TYPE_AX88172 (1U << 0)
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#define FLAG_TYPE_AX88772 (1U << 1)
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#define FLAG_TYPE_AX88772B (1U << 2)
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#define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
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static int curr_eth_dev; /* index for name of next device detected */
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* Asix infrastructure commands
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static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
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u16 size, void *data)
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debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
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"size=%d\n", cmd, value, index, size);
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len = usb_control_msg(
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usb_sndctrlpipe(dev->pusb_dev, 0),
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USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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USB_CTRL_SET_TIMEOUT);
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return len == size ? 0 : -1;
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static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
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u16 size, void *data)
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debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
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cmd, value, index, size);
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len = usb_control_msg(
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usb_rcvctrlpipe(dev->pusb_dev, 0),
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USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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USB_CTRL_GET_TIMEOUT);
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return len == size ? 0 : -1;
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static inline int asix_set_sw_mii(struct ueth_data *dev)
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ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
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debug("Failed to enable software MII access\n");
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static inline int asix_set_hw_mii(struct ueth_data *dev)
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ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
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debug("Failed to enable hardware MII access\n");
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static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
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ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
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asix_set_sw_mii(dev);
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asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
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asix_set_hw_mii(dev);
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debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
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phy_id, loc, le16_to_cpu(*res));
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return le16_to_cpu(*res);
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asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
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ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
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*res = cpu_to_le16(val);
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debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
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asix_set_sw_mii(dev);
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asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
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asix_set_hw_mii(dev);
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* Asix "high level" commands
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static int asix_sw_reset(struct ueth_data *dev, u8 flags)
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ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
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debug("Failed to send software reset: %02x\n", ret);
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static inline int asix_get_phy_addr(struct ueth_data *dev)
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ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
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int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
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debug("asix_get_phy_addr()\n");
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debug("Error reading PHYID register: %02x\n", ret);
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debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
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static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
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debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
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debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
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static u16 asix_read_rx_ctl(struct ueth_data *dev)
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ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
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int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
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debug("Error reading RX_CTL register: %02x\n", ret);
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ret = le16_to_cpu(*v);
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static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
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debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
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debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
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static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
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debug("asix_write_gpio() - value = 0x%04x\n", value);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
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debug("Failed to write GPIO value 0x%04x: %02x\n",
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udelay(sleep * 1000);
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static int asix_write_hwaddr(struct eth_device *eth)
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
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memcpy(buf, eth->enetaddr, ETH_ALEN);
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ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
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debug("Failed to set MAC address: %02x\n", ret);
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* mii_nway_restart - restart NWay (autonegotiation) for this interface
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* Returns 0 on success, negative on error.
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static int mii_nway_restart(struct ueth_data *dev)
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/* if autoneg is off, it's an error */
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bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
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if (bmcr & BMCR_ANENABLE) {
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bmcr |= BMCR_ANRESTART;
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asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
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static int asix_read_mac(struct eth_device *eth)
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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struct asix_private *priv = (struct asix_private *)dev->dev_priv;
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
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if (priv->flags & FLAG_EEPROM_MAC) {
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for (i = 0; i < (ETH_ALEN >> 1); i++) {
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if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
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0x04 + i, 0, 2, buf) < 0) {
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debug("Failed to read SROM address 04h.\n");
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memcpy((eth->enetaddr + i * 2), buf, 2);
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if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
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debug("Failed to read MAC address.\n");
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memcpy(eth->enetaddr, buf, ETH_ALEN);
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static int asix_basic_reset(struct ueth_data *dev)
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if (asix_write_gpio(dev,
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AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
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/* 0x10 is the phy id of the embedded 10/100 ethernet phy */
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embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
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if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
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embd_phy, 0, 0, NULL) < 0) {
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debug("Select PHY #1 failed\n");
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if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
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if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
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if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
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if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
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rx_ctl = asix_read_rx_ctl(dev);
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debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
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if (asix_write_rx_ctl(dev, 0x0000) < 0)
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rx_ctl = asix_read_rx_ctl(dev);
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debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
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dev->phy_id = asix_get_phy_addr(dev);
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debug("Failed to read phy id\n");
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asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
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asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
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ADVERTISE_ALL | ADVERTISE_CSMA);
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mii_nway_restart(dev);
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if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
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if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
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AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
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AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
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debug("Write IPG,IPG1,IPG2 failed\n");
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static int asix_init(struct eth_device *eth, bd_t *bd)
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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#define TIMEOUT_RESOLUTION 50 /* ms */
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debug("** %s()\n", __func__);
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if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
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link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
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if (!link_detected) {
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printf("Waiting for Ethernet connection... ");
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udelay(TIMEOUT_RESOLUTION * 1000);
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timeout += TIMEOUT_RESOLUTION;
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} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
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printf("unable to connect.\n");
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static int asix_send(struct eth_device *eth, void *packet, int length)
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
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PKTSIZE + sizeof(packet_len));
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debug("** %s(), len %d\n", __func__, length);
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packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
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cpu_to_le32s(&packet_len);
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memcpy(msg, &packet_len, sizeof(packet_len));
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memcpy(msg + sizeof(packet_len), (void *)packet, length);
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err = usb_bulk_msg(dev->pusb_dev,
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usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
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length + sizeof(packet_len),
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USB_BULK_SEND_TIMEOUT);
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debug("Tx: len = %u, actual = %u, err = %d\n",
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length + sizeof(packet_len), actual_len, err);
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static int asix_recv(struct eth_device *eth)
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
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unsigned char *buf_ptr;
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debug("** %s()\n", __func__);
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err = usb_bulk_msg(dev->pusb_dev,
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usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
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USB_BULK_RECV_TIMEOUT);
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debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
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debug("Rx: failed to receive\n");
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if (actual_len > AX_RX_URB_SIZE) {
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debug("Rx: received too many bytes %d\n", actual_len);
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while (actual_len > 0) {
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* 1st 4 bytes contain the length of the actual data as two
516
* complementary 16-bit words. Extract the length of the data.
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if (actual_len < sizeof(packet_len)) {
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debug("Rx: incomplete packet length\n");
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memcpy(&packet_len, buf_ptr, sizeof(packet_len));
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le32_to_cpus(&packet_len);
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if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
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debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
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packet_len, (~packet_len >> 16) & 0x7ff,
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packet_len = packet_len & 0x7ff;
531
if (packet_len > actual_len - sizeof(packet_len)) {
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debug("Rx: too large packet: %d\n", packet_len);
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/* Notify net stack */
537
NetReceive(buf_ptr + sizeof(packet_len), packet_len);
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/* Adjust for next iteration. Packets are padded to 16-bits */
542
actual_len -= sizeof(packet_len) + packet_len;
543
buf_ptr += sizeof(packet_len) + packet_len;
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static void asix_halt(struct eth_device *eth)
551
debug("** %s()\n", __func__);
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* Asix probing functions
557
void asix_eth_before_probe(void)
563
unsigned short vendor;
564
unsigned short product;
568
static const struct asix_dongle const asix_dongles[] = {
569
{ 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
570
{ 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
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{ 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */
572
/* Cables-to-Go USB Ethernet Adapter */
573
{ 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
574
{ 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
575
{ 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
576
{ 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
577
{ 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
578
{ 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
579
/* DLink DUB-E100 H/W Ver B1 Alternate */
580
{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
582
{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
583
{ 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
586
/* Probe to see if a new device is actually an asix device */
587
int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
588
struct ueth_data *ss)
590
struct usb_interface *iface;
591
struct usb_interface_descriptor *iface_desc;
592
int ep_in_found = 0, ep_out_found = 0;
595
/* let's examine the device now */
596
iface = &dev->config.if_desc[ifnum];
597
iface_desc = &dev->config.if_desc[ifnum].desc;
599
for (i = 0; asix_dongles[i].vendor != 0; i++) {
600
if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
601
dev->descriptor.idProduct == asix_dongles[i].product)
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/* Found a supported dongle */
606
if (asix_dongles[i].vendor == 0)
609
memset(ss, 0, sizeof(struct ueth_data));
611
/* At this point, we know we've got a live one */
612
debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
613
dev->descriptor.idVendor, dev->descriptor.idProduct);
615
/* Initialize the ueth_data structure with some useful info */
618
ss->subclass = iface_desc->bInterfaceSubClass;
619
ss->protocol = iface_desc->bInterfaceProtocol;
621
/* alloc driver private */
622
ss->dev_priv = calloc(1, sizeof(struct asix_private));
626
((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
629
* We are expecting a minimum of 3 endpoints - in, out (bulk), and
630
* int. We will ignore any others.
632
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
633
/* is it an BULK endpoint? */
634
if ((iface->ep_desc[i].bmAttributes &
635
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
636
u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
637
if (ep_addr & USB_DIR_IN) {
639
ss->ep_in = ep_addr &
640
USB_ENDPOINT_NUMBER_MASK;
645
ss->ep_out = ep_addr &
646
USB_ENDPOINT_NUMBER_MASK;
652
/* is it an interrupt endpoint? */
653
if ((iface->ep_desc[i].bmAttributes &
654
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
655
ss->ep_int = iface->ep_desc[i].bEndpointAddress &
656
USB_ENDPOINT_NUMBER_MASK;
657
ss->irqinterval = iface->ep_desc[i].bInterval;
660
debug("Endpoints In %d Out %d Int %d\n",
661
ss->ep_in, ss->ep_out, ss->ep_int);
663
/* Do some basic sanity checks, and bail if we find a problem */
664
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
665
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
666
debug("Problems with device\n");
669
dev->privptr = (void *)ss;
673
int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
674
struct eth_device *eth)
676
struct asix_private *priv = (struct asix_private *)ss->dev_priv;
679
debug("%s: missing parameter.\n", __func__);
682
sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
683
eth->init = asix_init;
684
eth->send = asix_send;
685
eth->recv = asix_recv;
686
eth->halt = asix_halt;
687
if (!(priv->flags & FLAG_TYPE_AX88172))
688
eth->write_hwaddr = asix_write_hwaddr;
691
if (asix_basic_reset(ss))
694
/* Get the MAC address */
695
if (asix_read_mac(eth))
697
debug("MAC %pM\n", eth->enetaddr);