← Back to branch summary

~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

« back to all changes in this revision

Viewing changes to roms/u-boot/arch/arm/cpu/armv7/omap5/sdram.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

Show diffs side-by-side

added added

removed removed

Lines of Context:
roms/u-boot/arch/arm/cpu/armv7/omap5/sdram.c
 
1
/*
 
2
 * Timing and Organization details of the ddr device parts used in OMAP5
 
3
 * EVM
 
4
 *
 
5
 * (C) Copyright 2010
 
6
 * Texas Instruments, <www.ti.com>
 
7
 *
 
8
 * Aneesh V <aneesh@ti.com>
 
9
 * Sricharan R <r.sricharan@ti.com>
 
10
 *
 
11
 * SPDX-License-Identifier:     GPL-2.0+
 
12
 */
 
13
 
 
14
#include <asm/emif.h>
 
15
#include <asm/arch/sys_proto.h>
 
16
 
 
17
/*
 
18
 * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
 
19
 * EVM. Since the parts used and geometry are identical for
 
20
 * evm for a given OMAP5 revision, this information is kept
 
21
 * here instead of being in board directory. However the key functions
 
22
 * exported are weakly linked so that they can be over-ridden in the board
 
23
 * directory if there is a OMAP5 board in the future that uses a different
 
24
 * memory device or geometry.
 
25
 *
 
26
 * For any new board with different memory devices over-ride one or more
 
27
 * of the following functions as per the CONFIG flags you intend to enable:
 
28
 * - emif_get_reg_dump()
 
29
 * - emif_get_dmm_regs()
 
30
 * - emif_get_device_details()
 
31
 * - emif_get_device_timings()
 
32
 */
 
33
 
 
34
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 
35
const struct emif_regs emif_regs_532_mhz_2cs = {
 
36
        .sdram_config_init              = 0x80800EBA,
 
37
        .sdram_config                   = 0x808022BA,
 
38
        .ref_ctrl                       = 0x0000081A,
 
39
        .sdram_tim1                     = 0x772F6873,
 
40
        .sdram_tim2                     = 0x304a129a,
 
41
        .sdram_tim3                     = 0x02f7e45f,
 
42
        .read_idle_ctrl                 = 0x00050000,
 
43
        .zq_config                      = 0x000b3215,
 
44
        .temp_alert_config              = 0x08000a05,
 
45
        .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
 
46
        .emif_ddr_phy_ctlr_1            = 0x0E28420d,
 
47
        .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
 
48
        .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
 
49
        .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
 
50
        .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
 
51
        .emif_ddr_ext_phy_ctrl_5        = 0x04010040
 
52
};
 
53
 
 
54
const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
 
55
        .sdram_config_init              = 0x80800EBA,
 
56
        .sdram_config                   = 0x808022BA,
 
57
        .ref_ctrl                       = 0x0000081A,
 
58
        .sdram_tim1                     = 0x772F6873,
 
59
        .sdram_tim2                     = 0x304a129a,
 
60
        .sdram_tim3                     = 0x02f7e45f,
 
61
        .read_idle_ctrl                 = 0x00050000,
 
62
        .zq_config                      = 0x100b3215,
 
63
        .temp_alert_config              = 0x08000a05,
 
64
        .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
 
65
        .emif_ddr_phy_ctlr_1            = 0x0E30400d,
 
66
        .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
 
67
        .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
 
68
        .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
 
69
        .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
 
70
        .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
 
71
};
 
72
 
 
73
const struct emif_regs emif_regs_266_mhz_2cs = {
 
74
        .sdram_config_init              = 0x80800EBA,
 
75
        .sdram_config                   = 0x808022BA,
 
76
        .ref_ctrl                       = 0x0000040D,
 
77
        .sdram_tim1                     = 0x2A86B419,
 
78
        .sdram_tim2                     = 0x1025094A,
 
79
        .sdram_tim3                     = 0x026BA22F,
 
80
        .read_idle_ctrl                 = 0x00050000,
 
81
        .zq_config                      = 0x000b3215,
 
82
        .temp_alert_config              = 0x08000a05,
 
83
        .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
 
84
        .emif_ddr_phy_ctlr_1            = 0x0E28420d,
 
85
        .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
 
86
        .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
 
87
        .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
 
88
        .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
 
89
        .emif_ddr_ext_phy_ctrl_5        = 0x04010040
 
90
};
 
91
 
 
92
const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
 
93
        .sdram_config_init              = 0x61851B32,
 
94
        .sdram_config                   = 0x61851B32,
 
95
        .sdram_config2                  = 0x0,
 
96
        .ref_ctrl                       = 0x00001035,
 
97
        .sdram_tim1                     = 0xCCCF36B3,
 
98
        .sdram_tim2                     = 0x308F7FDA,
 
99
        .sdram_tim3                     = 0x027F88A8,
 
100
        .read_idle_ctrl                 = 0x00050000,
 
101
        .zq_config                      = 0x0007190B,
 
102
        .temp_alert_config              = 0x00000000,
 
103
        .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 
104
        .emif_ddr_phy_ctlr_1            = 0x0024420A,
 
105
        .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 
106
        .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 
107
        .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 
108
        .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 
109
        .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 
110
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 
111
        .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 
112
        .emif_rd_wr_lvl_ctl             = 0x00000000,
 
113
        .emif_rd_wr_exec_thresh         = 0x00000305
 
114
};
 
115
 
 
116
const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 
117
        .sdram_config_init              = 0x61851B32,
 
118
        .sdram_config                   = 0x61851B32,
 
119
        .sdram_config2                  = 0x0,
 
120
        .ref_ctrl                       = 0x00001035,
 
121
        .sdram_tim1                     = 0xCCCF36B3,
 
122
        .sdram_tim2                     = 0x308F7FDA,
 
123
        .sdram_tim3                     = 0x027F88A8,
 
124
        .read_idle_ctrl                 = 0x00050000,
 
125
        .zq_config                      = 0x1007190B,
 
126
        .temp_alert_config              = 0x00000000,
 
127
        .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 
128
        .emif_ddr_phy_ctlr_1            = 0x0034400A,
 
129
        .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 
130
        .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 
131
        .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 
132
        .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 
133
        .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 
134
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 
135
        .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 
136
        .emif_rd_wr_lvl_ctl             = 0x00000000,
 
137
        .emif_rd_wr_exec_thresh         = 0x40000305
 
138
};
 
139
 
 
140
const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 
141
        .sdram_config_init              = 0x61851ab2,
 
142
        .sdram_config                   = 0x61851ab2,
 
143
        .sdram_config2                  = 0x08000000,
 
144
        .ref_ctrl                       = 0x00001035,
 
145
        .sdram_tim1                     = 0xCCCF36B3,
 
146
        .sdram_tim2                     = 0x308F7FDA,
 
147
        .sdram_tim3                     = 0x027F88A8,
 
148
        .read_idle_ctrl                 = 0x00050000,
 
149
        .zq_config                      = 0x0007190B,
 
150
        .temp_alert_config              = 0x00000000,
 
151
        .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
 
152
        .emif_ddr_phy_ctlr_1            = 0x0024400A,
 
153
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 
154
        .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
 
155
        .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
 
156
        .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 
157
        .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 
158
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 
159
        .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 
160
        .emif_rd_wr_lvl_ctl             = 0x00000000,
 
161
        .emif_rd_wr_exec_thresh         = 0x00000305
 
162
};
 
163
 
 
164
const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 
165
        .sdram_config_init              = 0x61851B32,
 
166
        .sdram_config                   = 0x61851B32,
 
167
        .sdram_config2                  = 0x08000000,
 
168
        .ref_ctrl                       = 0x00001035,
 
169
        .sdram_tim1                     = 0xCCCF36B3,
 
170
        .sdram_tim2                     = 0x308F7FDA,
 
171
        .sdram_tim3                     = 0x027F88A8,
 
172
        .read_idle_ctrl                 = 0x00050000,
 
173
        .zq_config                      = 0x0007190B,
 
174
        .temp_alert_config              = 0x00000000,
 
175
        .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
 
176
        .emif_ddr_phy_ctlr_1            = 0x0024400A,
 
177
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 
178
        .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
 
179
        .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
 
180
        .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 
181
        .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 
182
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 
183
        .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 
184
        .emif_rd_wr_lvl_ctl             = 0x00000000,
 
185
        .emif_rd_wr_exec_thresh         = 0x00000305
 
186
};
 
187
 
 
188
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 
189
        .dmm_lisa_map_0 = 0x0,
 
190
        .dmm_lisa_map_1 = 0x0,
 
191
        .dmm_lisa_map_2 = 0x80740300,
 
192
        .dmm_lisa_map_3 = 0xFF020100,
 
193
        .is_ma_present  = 0x1
 
194
};
 
195
 
 
196
/*
 
197
 * DRA752 EVM board has 1.5 GB of memory
 
198
 * EMIF1 --> 2Gb * 2 =  512MB
 
199
 * EMIF2 --> 2Gb * 4 =  1GB
 
200
 * so mapping 1GB interleaved and 512MB non-interleaved
 
201
 */
 
202
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 
203
        .dmm_lisa_map_0 = 0x0,
 
204
        .dmm_lisa_map_1 = 0x80640300,
 
205
        .dmm_lisa_map_2 = 0xC0500220,
 
206
        .dmm_lisa_map_3 = 0xFF020100,
 
207
        .is_ma_present  = 0x1
 
208
};
 
209
 
 
210
/*
 
211
 * DRA752 EVM EMIF1 ONLY CONFIGURATION
 
212
 */
 
213
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 
214
        .dmm_lisa_map_0 = 0x0,
 
215
        .dmm_lisa_map_1 = 0x0,
 
216
        .dmm_lisa_map_2 = 0x80500100,
 
217
        .dmm_lisa_map_3 = 0xFF020100,
 
218
        .is_ma_present  = 0x1
 
219
};
 
220
 
 
221
/*
 
222
 * DRA752 EVM EMIF2 ONLY CONFIGURATION
 
223
 */
 
224
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 
225
        .dmm_lisa_map_0 = 0x0,
 
226
        .dmm_lisa_map_1 = 0x0,
 
227
        .dmm_lisa_map_2 = 0x80600200,
 
228
        .dmm_lisa_map_3 = 0xFF020100,
 
229
        .is_ma_present  = 0x1
 
230
};
 
231
 
 
232
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 
233
{
 
234
        switch (omap_revision()) {
 
235
        case OMAP5430_ES1_0:
 
236
                *regs = &emif_regs_532_mhz_2cs;
 
237
                break;
 
238
        case OMAP5432_ES1_0:
 
239
                *regs = &emif_regs_ddr3_532_mhz_1cs;
 
240
                break;
 
241
        case OMAP5430_ES2_0:
 
242
                *regs = &emif_regs_532_mhz_2cs_es2;
 
243
                break;
 
244
        case OMAP5432_ES2_0:
 
245
                *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 
246
                break;
 
247
        case DRA752_ES1_0:
 
248
        case DRA752_ES1_1:
 
249
                switch (emif_nr) {
 
250
                case 1:
 
251
                        *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 
252
                        break;
 
253
                case 2:
 
254
                        *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
 
255
                        break;
 
256
                }
 
257
                break;
 
258
        default:
 
259
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 
260
        }
 
261
}
 
262
 
 
263
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 
264
        __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 
265
 
 
266
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 
267
                                                **dmm_lisa_regs)
 
268
{
 
269
        switch (omap_revision()) {
 
270
        case OMAP5430_ES1_0:
 
271
        case OMAP5430_ES2_0:
 
272
        case OMAP5432_ES1_0:
 
273
        case OMAP5432_ES2_0:
 
274
                *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 
275
                break;
 
276
        case DRA752_ES1_0:
 
277
        case DRA752_ES1_1:
 
278
        default:
 
279
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 
280
        }
 
281
 
 
282
}
 
283
 
 
284
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 
285
        __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 
286
#else
 
287
 
 
288
static const struct lpddr2_device_details dev_4G_S4_details = {
 
289
        .type           = LPDDR2_TYPE_S4,
 
290
        .density        = LPDDR2_DENSITY_4Gb,
 
291
        .io_width       = LPDDR2_IO_WIDTH_32,
 
292
        .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 
293
};
 
294
 
 
295
static void emif_get_device_details_sdp(u32 emif_nr,
 
296
                struct lpddr2_device_details *cs0_device_details,
 
297
                struct lpddr2_device_details *cs1_device_details)
 
298
{
 
299
        /* EMIF1 & EMIF2 have identical configuration */
 
300
        *cs0_device_details = dev_4G_S4_details;
 
301
        *cs1_device_details = dev_4G_S4_details;
 
302
}
 
303
 
 
304
void emif_get_device_details(u32 emif_nr,
 
305
                struct lpddr2_device_details *cs0_device_details,
 
306
                struct lpddr2_device_details *cs1_device_details)
 
307
        __attribute__((weak, alias("emif_get_device_details_sdp")));
 
308
 
 
309
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
310
 
 
311
const u32 ext_phy_ctrl_const_base[] = {
 
312
        0x01004010,
 
313
        0x00001004,
 
314
        0x04010040,
 
315
        0x01004010,
 
316
        0x00001004,
 
317
        0x00000000,
 
318
        0x00000000,
 
319
        0x00000000,
 
320
        0x80080080,
 
321
        0x00800800,
 
322
        0x08102040,
 
323
        0x00000001,
 
324
        0x540A8150,
 
325
        0xA81502a0,
 
326
        0x002A0540,
 
327
        0x00000000,
 
328
        0x00000000,
 
329
        0x00000000,
 
330
        0x00000077,
 
331
        0x0
 
332
};
 
333
 
 
334
const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 
335
        0x01004010,
 
336
        0x00001004,
 
337
        0x04010040,
 
338
        0x01004010,
 
339
        0x00001004,
 
340
        0x00000000,
 
341
        0x00000000,
 
342
        0x00000000,
 
343
        0x80080080,
 
344
        0x00800800,
 
345
        0x08102040,
 
346
        0x00000002,
 
347
        0x0,
 
348
        0x0,
 
349
        0x0,
 
350
        0x00000000,
 
351
        0x00000000,
 
352
        0x00000000,
 
353
        0x00000057,
 
354
        0x0
 
355
};
 
356
 
 
357
const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 
358
        0x50D4350D,
 
359
        0x00000D43,
 
360
        0x04010040,
 
361
        0x01004010,
 
362
        0x00001004,
 
363
        0x00000000,
 
364
        0x00000000,
 
365
        0x00000000,
 
366
        0x80080080,
 
367
        0x00800800,
 
368
        0x08102040,
 
369
        0x00000002,
 
370
        0x00000000,
 
371
        0x00000000,
 
372
        0x00000000,
 
373
        0x00000000,
 
374
        0x00000000,
 
375
        0x00000000,
 
376
        0x00000057,
 
377
        0x0
 
378
};
 
379
 
 
380
const u32
 
381
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 
382
        0x00B000B0,
 
383
        0x00400040,
 
384
        0x00400040,
 
385
        0x00400040,
 
386
        0x00400040,
 
387
        0x00400040,
 
388
        0x00800080,
 
389
        0x00800080,
 
390
        0x00800080,
 
391
        0x00800080,
 
392
        0x00800080,
 
393
        0x00600060,
 
394
        0x00600060,
 
395
        0x00600060,
 
396
        0x00600060,
 
397
        0x00600060,
 
398
        0x00800080,
 
399
        0x00800080,
 
400
        0x40010080,
 
401
        0x08102040,
 
402
        0x0,
 
403
        0x0,
 
404
        0x0,
 
405
        0x0,
 
406
        0x0
 
407
};
 
408
 
 
409
const u32
 
410
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 
411
        0x00BB00BB,
 
412
        0x00440044,
 
413
        0x00440044,
 
414
        0x00440044,
 
415
        0x00440044,
 
416
        0x00440044,
 
417
        0x007F007F,
 
418
        0x007F007F,
 
419
        0x007F007F,
 
420
        0x007F007F,
 
421
        0x007F007F,
 
422
        0x00600060,
 
423
        0x00600060,
 
424
        0x00600060,
 
425
        0x00600060,
 
426
        0x00600060,
 
427
        0x0,
 
428
        0x00600020,
 
429
        0x40010080,
 
430
        0x08102040,
 
431
        0x0,
 
432
        0x0,
 
433
        0x0,
 
434
        0x0,
 
435
        0x0
 
436
};
 
437
 
 
438
const struct lpddr2_mr_regs mr_regs = {
 
439
        .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 
440
        .mr2    = 0x6,
 
441
        .mr3    = 0x1,
 
442
        .mr10   = MR10_ZQ_ZQINIT,
 
443
        .mr16   = MR16_REF_FULL_ARRAY
 
444
};
 
445
 
 
446
static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 
447
                                             const u32 **regs,
 
448
                                             u32 *size)
 
449
{
 
450
        switch (omap_revision()) {
 
451
        case OMAP5430_ES1_0:
 
452
        case OMAP5430_ES2_0:
 
453
                *regs = ext_phy_ctrl_const_base;
 
454
                *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 
455
                break;
 
456
        case OMAP5432_ES1_0:
 
457
                *regs = ddr3_ext_phy_ctrl_const_base_es1;
 
458
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 
459
                break;
 
460
        case OMAP5432_ES2_0:
 
461
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
 
462
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 
463
                break;
 
464
        case DRA752_ES1_0:
 
465
        case DRA752_ES1_1:
 
466
                if (emif_nr == 1) {
 
467
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 
468
                        *size =
 
469
                        ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
 
470
                } else {
 
471
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 
472
                        *size =
 
473
                        ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
 
474
                }
 
475
                break;
 
476
        default:
 
477
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
 
478
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 
479
 
 
480
        }
 
481
}
 
482
 
 
483
void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 
484
{
 
485
        *regs = &mr_regs;
 
486
}
 
487
 
 
488
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 
489
{
 
490
        u32 *ext_phy_ctrl_base = 0;
 
491
        u32 *emif_ext_phy_ctrl_base = 0;
 
492
        u32 emif_nr;
 
493
        const u32 *ext_phy_ctrl_const_regs;
 
494
        u32 i = 0;
 
495
        u32 size;
 
496
 
 
497
        emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
498
 
 
499
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
500
 
 
501
        ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 
502
        emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 
503
 
 
504
        /* Configure external phy control timing registers */
 
505
        for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 
506
                writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 
507
                /* Update shadow registers */
 
508
                writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 
509
        }
 
510
 
 
511
        /*
 
512
         * external phy 6-24 registers do not change with
 
513
         * ddr frequency
 
514
         */
 
515
        emif_get_ext_phy_ctrl_const_regs(emif_nr,
 
516
                                         &ext_phy_ctrl_const_regs, &size);
 
517
 
 
518
        for (i = 0; i < size; i++) {
 
519
                writel(ext_phy_ctrl_const_regs[i],
 
520
                       emif_ext_phy_ctrl_base++);
 
521
                /* Update shadow registers */
 
522
                writel(ext_phy_ctrl_const_regs[i],
 
523
                       emif_ext_phy_ctrl_base++);
 
524
        }
 
525
}
 
526
 
 
527
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 
528
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 
529
        .max_freq       = 532000000,
 
530
        .RL             = 8,
 
531
        .tRPab          = 21,
 
532
        .tRCD           = 18,
 
533
        .tWR            = 15,
 
534
        .tRASmin        = 42,
 
535
        .tRRD           = 10,
 
536
        .tWTRx2         = 15,
 
537
        .tXSR           = 140,
 
538
        .tXPx2          = 15,
 
539
        .tRFCab         = 130,
 
540
        .tRTPx2         = 15,
 
541
        .tCKE           = 3,
 
542
        .tCKESR         = 15,
 
543
        .tZQCS          = 90,
 
544
        .tZQCL          = 360,
 
545
        .tZQINIT        = 1000,
 
546
        .tDQSCKMAXx2    = 11,
 
547
        .tRASmax        = 70,
 
548
        .tFAW           = 50
 
549
};
 
550
 
 
551
static const struct lpddr2_min_tck min_tck = {
 
552
        .tRL            = 3,
 
553
        .tRP_AB         = 3,
 
554
        .tRCD           = 3,
 
555
        .tWR            = 3,
 
556
        .tRAS_MIN       = 3,
 
557
        .tRRD           = 2,
 
558
        .tWTR           = 2,
 
559
        .tXP            = 2,
 
560
        .tRTP           = 2,
 
561
        .tCKE           = 3,
 
562
        .tCKESR         = 3,
 
563
        .tFAW           = 8
 
564
};
 
565
 
 
566
static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 
567
        &timings_jedec_532_mhz
 
568
};
 
569
 
 
570
static const struct lpddr2_device_timings dev_4G_S4_timings = {
 
571
        .ac_timings     = ac_timings,
 
572
        .min_tck        = &min_tck,
 
573
};
 
574
 
 
575
/*
 
576
 * List of status registers to be controlled back to control registers
 
577
 * after initial leveling
 
578
 * readreg, writereg
 
579
 */
 
580
const struct read_write_regs omap5_bug_00339_regs[] = {
 
581
        { 8,  5 },
 
582
        { 9,  6 },
 
583
        { 10, 7 },
 
584
        { 14, 8 },
 
585
        { 15, 9 },
 
586
        { 16, 10 },
 
587
        { 11, 2 },
 
588
        { 12, 3 },
 
589
        { 13, 4 },
 
590
        { 17, 11 },
 
591
        { 18, 12 },
 
592
        { 19, 13 },
 
593
};
 
594
 
 
595
const struct read_write_regs dra_bug_00339_regs[] = {
 
596
        { 7,  7 },
 
597
        { 8,  8 },
 
598
        { 9,  9 },
 
599
        { 10, 10 },
 
600
        { 11, 11 },
 
601
        { 12, 2 },
 
602
        { 13, 3 },
 
603
        { 14, 4 },
 
604
        { 15, 5 },
 
605
        { 16, 6 },
 
606
        { 17, 12 },
 
607
        { 18, 13 },
 
608
        { 19, 14 },
 
609
        { 20, 15 },
 
610
        { 21, 16 },
 
611
        { 22, 17 },
 
612
        { 23, 18 },
 
613
        { 24, 19 },
 
614
        { 25, 20 },
 
615
        { 26, 21}
 
616
};
 
617
 
 
618
const struct read_write_regs *get_bug_regs(u32 *iterations)
 
619
{
 
620
        const struct read_write_regs *bug_00339_regs_ptr = NULL;
 
621
 
 
622
        switch (omap_revision()) {
 
623
        case OMAP5430_ES1_0:
 
624
        case OMAP5430_ES2_0:
 
625
        case OMAP5432_ES1_0:
 
626
        case OMAP5432_ES2_0:
 
627
                bug_00339_regs_ptr = omap5_bug_00339_regs;
 
628
                *iterations = sizeof(omap5_bug_00339_regs)/
 
629
                             sizeof(omap5_bug_00339_regs[0]);
 
630
                break;
 
631
        case DRA752_ES1_0:
 
632
        case DRA752_ES1_1:
 
633
                bug_00339_regs_ptr = dra_bug_00339_regs;
 
634
                *iterations = sizeof(dra_bug_00339_regs)/
 
635
                             sizeof(dra_bug_00339_regs[0]);
 
636
                break;
 
637
        default:
 
638
                printf("\n Error: UnKnown SOC");
 
639
        }
 
640
 
 
641
        return bug_00339_regs_ptr;
 
642
}
 
643
 
 
644
void emif_get_device_timings_sdp(u32 emif_nr,
 
645
                const struct lpddr2_device_timings **cs0_device_timings,
 
646
                const struct lpddr2_device_timings **cs1_device_timings)
 
647
{
 
648
        /* Identical devices on EMIF1 & EMIF2 */
 
649
        *cs0_device_timings = &dev_4G_S4_timings;
 
650
        *cs1_device_timings = &dev_4G_S4_timings;
 
651
}
 
652
 
 
653
void emif_get_device_timings(u32 emif_nr,
 
654
                const struct lpddr2_device_timings **cs0_device_timings,
 
655
                const struct lpddr2_device_timings **cs1_device_timings)
 
656
        __attribute__((weak, alias("emif_get_device_timings_sdp")));
 
657
 
 
658
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */