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Viewing changes to roms/u-boot/include/radeon.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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Lines of Context:
roms/u-boot/include/radeon.h
 
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#ifndef _RADEON_H
 
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#define _RADEON_H
 
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4
 
 
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#define RADEON_REGSIZE                  0x4000
 
6
 
 
7
 
 
8
#define MM_INDEX                        0x0000
 
9
#define MM_DATA                         0x0004
 
10
#define BUS_CNTL                        0x0030
 
11
#define HI_STAT                         0x004C
 
12
#define BUS_CNTL1                       0x0034
 
13
#define I2C_CNTL_1                      0x0094
 
14
#define CONFIG_CNTL                     0x00E0
 
15
#define CONFIG_MEMSIZE                  0x00F8
 
16
#define CONFIG_APER_0_BASE              0x0100
 
17
#define CONFIG_APER_1_BASE              0x0104
 
18
#define CONFIG_APER_SIZE                0x0108
 
19
#define CONFIG_REG_1_BASE               0x010C
 
20
#define CONFIG_REG_APER_SIZE            0x0110
 
21
#define PAD_AGPINPUT_DELAY              0x0164
 
22
#define PAD_CTLR_STRENGTH               0x0168
 
23
#define PAD_CTLR_UPDATE                 0x016C
 
24
#define PAD_CTLR_MISC                   0x0aa0
 
25
#define AGP_CNTL                        0x0174
 
26
#define BM_STATUS                       0x0160
 
27
#define CAP0_TRIG_CNTL                  0x0950
 
28
#define CAP1_TRIG_CNTL                  0x09c0
 
29
#define VIPH_CONTROL                    0x0C40
 
30
#define VENDOR_ID                       0x0F00
 
31
#define DEVICE_ID                       0x0F02
 
32
#define COMMAND                         0x0F04
 
33
#define STATUS                          0x0F06
 
34
#define REVISION_ID                     0x0F08
 
35
#define REGPROG_INF                     0x0F09
 
36
#define SUB_CLASS                       0x0F0A
 
37
#define BASE_CODE                       0x0F0B
 
38
#define CACHE_LINE                      0x0F0C
 
39
#define LATENCY                         0x0F0D
 
40
#define HEADER                          0x0F0E
 
41
#define BIST                            0x0F0F
 
42
#define REG_MEM_BASE                    0x0F10
 
43
#define REG_IO_BASE                     0x0F14
 
44
#define REG_REG_BASE                    0x0F18
 
45
#define ADAPTER_ID                      0x0F2C
 
46
#define BIOS_ROM                        0x0F30
 
47
#define CAPABILITIES_PTR                0x0F34
 
48
#define INTERRUPT_LINE                  0x0F3C
 
49
#define INTERRUPT_PIN                   0x0F3D
 
50
#define MIN_GRANT                       0x0F3E
 
51
#define MAX_LATENCY                     0x0F3F
 
52
#define ADAPTER_ID_W                    0x0F4C
 
53
#define PMI_CAP_ID                      0x0F50
 
54
#define PMI_NXT_CAP_PTR                 0x0F51
 
55
#define PMI_PMC_REG                     0x0F52
 
56
#define PM_STATUS                       0x0F54
 
57
#define PMI_DATA                        0x0F57
 
58
#define AGP_CAP_ID                      0x0F58
 
59
#define AGP_STATUS                      0x0F5C
 
60
#define AGP_COMMAND                     0x0F60
 
61
#define AIC_CTRL                        0x01D0
 
62
#define AIC_STAT                        0x01D4
 
63
#define AIC_PT_BASE                     0x01D8
 
64
#define AIC_LO_ADDR                     0x01DC
 
65
#define AIC_HI_ADDR                     0x01E0
 
66
#define AIC_TLB_ADDR                    0x01E4
 
67
#define AIC_TLB_DATA                    0x01E8
 
68
#define DAC_CNTL                        0x0058
 
69
#define DAC_CNTL2                       0x007c
 
70
#define CRTC_GEN_CNTL                   0x0050
 
71
#define MEM_CNTL                        0x0140
 
72
#define MC_CNTL                         0x0140
 
73
#define EXT_MEM_CNTL                    0x0144
 
74
#define MC_TIMING_CNTL                  0x0144
 
75
#define MC_AGP_LOCATION                 0x014C
 
76
#define MEM_IO_CNTL_A0                  0x0178
 
77
#define MEM_REFRESH_CNTL                0x0178
 
78
#define MEM_INIT_LATENCY_TIMER          0x0154
 
79
#define MC_INIT_GFX_LAT_TIMER           0x0154
 
80
#define MEM_SDRAM_MODE_REG              0x0158
 
81
#define AGP_BASE                        0x0170
 
82
#define MEM_IO_CNTL_A1                  0x017C
 
83
#define MC_READ_CNTL_AB                 0x017C
 
84
#define MEM_IO_CNTL_B0                  0x0180
 
85
#define MC_INIT_MISC_LAT_TIMER          0x0180
 
86
#define MEM_IO_CNTL_B1                  0x0184
 
87
#define MC_IOPAD_CNTL                   0x0184
 
88
#define MC_DEBUG                        0x0188
 
89
#define MC_STATUS                       0x0150
 
90
#define MEM_IO_OE_CNTL                  0x018C
 
91
#define MC_CHIP_IO_OE_CNTL_AB           0x018C
 
92
#define MC_FB_LOCATION                  0x0148
 
93
/* #define MC_FB_LOCATION               0x0188 */
 
94
#define HOST_PATH_CNTL                  0x0130
 
95
#define MEM_VGA_WP_SEL                  0x0038
 
96
#define MEM_VGA_RP_SEL                  0x003C
 
97
#define HDP_DEBUG                       0x0138
 
98
#define SW_SEMAPHORE                    0x013C
 
99
#define CRTC2_GEN_CNTL                  0x03f8
 
100
#define CRTC2_DISPLAY_BASE_ADDR         0x033c
 
101
#define SURFACE_CNTL                    0x0B00
 
102
#define SURFACE0_LOWER_BOUND            0x0B04
 
103
#define SURFACE1_LOWER_BOUND            0x0B14
 
104
#define SURFACE2_LOWER_BOUND            0x0B24
 
105
#define SURFACE3_LOWER_BOUND            0x0B34
 
106
#define SURFACE4_LOWER_BOUND            0x0B44
 
107
#define SURFACE5_LOWER_BOUND            0x0B54
 
108
#define SURFACE6_LOWER_BOUND            0x0B64
 
109
#define SURFACE7_LOWER_BOUND            0x0B74
 
110
#define SURFACE0_UPPER_BOUND            0x0B08
 
111
#define SURFACE1_UPPER_BOUND            0x0B18
 
112
#define SURFACE2_UPPER_BOUND            0x0B28
 
113
#define SURFACE3_UPPER_BOUND            0x0B38
 
114
#define SURFACE4_UPPER_BOUND            0x0B48
 
115
#define SURFACE5_UPPER_BOUND            0x0B58
 
116
#define SURFACE6_UPPER_BOUND            0x0B68
 
117
#define SURFACE7_UPPER_BOUND            0x0B78
 
118
#define SURFACE0_INFO                   0x0B0C
 
119
#define SURFACE1_INFO                   0x0B1C
 
120
#define SURFACE2_INFO                   0x0B2C
 
121
#define SURFACE3_INFO                   0x0B3C
 
122
#define SURFACE4_INFO                   0x0B4C
 
123
#define SURFACE5_INFO                   0x0B5C
 
124
#define SURFACE6_INFO                   0x0B6C
 
125
#define SURFACE7_INFO                   0x0B7C
 
126
#define SURFACE_ACCESS_FLAGS            0x0BF8
 
127
#define SURFACE_ACCESS_CLR              0x0BFC
 
128
#define GEN_INT_CNTL                    0x0040
 
129
#define GEN_INT_STATUS                  0x0044
 
130
#define CRTC_EXT_CNTL                   0x0054
 
131
#define RB3D_CNTL                       0x1C3C
 
132
#define WAIT_UNTIL                      0x1720
 
133
#define ISYNC_CNTL                      0x1724
 
134
#define RBBM_GUICNTL                    0x172C
 
135
#define RBBM_STATUS                     0x0E40
 
136
#define RBBM_STATUS_alt_1               0x1740
 
137
#define RBBM_CNTL                       0x00EC
 
138
#define RBBM_CNTL_alt_1                 0x0E44
 
139
#define RBBM_SOFT_RESET                 0x00F0
 
140
#define RBBM_SOFT_RESET_alt_1           0x0E48
 
141
#define NQWAIT_UNTIL                    0x0E50
 
142
#define RBBM_DEBUG                      0x0E6C
 
143
#define RBBM_CMDFIFO_ADDR               0x0E70
 
144
#define RBBM_CMDFIFO_DATAL              0x0E74
 
145
#define RBBM_CMDFIFO_DATAH              0x0E78
 
146
#define RBBM_CMDFIFO_STAT               0x0E7C
 
147
#define CRTC_STATUS                     0x005C
 
148
#define GPIO_VGA_DDC                    0x0060
 
149
#define GPIO_DVI_DDC                    0x0064
 
150
#define GPIO_MONID                      0x0068
 
151
#define GPIO_CRT2_DDC                   0x006c
 
152
#define PALETTE_INDEX                   0x00B0
 
153
#define PALETTE_DATA                    0x00B4
 
154
#define PALETTE_30_DATA                 0x00B8
 
155
#define CRTC_H_TOTAL_DISP               0x0200
 
156
#define CRTC_H_SYNC_STRT_WID            0x0204
 
157
#define CRTC_H_SYNC_POL                 (1 << 23)
 
158
#define CRTC_V_TOTAL_DISP               0x0208
 
159
#define CRTC_V_SYNC_STRT_WID            0x020C
 
160
#define CRTC_V_SYNC_POL                 (1 << 23)
 
161
#define CRTC_VLINE_CRNT_VLINE           0x0210
 
162
#define CRTC_CRNT_FRAME                 0x0214
 
163
#define CRTC_GUI_TRIG_VLINE             0x0218
 
164
#define CRTC_DEBUG                      0x021C
 
165
#define CRTC_OFFSET_RIGHT               0x0220
 
166
#define CRTC_OFFSET                     0x0224
 
167
#define CRTC_OFFSET_CNTL                0x0228
 
168
#define CRTC_PITCH                      0x022C
 
169
#define OVR_CLR                         0x0230
 
170
#define OVR_WID_LEFT_RIGHT              0x0234
 
171
#define OVR_WID_TOP_BOTTOM              0x0238
 
172
#define DISPLAY_BASE_ADDR               0x023C
 
173
#define SNAPSHOT_VH_COUNTS              0x0240
 
174
#define SNAPSHOT_F_COUNT                0x0244
 
175
#define N_VIF_COUNT                     0x0248
 
176
#define SNAPSHOT_VIF_COUNT              0x024C
 
177
#define FP_CRTC_H_TOTAL_DISP            0x0250
 
178
#define FP_CRTC_V_TOTAL_DISP            0x0254
 
179
#define CRT_CRTC_H_SYNC_STRT_WID        0x0258
 
180
#define CRT_CRTC_V_SYNC_STRT_WID        0x025C
 
181
#define CUR_OFFSET                      0x0260
 
182
#define CUR_HORZ_VERT_POSN              0x0264
 
183
#define CUR_HORZ_VERT_OFF               0x0268
 
184
#define CUR_CLR0                        0x026C
 
185
#define CUR_CLR1                        0x0270
 
186
#define FP_HORZ_VERT_ACTIVE             0x0278
 
187
#define CRTC_MORE_CNTL                  0x027C
 
188
#define CRTC_H_CUTOFF_ACTIVE_EN         (1<<4)
 
189
#define CRTC_V_CUTOFF_ACTIVE_EN         (1<<5)
 
190
#define DAC_EXT_CNTL                    0x0280
 
191
#define FP_GEN_CNTL                     0x0284
 
192
#define FP_HORZ_STRETCH                 0x028C
 
193
#define FP_VERT_STRETCH                 0x0290
 
194
#define FP_H_SYNC_STRT_WID              0x02C4
 
195
#define FP_V_SYNC_STRT_WID              0x02C8
 
196
#define AUX_WINDOW_HORZ_CNTL            0x02D8
 
197
#define AUX_WINDOW_VERT_CNTL            0x02DC
 
198
/* #define DDA_CONFIG                   0x02e0 */
 
199
/* #define DDA_ON_OFF                   0x02e4 */
 
200
#define DVI_I2C_CNTL_1                  0x02e4
 
201
#define GRPH_BUFFER_CNTL                0x02F0
 
202
#define GRPH2_BUFFER_CNTL               0x03F0
 
203
#define VGA_BUFFER_CNTL                 0x02F4
 
204
#define OV0_Y_X_START                   0x0400
 
205
#define OV0_Y_X_END                     0x0404
 
206
#define OV0_PIPELINE_CNTL               0x0408
 
207
#define OV0_REG_LOAD_CNTL               0x0410
 
208
#define OV0_SCALE_CNTL                  0x0420
 
209
#define OV0_V_INC                       0x0424
 
210
#define OV0_P1_V_ACCUM_INIT             0x0428
 
211
#define OV0_P23_V_ACCUM_INIT            0x042C
 
212
#define OV0_P1_BLANK_LINES_AT_TOP       0x0430
 
213
#define OV0_P23_BLANK_LINES_AT_TOP      0x0434
 
214
#define OV0_BASE_ADDR                   0x043C
 
215
#define OV0_VID_BUF0_BASE_ADRS          0x0440
 
216
#define OV0_VID_BUF1_BASE_ADRS          0x0444
 
217
#define OV0_VID_BUF2_BASE_ADRS          0x0448
 
218
#define OV0_VID_BUF3_BASE_ADRS          0x044C
 
219
#define OV0_VID_BUF4_BASE_ADRS          0x0450
 
220
#define OV0_VID_BUF5_BASE_ADRS          0x0454
 
221
#define OV0_VID_BUF_PITCH0_VALUE        0x0460
 
222
#define OV0_VID_BUF_PITCH1_VALUE        0x0464
 
223
#define OV0_AUTO_FLIP_CNTRL             0x0470
 
224
#define OV0_DEINTERLACE_PATTERN         0x0474
 
225
#define OV0_SUBMIT_HISTORY              0x0478
 
226
#define OV0_H_INC                       0x0480
 
227
#define OV0_STEP_BY                     0x0484
 
228
#define OV0_P1_H_ACCUM_INIT             0x0488
 
229
#define OV0_P23_H_ACCUM_INIT            0x048C
 
230
#define OV0_P1_X_START_END              0x0494
 
231
#define OV0_P2_X_START_END              0x0498
 
232
#define OV0_P3_X_START_END              0x049C
 
233
#define OV0_FILTER_CNTL                 0x04A0
 
234
#define OV0_FOUR_TAP_COEF_0             0x04B0
 
235
#define OV0_FOUR_TAP_COEF_1             0x04B4
 
236
#define OV0_FOUR_TAP_COEF_2             0x04B8
 
237
#define OV0_FOUR_TAP_COEF_3             0x04BC
 
238
#define OV0_FOUR_TAP_COEF_4             0x04C0
 
239
#define OV0_FLAG_CNTRL                  0x04DC
 
240
#define OV0_SLICE_CNTL                  0x04E0
 
241
#define OV0_VID_KEY_CLR_LOW             0x04E4
 
242
#define OV0_VID_KEY_CLR_HIGH            0x04E8
 
243
#define OV0_GRPH_KEY_CLR_LOW            0x04EC
 
244
#define OV0_GRPH_KEY_CLR_HIGH           0x04F0
 
245
#define OV0_KEY_CNTL                    0x04F4
 
246
#define OV0_TEST                        0x04F8
 
247
#define SUBPIC_CNTL                     0x0540
 
248
#define SUBPIC_DEFCOLCON                0x0544
 
249
#define SUBPIC_Y_X_START                0x054C
 
250
#define SUBPIC_Y_X_END                  0x0550
 
251
#define SUBPIC_V_INC                    0x0554
 
252
#define SUBPIC_H_INC                    0x0558
 
253
#define SUBPIC_BUF0_OFFSET              0x055C
 
254
#define SUBPIC_BUF1_OFFSET              0x0560
 
255
#define SUBPIC_LC0_OFFSET               0x0564
 
256
#define SUBPIC_LC1_OFFSET               0x0568
 
257
#define SUBPIC_PITCH                    0x056C
 
258
#define SUBPIC_BTN_HLI_COLCON           0x0570
 
259
#define SUBPIC_BTN_HLI_Y_X_START        0x0574
 
260
#define SUBPIC_BTN_HLI_Y_X_END          0x0578
 
261
#define SUBPIC_PALETTE_INDEX            0x057C
 
262
#define SUBPIC_PALETTE_DATA             0x0580
 
263
#define SUBPIC_H_ACCUM_INIT             0x0584
 
264
#define SUBPIC_V_ACCUM_INIT             0x0588
 
265
#define DISP_MISC_CNTL                  0x0D00
 
266
#define DAC_MACRO_CNTL                  0x0D04
 
267
#define DISP_PWR_MAN                    0x0D08
 
268
#define DISP_TEST_DEBUG_CNTL            0x0D10
 
269
#define DISP_HW_DEBUG                   0x0D14
 
270
#define DAC_CRC_SIG1                    0x0D18
 
271
#define DAC_CRC_SIG2                    0x0D1C
 
272
#define OV0_LIN_TRANS_A                 0x0D20
 
273
#define OV0_LIN_TRANS_B                 0x0D24
 
274
#define OV0_LIN_TRANS_C                 0x0D28
 
275
#define OV0_LIN_TRANS_D                 0x0D2C
 
276
#define OV0_LIN_TRANS_E                 0x0D30
 
277
#define OV0_LIN_TRANS_F                 0x0D34
 
278
#define OV0_GAMMA_0_F                   0x0D40
 
279
#define OV0_GAMMA_10_1F                 0x0D44
 
280
#define OV0_GAMMA_20_3F                 0x0D48
 
281
#define OV0_GAMMA_40_7F                 0x0D4C
 
282
#define OV0_GAMMA_380_3BF               0x0D50
 
283
#define OV0_GAMMA_3C0_3FF               0x0D54
 
284
#define DISP_MERGE_CNTL                 0x0D60
 
285
#define DISP_OUTPUT_CNTL                0x0D64
 
286
#define DISP_LIN_TRANS_GRPH_A           0x0D80
 
287
#define DISP_LIN_TRANS_GRPH_B           0x0D84
 
288
#define DISP_LIN_TRANS_GRPH_C           0x0D88
 
289
#define DISP_LIN_TRANS_GRPH_D           0x0D8C
 
290
#define DISP_LIN_TRANS_GRPH_E           0x0D90
 
291
#define DISP_LIN_TRANS_GRPH_F           0x0D94
 
292
#define DISP_LIN_TRANS_VID_A            0x0D98
 
293
#define DISP_LIN_TRANS_VID_B            0x0D9C
 
294
#define DISP_LIN_TRANS_VID_C            0x0DA0
 
295
#define DISP_LIN_TRANS_VID_D            0x0DA4
 
296
#define DISP_LIN_TRANS_VID_E            0x0DA8
 
297
#define DISP_LIN_TRANS_VID_F            0x0DAC
 
298
#define RMX_HORZ_FILTER_0TAP_COEF       0x0DB0
 
299
#define RMX_HORZ_FILTER_1TAP_COEF       0x0DB4
 
300
#define RMX_HORZ_FILTER_2TAP_COEF       0x0DB8
 
301
#define RMX_HORZ_PHASE                  0x0DBC
 
302
#define DAC_EMBEDDED_SYNC_CNTL          0x0DC0
 
303
#define DAC_BROAD_PULSE                 0x0DC4
 
304
#define DAC_SKEW_CLKS                   0x0DC8
 
305
#define DAC_INCR                        0x0DCC
 
306
#define DAC_NEG_SYNC_LEVEL              0x0DD0
 
307
#define DAC_POS_SYNC_LEVEL              0x0DD4
 
308
#define DAC_BLANK_LEVEL                 0x0DD8
 
309
#define CLOCK_CNTL_INDEX                0x0008
 
310
#define CLOCK_CNTL_DATA                 0x000C
 
311
#define CP_RB_CNTL                      0x0704
 
312
#define CP_RB_BASE                      0x0700
 
313
#define CP_RB_RPTR_ADDR                 0x070C
 
314
#define CP_RB_RPTR                      0x0710
 
315
#define CP_RB_WPTR                      0x0714
 
316
#define CP_RB_WPTR_DELAY                0x0718
 
317
#define CP_IB_BASE                      0x0738
 
318
#define CP_IB_BUFSZ                     0x073C
 
319
#define SCRATCH_REG0                    0x15E0
 
320
#define GUI_SCRATCH_REG0                0x15E0
 
321
#define SCRATCH_REG1                    0x15E4
 
322
#define GUI_SCRATCH_REG1                0x15E4
 
323
#define SCRATCH_REG2                    0x15E8
 
324
#define GUI_SCRATCH_REG2                0x15E8
 
325
#define SCRATCH_REG3                    0x15EC
 
326
#define GUI_SCRATCH_REG3                0x15EC
 
327
#define SCRATCH_REG4                    0x15F0
 
328
#define GUI_SCRATCH_REG4                0x15F0
 
329
#define SCRATCH_REG5                    0x15F4
 
330
#define GUI_SCRATCH_REG5                0x15F4
 
331
#define SCRATCH_UMSK                    0x0770
 
332
#define SCRATCH_ADDR                    0x0774
 
333
#define DP_BRUSH_FRGD_CLR               0x147C
 
334
#define DP_BRUSH_BKGD_CLR               0x1478
 
335
#define DST_LINE_START                  0x1600
 
336
#define DST_LINE_END                    0x1604
 
337
#define SRC_OFFSET                      0x15AC
 
338
#define SRC_PITCH                       0x15B0
 
339
#define SRC_TILE                        0x1704
 
340
#define SRC_PITCH_OFFSET                0x1428
 
341
#define SRC_X                           0x1414
 
342
#define SRC_Y                           0x1418
 
343
#define SRC_X_Y                         0x1590
 
344
#define SRC_Y_X                         0x1434
 
345
#define DST_Y_X                         0x1438
 
346
#define DST_WIDTH_HEIGHT                0x1598
 
347
#define DST_HEIGHT_WIDTH                0x143c
 
348
#define DST_OFFSET                      0x1404
 
349
#define SRC_CLUT_ADDRESS                0x1780
 
350
#define SRC_CLUT_DATA                   0x1784
 
351
#define SRC_CLUT_DATA_RD                0x1788
 
352
#define HOST_DATA0                      0x17C0
 
353
#define HOST_DATA1                      0x17C4
 
354
#define HOST_DATA2                      0x17C8
 
355
#define HOST_DATA3                      0x17CC
 
356
#define HOST_DATA4                      0x17D0
 
357
#define HOST_DATA5                      0x17D4
 
358
#define HOST_DATA6                      0x17D8
 
359
#define HOST_DATA7                      0x17DC
 
360
#define HOST_DATA_LAST                  0x17E0
 
361
#define DP_SRC_ENDIAN                   0x15D4
 
362
#define DP_SRC_FRGD_CLR                 0x15D8
 
363
#define DP_SRC_BKGD_CLR                 0x15DC
 
364
#define SC_LEFT                         0x1640
 
365
#define SC_RIGHT                        0x1644
 
366
#define SC_TOP                          0x1648
 
367
#define SC_BOTTOM                       0x164C
 
368
#define SRC_SC_RIGHT                    0x1654
 
369
#define SRC_SC_BOTTOM                   0x165C
 
370
#define DP_CNTL                         0x16C0
 
371
#define DP_CNTL_XDIR_YDIR_YMAJOR        0x16D0
 
372
#define DP_DATATYPE                     0x16C4
 
373
#define DP_MIX                          0x16C8
 
374
#define DP_WRITE_MSK                    0x16CC
 
375
#define DP_XOP                          0x17F8
 
376
#define CLR_CMP_CLR_SRC                 0x15C4
 
377
#define CLR_CMP_CLR_DST                 0x15C8
 
378
#define CLR_CMP_CNTL                    0x15C0
 
379
#define CLR_CMP_MSK                     0x15CC
 
380
#define DSTCACHE_MODE                   0x1710
 
381
#define DSTCACHE_CTLSTAT                0x1714
 
382
#define DEFAULT_PITCH_OFFSET            0x16E0
 
383
#define DEFAULT_SC_BOTTOM_RIGHT         0x16E8
 
384
#define DEFAULT_SC_TOP_LEFT             0x16EC
 
385
#define SRC_PITCH_OFFSET                0x1428
 
386
#define DST_PITCH_OFFSET                0x142C
 
387
#define DP_GUI_MASTER_CNTL              0x146C
 
388
#define SC_TOP_LEFT                     0x16EC
 
389
#define SC_BOTTOM_RIGHT                 0x16F0
 
390
#define SRC_SC_BOTTOM_RIGHT             0x16F4
 
391
#define RB2D_DSTCACHE_MODE              0x3428
 
392
#define RB2D_DSTCACHE_CTLSTAT           0x342C
 
393
#define LVDS_GEN_CNTL                   0x02d0
 
394
#define LVDS_PLL_CNTL                   0x02d4
 
395
#define FP2_GEN_CNTL                    0x0288
 
396
#define TMDS_CNTL                       0x0294
 
397
#define TMDS_CRC                        0x02a0
 
398
#define TMDS_TRANSMITTER_CNTL           0x02a4
 
399
#define MPP_TB_CONFIG                   0x01c0
 
400
#define PAMAC0_DLY_CNTL                 0x0a94
 
401
#define PAMAC1_DLY_CNTL                 0x0a98
 
402
#define PAMAC2_DLY_CNTL                 0x0a9c
 
403
#define FW_CNTL                         0x0118
 
404
#define FCP_CNTL                        0x0910
 
405
#define VGA_DDA_ON_OFF                  0x02ec
 
406
#define TV_MASTER_CNTL                  0x0800
 
407
 
 
408
/* #define BASE_CODE                    0x0f0b */
 
409
#define BIOS_0_SCRATCH                  0x0010
 
410
#define BIOS_1_SCRATCH                  0x0014
 
411
#define BIOS_2_SCRATCH                  0x0018
 
412
#define BIOS_3_SCRATCH                  0x001c
 
413
#define BIOS_4_SCRATCH                  0x0020
 
414
#define BIOS_5_SCRATCH                  0x0024
 
415
#define BIOS_6_SCRATCH                  0x0028
 
416
#define BIOS_7_SCRATCH                  0x002c
 
417
 
 
418
#define HDP_SOFT_RESET                  (1 << 26)
 
419
 
 
420
#define TV_DAC_CNTL                     0x088c
 
421
#define GPIOPAD_MASK                    0x0198
 
422
#define GPIOPAD_A                       0x019c
 
423
#define GPIOPAD_EN                      0x01a0
 
424
#define GPIOPAD_Y                       0x01a4
 
425
#define ZV_LCDPAD_MASK                  0x01a8
 
426
#define ZV_LCDPAD_A                     0x01ac
 
427
#define ZV_LCDPAD_EN                    0x01b0
 
428
#define ZV_LCDPAD_Y                     0x01b4
 
429
 
 
430
/* PLL Registers */
 
431
#define CLK_PIN_CNTL                    0x0001
 
432
#define PPLL_CNTL                       0x0002
 
433
#define PPLL_REF_DIV                    0x0003
 
434
#define PPLL_DIV_0                      0x0004
 
435
#define PPLL_DIV_1                      0x0005
 
436
#define PPLL_DIV_2                      0x0006
 
437
#define PPLL_DIV_3                      0x0007
 
438
#define VCLK_ECP_CNTL                   0x0008
 
439
#define HTOTAL_CNTL                     0x0009
 
440
#define M_SPLL_REF_FB_DIV               0x000a
 
441
#define AGP_PLL_CNTL                    0x000b
 
442
#define SPLL_CNTL                       0x000c
 
443
#define SCLK_CNTL                       0x000d
 
444
#define MPLL_CNTL                       0x000e
 
445
#define MDLL_CKO                        0x000f
 
446
#define MDLL_RDCKA                      0x0010
 
447
#define MCLK_CNTL                       0x0012
 
448
#define AGP_PLL_CNTL                    0x000b
 
449
#define PLL_TEST_CNTL                   0x0013
 
450
#define CLK_PWRMGT_CNTL                 0x0014
 
451
#define PLL_PWRMGT_CNTL                 0x0015
 
452
#define MCLK_MISC                       0x001f
 
453
#define P2PLL_CNTL                      0x002a
 
454
#define P2PLL_REF_DIV                   0x002b
 
455
#define PIXCLKS_CNTL                    0x002d
 
456
#define SCLK_MORE_CNTL                  0x0035
 
457
 
 
458
/* MCLK_CNTL bit constants */
 
459
#define FORCEON_MCLKA                   (1 << 16)
 
460
#define FORCEON_MCLKB                   (1 << 17)
 
461
#define FORCEON_YCLKA                   (1 << 18)
 
462
#define FORCEON_YCLKB                   (1 << 19)
 
463
#define FORCEON_MC                      (1 << 20)
 
464
#define FORCEON_AIC                     (1 << 21)
 
465
 
 
466
/* SCLK_CNTL bit constants */
 
467
#define DYN_STOP_LAT_MASK               0x00007ff8
 
468
#define CP_MAX_DYN_STOP_LAT             0x0008
 
469
#define SCLK_FORCEON_MASK               0xffff8000
 
470
 
 
471
/* SCLK_MORE_CNTL bit constants */
 
472
#define SCLK_MORE_FORCEON               0x0700
 
473
 
 
474
/* BUS_CNTL bit constants */
 
475
#define BUS_DBL_RESYNC                  0x00000001
 
476
#define BUS_MSTR_RESET                  0x00000002
 
477
#define BUS_FLUSH_BUF                   0x00000004
 
478
#define BUS_STOP_REQ_DIS                0x00000008
 
479
#define BUS_ROTATION_DIS                0x00000010
 
480
#define BUS_MASTER_DIS                  0x00000040
 
481
#define BUS_ROM_WRT_EN                  0x00000080
 
482
#define BUS_DIS_ROM                     0x00001000
 
483
#define BUS_PCI_READ_RETRY_EN           0x00002000
 
484
#define BUS_AGP_AD_STEPPING_EN          0x00004000
 
485
#define BUS_PCI_WRT_RETRY_EN            0x00008000
 
486
#define BUS_MSTR_RD_MULT                0x00100000
 
487
#define BUS_MSTR_RD_LINE                0x00200000
 
488
#define BUS_SUSPEND                     0x00400000
 
489
#define LAT_16X                         0x00800000
 
490
#define BUS_RD_DISCARD_EN               0x01000000
 
491
#define BUS_RD_ABORT_EN                 0x02000000
 
492
#define BUS_MSTR_WS                     0x04000000
 
493
#define BUS_PARKING_DIS                 0x08000000
 
494
#define BUS_MSTR_DISCONNECT_EN          0x10000000
 
495
#define BUS_WRT_BURST                   0x20000000
 
496
#define BUS_READ_BURST                  0x40000000
 
497
#define BUS_RDY_READ_DLY                0x80000000
 
498
 
 
499
/* PIXCLKS_CNTL */
 
500
#define PIX2CLK_SRC_SEL_MASK            0x03
 
501
#define PIX2CLK_SRC_SEL_CPUCLK          0x00
 
502
#define PIX2CLK_SRC_SEL_PSCANCLK        0x01
 
503
#define PIX2CLK_SRC_SEL_BYTECLK         0x02
 
504
#define PIX2CLK_SRC_SEL_P2PLLCLK        0x03
 
505
#define PIX2CLK_ALWAYS_ONb              (1<<6)
 
506
#define PIX2CLK_DAC_ALWAYS_ONb          (1<<7)
 
507
#define PIXCLK_TV_SRC_SEL               (1 << 8)
 
508
#define PIXCLK_LVDS_ALWAYS_ONb          (1 << 14)
 
509
#define PIXCLK_TMDS_ALWAYS_ONb          (1 << 15)
 
510
 
 
511
 
 
512
/* CLOCK_CNTL_INDEX bit constants */
 
513
#define PLL_WR_EN                       0x00000080
 
514
 
 
515
/* CONFIG_CNTL bit constants */
 
516
#define CONFIG_SYS_VGA_RAM_EN                   0x00000100
 
517
#define CONFIG_SYS_ATI_REV_ID_MASK              (0xf << 16)
 
518
#define CONFIG_SYS_ATI_REV_A11                  (0 << 16)
 
519
#define CONFIG_SYS_ATI_REV_A12                  (1 << 16)
 
520
#define CONFIG_SYS_ATI_REV_A13                  (2 << 16)
 
521
 
 
522
/* CRTC_EXT_CNTL bit constants */
 
523
#define VGA_ATI_LINEAR                  0x00000008
 
524
#define VGA_128KAP_PAGING               0x00000010
 
525
#define XCRT_CNT_EN                     (1 << 6)
 
526
#define CRTC_HSYNC_DIS                  (1 << 8)
 
527
#define CRTC_VSYNC_DIS                  (1 << 9)
 
528
#define CRTC_DISPLAY_DIS                (1 << 10)
 
529
#define CRTC_CRT_ON                     (1 << 15)
 
530
 
 
531
 
 
532
/* DSTCACHE_CTLSTAT bit constants */
 
533
#define RB2D_DC_FLUSH                   (3 << 0)
 
534
#define RB2D_DC_FLUSH_ALL               0xf
 
535
#define RB2D_DC_BUSY                    (1 << 31)
 
536
 
 
537
 
 
538
/* CRTC_GEN_CNTL bit constants */
 
539
#define CRTC_DBL_SCAN_EN                0x00000001
 
540
#define CRTC_CUR_EN                     0x00010000
 
541
#define CRTC_INTERLACE_EN               (1 << 1)
 
542
#define CRTC_BYPASS_LUT_EN              (1 << 14)
 
543
#define CRTC_EXT_DISP_EN                (1 << 24)
 
544
#define CRTC_EN                         (1 << 25)
 
545
#define CRTC_DISP_REQ_EN_B              (1 << 26)
 
546
 
 
547
/* CRTC_STATUS bit constants */
 
548
#define CRTC_VBLANK                     0x00000001
 
549
 
 
550
/* CRTC2_GEN_CNTL bit constants */
 
551
#define CRT2_ON                         (1 << 7)
 
552
#define CRTC2_DISPLAY_DIS               (1 << 23)
 
553
#define CRTC2_EN                        (1 << 25)
 
554
#define CRTC2_DISP_REQ_EN_B             (1 << 26)
 
555
 
 
556
/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
 
557
#define CUR_LOCK                        0x80000000
 
558
 
 
559
/* GPIO bit constants */
 
560
#define GPIO_A_0                        (1 <<  0)
 
561
#define GPIO_A_1                        (1 <<  1)
 
562
#define GPIO_Y_0                        (1 <<  8)
 
563
#define GPIO_Y_1                        (1 <<  9)
 
564
#define GPIO_EN_0                       (1 << 16)
 
565
#define GPIO_EN_1                       (1 << 17)
 
566
#define GPIO_MASK_0                     (1 << 24)
 
567
#define GPIO_MASK_1                     (1 << 25)
 
568
#define VGA_DDC_DATA_OUTPUT             GPIO_A_0
 
569
#define VGA_DDC_CLK_OUTPUT              GPIO_A_1
 
570
#define VGA_DDC_DATA_INPUT              GPIO_Y_0
 
571
#define VGA_DDC_CLK_INPUT               GPIO_Y_1
 
572
#define VGA_DDC_DATA_OUT_EN             GPIO_EN_0
 
573
#define VGA_DDC_CLK_OUT_EN              GPIO_EN_1
 
574
 
 
575
 
 
576
/* FP bit constants */
 
577
#define FP_CRTC_H_TOTAL_MASK            000003ff
 
578
#define FP_CRTC_H_DISP_MASK             0x01ff0000
 
579
#define FP_CRTC_V_TOTAL_MASK            0x00000fff
 
580
#define FP_CRTC_V_DISP_MASK             0x0fff0000
 
581
#define FP_H_SYNC_STRT_CHAR_MASK        0x00001ff8
 
582
#define FP_H_SYNC_WID_MASK              0x003f0000
 
583
#define FP_V_SYNC_STRT_MASK             0x00000fff
 
584
#define FP_V_SYNC_WID_MASK              0x001f0000
 
585
#define FP_CRTC_H_TOTAL_SHIFT           0x00000000
 
586
#define FP_CRTC_H_DISP_SHIFT            0x00000010
 
587
#define FP_CRTC_V_TOTAL_SHIFT           0x00000000
 
588
#define FP_CRTC_V_DISP_SHIFT            0x00000010
 
589
#define FP_H_SYNC_STRT_CHAR_SHIFT       0x00000003
 
590
#define FP_H_SYNC_WID_SHIFT             0x00000010
 
591
#define FP_V_SYNC_STRT_SHIFT            0x00000000
 
592
#define FP_V_SYNC_WID_SHIFT             0x00000010
 
593
 
 
594
/* FP_GEN_CNTL bit constants */
 
595
#define FP_FPON                         (1 << 0)
 
596
#define FP_TMDS_EN                      (1 << 2)
 
597
#define FP_PANEL_FORMAT                 (1 << 3)
 
598
#define FP_EN_TMDS                      (1 << 7)
 
599
#define FP_DETECT_SENSE                 (1 << 8)
 
600
#define R200_FP_SOURCE_SEL_MASK         (3 << 10)
 
601
#define R200_FP_SOURCE_SEL_CRTC1        (0 << 10)
 
602
#define R200_FP_SOURCE_SEL_CRTC2        (1 << 10)
 
603
#define R200_FP_SOURCE_SEL_RMX          (2 << 10)
 
604
#define R200_FP_SOURCE_SEL_TRANS        (3 << 10)
 
605
#define FP_SEL_CRTC1                    (0 << 13)
 
606
#define FP_SEL_CRTC2                    (1 << 13)
 
607
#define FP_USE_VGA_HSYNC                (1 << 14)
 
608
#define FP_CRTC_DONT_SHADOW_HPAR        (1 << 15)
 
609
#define FP_CRTC_DONT_SHADOW_VPAR        (1 << 16)
 
610
#define FP_CRTC_DONT_SHADOW_HEND        (1 << 17)
 
611
#define FP_CRTC_USE_SHADOW_VEND         (1 << 18)
 
612
#define FP_RMX_HVSYNC_CONTROL_EN        (1 << 20)
 
613
#define FP_DFP_SYNC_SEL                 (1 << 21)
 
614
#define FP_CRTC_LOCK_8DOT               (1 << 22)
 
615
#define FP_CRT_SYNC_SEL                 (1 << 23)
 
616
#define FP_USE_SHADOW_EN                (1 << 24)
 
617
#define FP_CRT_SYNC_ALT                 (1 << 26)
 
618
 
 
619
/* FP2_GEN_CNTL bit constants */
 
620
#define FP2_BLANK_EN                    (1 <<   1)
 
621
#define FP2_ON                          (1 <<   2)
 
622
#define FP2_PANEL_FORMAT                (1 <<   3)
 
623
#define FP2_SOURCE_SEL_MASK             (3 << 10)
 
624
#define FP2_SOURCE_SEL_CRTC2            (1 << 10)
 
625
#define FP2_SRC_SEL_MASK                (3 << 13)
 
626
#define FP2_SRC_SEL_CRTC2               (1 << 13)
 
627
#define FP2_FP_POL                      (1 << 16)
 
628
#define FP2_LP_POL                      (1 << 17)
 
629
#define FP2_SCK_POL                     (1 << 18)
 
630
#define FP2_LCD_CNTL_MASK               (7 << 19)
 
631
#define FP2_PAD_FLOP_EN                 (1 << 22)
 
632
#define FP2_CRC_EN                      (1 << 23)
 
633
#define FP2_CRC_READ_EN                 (1 << 24)
 
634
#define FP2_DV0_EN                      (1 << 25)
 
635
#define FP2_DV0_RATE_SEL_SDR            (1 << 26)
 
636
 
 
637
 
 
638
/* LVDS_GEN_CNTL bit constants */
 
639
#define LVDS_ON                         (1 << 0)
 
640
#define LVDS_DISPLAY_DIS                (1 << 1)
 
641
#define LVDS_PANEL_TYPE                 (1 << 2)
 
642
#define LVDS_PANEL_FORMAT               (1 << 3)
 
643
#define LVDS_EN                         (1 << 7)
 
644
#define LVDS_BL_MOD_LEVEL_MASK          0x0000ff00
 
645
#define LVDS_BL_MOD_LEVEL_SHIFT         8
 
646
#define LVDS_BL_MOD_EN                  (1 << 16)
 
647
#define LVDS_DIGON                      (1 << 18)
 
648
#define LVDS_BLON                       (1 << 19)
 
649
#define LVDS_SEL_CRTC2                  (1 << 23)
 
650
#define LVDS_STATE_MASK \
 
651
        (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
 
652
 
 
653
/* LVDS_PLL_CNTL bit constatns */
 
654
#define HSYNC_DELAY_SHIFT               0x1c
 
655
#define HSYNC_DELAY_MASK                (0xf << 0x1c)
 
656
 
 
657
/* TMDS_TRANSMITTER_CNTL bit constants */
 
658
#define TMDS_PLL_EN                     (1 << 0)
 
659
#define TMDS_PLLRST                     (1 << 1)
 
660
#define TMDS_RAN_PAT_RST                (1 << 7)
 
661
#define TMDS_ICHCSEL                    (1 << 28)
 
662
 
 
663
/* FP_HORZ_STRETCH bit constants */
 
664
#define HORZ_STRETCH_RATIO_MASK         0xffff
 
665
#define HORZ_STRETCH_RATIO_MAX          4096
 
666
#define HORZ_PANEL_SIZE                 (0x1ff << 16)
 
667
#define HORZ_PANEL_SHIFT                16
 
668
#define HORZ_STRETCH_PIXREP             (0 << 25)
 
669
#define HORZ_STRETCH_BLEND              (1 << 26)
 
670
#define HORZ_STRETCH_ENABLE             (1 << 25)
 
671
#define HORZ_AUTO_RATIO                 (1 << 27)
 
672
#define HORZ_FP_LOOP_STRETCH            (0x7 << 28)
 
673
#define HORZ_AUTO_RATIO_INC             (1 << 31)
 
674
 
 
675
 
 
676
/* FP_VERT_STRETCH bit constants */
 
677
#define VERT_STRETCH_RATIO_MASK         0xfff
 
678
#define VERT_STRETCH_RATIO_MAX          4096
 
679
#define VERT_PANEL_SIZE                 (0xfff << 12)
 
680
#define VERT_PANEL_SHIFT                12
 
681
#define VERT_STRETCH_LINREP             (0 << 26)
 
682
#define VERT_STRETCH_BLEND              (1 << 26)
 
683
#define VERT_STRETCH_ENABLE             (1 << 25)
 
684
#define VERT_AUTO_RATIO_EN              (1 << 27)
 
685
#define VERT_FP_LOOP_STRETCH            (0x7 << 28)
 
686
#define VERT_STRETCH_RESERVED           0xf1000000
 
687
 
 
688
/* DAC_CNTL bit constants */
 
689
#define DAC_8BIT_EN                     0x00000100
 
690
#define DAC_4BPP_PIX_ORDER              0x00000200
 
691
#define DAC_CRC_EN                      0x00080000
 
692
#define DAC_MASK_ALL                    (0xff << 24)
 
693
#define DAC_PDWN                        (1 << 15)
 
694
#define DAC_EXPAND_MODE                 (1 << 14)
 
695
#define DAC_VGA_ADR_EN                  (1 << 13)
 
696
#define DAC_RANGE_CNTL                  (3 <<  0)
 
697
#define DAC_RANGE_CNTL_MASK             0x03
 
698
#define DAC_BLANKING                    (1 <<  2)
 
699
#define DAC_CMP_EN                      (1 <<  3)
 
700
#define DAC_CMP_OUTPUT                  (1 <<  7)
 
701
 
 
702
/* DAC_CNTL2 bit constants */
 
703
#define DAC2_EXPAND_MODE                (1 << 14)
 
704
#define DAC2_CMP_EN                     (1 << 7)
 
705
#define DAC2_PALETTE_ACCESS_CNTL        (1 << 5)
 
706
 
 
707
/* DAC_EXT_CNTL bit constants */
 
708
#define DAC_FORCE_BLANK_OFF_EN          (1 << 4)
 
709
#define DAC_FORCE_DATA_EN               (1 << 5)
 
710
#define DAC_FORCE_DATA_SEL_MASK         (3 << 6)
 
711
#define DAC_FORCE_DATA_MASK             0x0003ff00
 
712
#define DAC_FORCE_DATA_SHIFT            8
 
713
 
 
714
/* GEN_RESET_CNTL bit constants */
 
715
#define SOFT_RESET_GUI                  0x00000001
 
716
#define SOFT_RESET_VCLK                 0x00000100
 
717
#define SOFT_RESET_PCLK                 0x00000200
 
718
#define SOFT_RESET_ECP                  0x00000400
 
719
#define SOFT_RESET_DISPENG_XCLK         0x00000800
 
720
 
 
721
/* MEM_CNTL bit constants */
 
722
#define MEM_CTLR_STATUS_IDLE            0x00000000
 
723
#define MEM_CTLR_STATUS_BUSY            0x00100000
 
724
#define MEM_SEQNCR_STATUS_IDLE          0x00000000
 
725
#define MEM_SEQNCR_STATUS_BUSY          0x00200000
 
726
#define MEM_ARBITER_STATUS_IDLE         0x00000000
 
727
#define MEM_ARBITER_STATUS_BUSY         0x00400000
 
728
#define MEM_REQ_UNLOCK                  0x00000000
 
729
#define MEM_REQ_LOCK                    0x00800000
 
730
#define MEM_NUM_CHANNELS_MASK           0x00000001
 
731
#define MEM_USE_B_CH_ONLY               0x00000002
 
732
#define RV100_MEM_HALF_MODE             0x00000008
 
733
#define R300_MEM_NUM_CHANNELS_MASK      0x00000003
 
734
#define R300_MEM_USE_CD_CH_ONLY         0x00000004
 
735
 
 
736
 
 
737
/* RBBM_SOFT_RESET bit constants */
 
738
#define SOFT_RESET_CP                   (1 <<  0)
 
739
#define SOFT_RESET_HI                   (1 <<  1)
 
740
#define SOFT_RESET_SE                   (1 <<  2)
 
741
#define SOFT_RESET_RE                   (1 <<  3)
 
742
#define SOFT_RESET_PP                   (1 <<  4)
 
743
#define SOFT_RESET_E2                   (1 <<  5)
 
744
#define SOFT_RESET_RB                   (1 <<  6)
 
745
#define SOFT_RESET_HDP                  (1 <<  7)
 
746
 
 
747
/* SURFACE_CNTL bit consants */
 
748
#define SURF_TRANSLATION_DIS            (1 << 8)
 
749
#define NONSURF_AP0_SWP_16BPP           (1 << 20)
 
750
#define NONSURF_AP0_SWP_32BPP           (1 << 21)
 
751
#define NONSURF_AP1_SWP_16BPP           (1 << 22)
 
752
#define NONSURF_AP1_SWP_32BPP           (1 << 23)
 
753
 
 
754
#define R200_SURF_TILE_COLOR_MACRO      (1 << 16)
 
755
 
 
756
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
 
757
#define DEFAULT_SC_RIGHT_MAX            (0x1fff << 0)
 
758
#define DEFAULT_SC_BOTTOM_MAX           (0x1fff << 16)
 
759
 
 
760
/* MM_INDEX bit constants */
 
761
#define MM_APER                         0x80000000
 
762
 
 
763
/* CLR_CMP_CNTL bit constants */
 
764
#define COMPARE_SRC_FALSE               0x00000000
 
765
#define COMPARE_SRC_TRUE                0x00000001
 
766
#define COMPARE_SRC_NOT_EQUAL           0x00000004
 
767
#define COMPARE_SRC_EQUAL               0x00000005
 
768
#define COMPARE_SRC_EQUAL_FLIP          0x00000007
 
769
#define COMPARE_DST_FALSE               0x00000000
 
770
#define COMPARE_DST_TRUE                0x00000100
 
771
#define COMPARE_DST_NOT_EQUAL           0x00000400
 
772
#define COMPARE_DST_EQUAL               0x00000500
 
773
#define COMPARE_DESTINATION             0x00000000
 
774
#define COMPARE_SOURCE                  0x01000000
 
775
#define COMPARE_SRC_AND_DST             0x02000000
 
776
 
 
777
 
 
778
/* DP_CNTL bit constants */
 
779
#define DST_X_RIGHT_TO_LEFT             0x00000000
 
780
#define DST_X_LEFT_TO_RIGHT             0x00000001
 
781
#define DST_Y_BOTTOM_TO_TOP             0x00000000
 
782
#define DST_Y_TOP_TO_BOTTOM             0x00000002
 
783
#define DST_X_MAJOR                     0x00000000
 
784
#define DST_Y_MAJOR                     0x00000004
 
785
#define DST_X_TILE                      0x00000008
 
786
#define DST_Y_TILE                      0x00000010
 
787
#define DST_LAST_PEL                    0x00000020
 
788
#define DST_TRAIL_X_RIGHT_TO_LEFT       0x00000000
 
789
#define DST_TRAIL_X_LEFT_TO_RIGHT       0x00000040
 
790
#define DST_TRAP_FILL_RIGHT_TO_LEFT     0x00000000
 
791
#define DST_TRAP_FILL_LEFT_TO_RIGHT     0x00000080
 
792
#define DST_BRES_SIGN                   0x00000100
 
793
#define DST_HOST_BIG_ENDIAN_EN          0x00000200
 
794
#define DST_POLYLINE_NONLAST            0x00008000
 
795
#define DST_RASTER_STALL                0x00010000
 
796
#define DST_POLY_EDGE                   0x00040000
 
797
 
 
798
 
 
799
/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
 
800
#define DST_X_MAJOR_S                   0x00000000
 
801
#define DST_Y_MAJOR_S                   0x00000001
 
802
#define DST_Y_BOTTOM_TO_TOP_S           0x00000000
 
803
#define DST_Y_TOP_TO_BOTTOM_S           0x00008000
 
804
#define DST_X_RIGHT_TO_LEFT_S           0x00000000
 
805
#define DST_X_LEFT_TO_RIGHT_S           0x80000000
 
806
 
 
807
 
 
808
/* DP_DATATYPE bit constants */
 
809
#define DST_8BPP                        0x00000002
 
810
#define DST_15BPP                       0x00000003
 
811
#define DST_16BPP                       0x00000004
 
812
#define DST_24BPP                       0x00000005
 
813
#define DST_32BPP                       0x00000006
 
814
#define DST_8BPP_RGB332                 0x00000007
 
815
#define DST_8BPP_Y8                     0x00000008
 
816
#define DST_8BPP_RGB8                   0x00000009
 
817
#define DST_16BPP_VYUY422               0x0000000b
 
818
#define DST_16BPP_YVYU422               0x0000000c
 
819
#define DST_32BPP_AYUV444               0x0000000e
 
820
#define DST_16BPP_ARGB4444              0x0000000f
 
821
#define BRUSH_SOLIDCOLOR                0x00000d00
 
822
#define SRC_MONO                        0x00000000
 
823
#define SRC_MONO_LBKGD                  0x00010000
 
824
#define SRC_DSTCOLOR                    0x00030000
 
825
#define BYTE_ORDER_MSB_TO_LSB           0x00000000
 
826
#define BYTE_ORDER_LSB_TO_MSB           0x40000000
 
827
#define DP_CONVERSION_TEMP              0x80000000
 
828
#define HOST_BIG_ENDIAN_EN              (1 << 29)
 
829
 
 
830
 
 
831
/* DP_GUI_MASTER_CNTL bit constants */
 
832
#define GMC_SRC_PITCH_OFFSET_DEFAULT    0x00000000
 
833
#define GMC_SRC_PITCH_OFFSET_LEAVE      0x00000001
 
834
#define GMC_DST_PITCH_OFFSET_DEFAULT    0x00000000
 
835
#define GMC_DST_PITCH_OFFSET_LEAVE      0x00000002
 
836
#define GMC_SRC_CLIP_DEFAULT            0x00000000
 
837
#define GMC_SRC_CLIP_LEAVE              0x00000004
 
838
#define GMC_DST_CLIP_DEFAULT            0x00000000
 
839
#define GMC_DST_CLIP_LEAVE              0x00000008
 
840
#define GMC_BRUSH_8x8MONO               0x00000000
 
841
#define GMC_BRUSH_8x8MONO_LBKGD         0x00000010
 
842
#define GMC_BRUSH_8x1MONO               0x00000020
 
843
#define GMC_BRUSH_8x1MONO_LBKGD         0x00000030
 
844
#define GMC_BRUSH_1x8MONO               0x00000040
 
845
#define GMC_BRUSH_1x8MONO_LBKGD         0x00000050
 
846
#define GMC_BRUSH_32x1MONO              0x00000060
 
847
#define GMC_BRUSH_32x1MONO_LBKGD        0x00000070
 
848
#define GMC_BRUSH_32x32MONO             0x00000080
 
849
#define GMC_BRUSH_32x32MONO_LBKGD       0x00000090
 
850
#define GMC_BRUSH_8x8COLOR              0x000000a0
 
851
#define GMC_BRUSH_8x1COLOR              0x000000b0
 
852
#define GMC_BRUSH_1x8COLOR              0x000000c0
 
853
#define GMC_BRUSH_SOLID_COLOR           0x000000d0
 
854
#define GMC_DST_8BPP                    0x00000200
 
855
#define GMC_DST_15BPP                   0x00000300
 
856
#define GMC_DST_16BPP                   0x00000400
 
857
#define GMC_DST_24BPP                   0x00000500
 
858
#define GMC_DST_32BPP                   0x00000600
 
859
#define GMC_DST_8BPP_RGB332             0x00000700
 
860
#define GMC_DST_8BPP_Y8                 0x00000800
 
861
#define GMC_DST_8BPP_RGB8               0x00000900
 
862
#define GMC_DST_16BPP_VYUY422           0x00000b00
 
863
#define GMC_DST_16BPP_YVYU422           0x00000c00
 
864
#define GMC_DST_32BPP_AYUV444           0x00000e00
 
865
#define GMC_DST_16BPP_ARGB4444          0x00000f00
 
866
#define GMC_SRC_MONO                    0x00000000
 
867
#define GMC_SRC_MONO_LBKGD              0x00001000
 
868
#define GMC_SRC_DSTCOLOR                0x00003000
 
869
#define GMC_BYTE_ORDER_MSB_TO_LSB       0x00000000
 
870
#define GMC_BYTE_ORDER_LSB_TO_MSB       0x00004000
 
871
#define GMC_DP_CONVERSION_TEMP_9300     0x00008000
 
872
#define GMC_DP_CONVERSION_TEMP_6500     0x00000000
 
873
#define GMC_DP_SRC_RECT                 0x02000000
 
874
#define GMC_DP_SRC_HOST                 0x03000000
 
875
#define GMC_DP_SRC_HOST_BYTEALIGN       0x04000000
 
876
#define GMC_3D_FCN_EN_CLR               0x00000000
 
877
#define GMC_3D_FCN_EN_SET               0x08000000
 
878
#define GMC_DST_CLR_CMP_FCN_LEAVE       0x00000000
 
879
#define GMC_DST_CLR_CMP_FCN_CLEAR       0x10000000
 
880
#define GMC_AUX_CLIP_LEAVE              0x00000000
 
881
#define GMC_AUX_CLIP_CLEAR              0x20000000
 
882
#define GMC_WRITE_MASK_LEAVE            0x00000000
 
883
#define GMC_WRITE_MASK_SET              0x40000000
 
884
#define GMC_CLR_CMP_CNTL_DIS            (1 << 28)
 
885
#define GMC_SRC_DATATYPE_COLOR          (3 << 12)
 
886
#define ROP3_S                          0x00cc0000
 
887
#define ROP3_SRCCOPY                    0x00cc0000
 
888
#define ROP3_P                          0x00f00000
 
889
#define ROP3_PATCOPY                    0x00f00000
 
890
#define DP_SRC_SOURCE_MASK              (7  << 24)
 
891
#define GMC_BRUSH_NONE                  (15 <<  4)
 
892
#define DP_SRC_SOURCE_MEMORY            (2  << 24)
 
893
#define GMC_BRUSH_SOLIDCOLOR            0x000000d0
 
894
 
 
895
/* DP_MIX bit constants */
 
896
#define DP_SRC_RECT                     0x00000200
 
897
#define DP_SRC_HOST                     0x00000300
 
898
#define DP_SRC_HOST_BYTEALIGN           0x00000400
 
899
 
 
900
/* MPLL_CNTL bit constants */
 
901
#define MPLL_RESET                      0x00000001
 
902
 
 
903
/* MDLL_CKO bit constants */
 
904
#define MCKOA_SLEEP                     0x00000001
 
905
#define MCKOA_RESET                     0x00000002
 
906
#define MCKOA_REF_SKEW_MASK             0x00000700
 
907
#define MCKOA_FB_SKEW_MASK              0x00007000
 
908
 
 
909
/* MDLL_RDCKA bit constants */
 
910
#define MRDCKA0_SLEEP                   0x00000001
 
911
#define MRDCKA0_RESET                   0x00000002
 
912
#define MRDCKA1_SLEEP                   0x00010000
 
913
#define MRDCKA1_RESET                   0x00020000
 
914
 
 
915
/* VCLK_ECP_CNTL constants */
 
916
#define VCLK_SRC_SEL_MASK               0x03
 
917
#define VCLK_SRC_SEL_CPUCLK             0x00
 
918
#define VCLK_SRC_SEL_PSCANCLK           0x01
 
919
#define VCLK_SRC_SEL_BYTECLK            0x02
 
920
#define VCLK_SRC_SEL_PPLLCLK            0x03
 
921
#define PIXCLK_ALWAYS_ONb               0x00000040
 
922
#define PIXCLK_DAC_ALWAYS_ONb           0x00000080
 
923
 
 
924
/* BUS_CNTL1 constants */
 
925
#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK      0x0c000000
 
926
#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT     26
 
927
#define BUS_CNTL1_AGPCLK_VALID                  0x80000000
 
928
 
 
929
/* PLL_PWRMGT_CNTL constants */
 
930
#define PLL_PWRMGT_CNTL_SPLL_TURNOFF            0x00000002
 
931
#define PLL_PWRMGT_CNTL_PPLL_TURNOFF            0x00000004
 
932
#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF           0x00000008
 
933
#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF           0x00000010
 
934
#define PLL_PWRMGT_CNTL_MOBILE_SU               0x00010000
 
935
#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK        0x00020000
 
936
#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK        0x00040000
 
937
 
 
938
/* TV_DAC_CNTL constants */
 
939
#define TV_DAC_CNTL_BGSLEEP                     0x00000040
 
940
#define TV_DAC_CNTL_DETECT                      0x00000010
 
941
#define TV_DAC_CNTL_BGADJ_MASK                  0x000f0000
 
942
#define TV_DAC_CNTL_DACADJ_MASK                 0x00f00000
 
943
#define TV_DAC_CNTL_BGADJ__SHIFT                16
 
944
#define TV_DAC_CNTL_DACADJ__SHIFT               20
 
945
#define TV_DAC_CNTL_RDACPD                      0x01000000
 
946
#define TV_DAC_CNTL_GDACPD                      0x02000000
 
947
#define TV_DAC_CNTL_BDACPD                      0x04000000
 
948
 
 
949
/* DISP_MISC_CNTL constants */
 
950
#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP       (1 << 0)
 
951
#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP     (1 << 1)
 
952
#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP        (1 << 2)
 
953
#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK     (1 << 4)
 
954
#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK   (1 << 5)
 
955
#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK      (1 << 6)
 
956
#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP      (1 << 12)
 
957
#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK    (1 << 15)
 
958
#define DISP_MISC_CNTL_SOFT_RESET_LVDS          (1 << 16)
 
959
#define DISP_MISC_CNTL_SOFT_RESET_TMDS          (1 << 17)
 
960
#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS      (1 << 18)
 
961
#define DISP_MISC_CNTL_SOFT_RESET_TV            (1 << 19)
 
962
 
 
963
/* DISP_PWR_MAN constants */
 
964
#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN    (1 << 0)
 
965
#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN  (1 << 4)
 
966
#define DISP_PWR_MAN_DISP_D3_RST                (1 << 16)
 
967
#define DISP_PWR_MAN_DISP_D3_REG_RST            (1 << 17)
 
968
#define DISP_PWR_MAN_DISP_D3_GRPH_RST           (1 << 18)
 
969
#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST         (1 << 19)
 
970
#define DISP_PWR_MAN_DISP_D3_OV0_RST            (1 << 20)
 
971
#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST         (1 << 21)
 
972
#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST       (1 << 22)
 
973
#define DISP_PWR_MAN_DISP_D1D2_OV0_RST          (1 << 23)
 
974
#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST        (1 << 24)
 
975
#define DISP_PWR_MAN_TV_ENABLE_RST              (1 << 25)
 
976
#define DISP_PWR_MAN_AUTO_PWRUP_EN              (1 << 26)
 
977
 
 
978
/* masks */
 
979
 
 
980
#define CONFIG_MEMSIZE_MASK             0x1f000000
 
981
#define MEM_CFG_TYPE                    0x40000000
 
982
#define DST_OFFSET_MASK                 0x003fffff
 
983
#define DST_PITCH_MASK                  0x3fc00000
 
984
#define DEFAULT_TILE_MASK               0xc0000000
 
985
#define PPLL_DIV_SEL_MASK               0x00000300
 
986
#define PPLL_RESET                      0x00000001
 
987
#define PPLL_SLEEP                      0x00000002
 
988
#define PPLL_ATOMIC_UPDATE_EN           0x00010000
 
989
#define PPLL_REF_DIV_MASK               0x000003ff
 
990
#define PPLL_FB3_DIV_MASK               0x000007ff
 
991
#define PPLL_POST3_DIV_MASK             0x00070000
 
992
#define PPLL_ATOMIC_UPDATE_R            0x00008000
 
993
#define PPLL_ATOMIC_UPDATE_W            0x00008000
 
994
#define PPLL_VGA_ATOMIC_UPDATE_EN       0x00020000
 
995
#define R300_PPLL_REF_DIV_ACC_MASK      (0x3ff << 18)
 
996
#define R300_PPLL_REF_DIV_ACC_SHIFT     18
 
997
 
 
998
#define GUI_ACTIVE                      0x80000000
 
999
 
 
1000
 
 
1001
#define MC_IND_INDEX                    0x01F8
 
1002
#define MC_IND_DATA                     0x01FC
 
1003
 
 
1004
/* PAD_CTLR_STRENGTH */
 
1005
#define PAD_MANUAL_OVERRIDE             0x80000000
 
1006
 
 
1007
/* pllCLK_PIN_CNTL */
 
1008
#define CLK_PIN_CNTL__OSC_EN_MASK                       0x00000001L
 
1009
#define CLK_PIN_CNTL__OSC_EN                            0x00000001L
 
1010
#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK                 0x00000004L
 
1011
#define CLK_PIN_CNTL__XTL_LOW_GAIN                      0x00000004L
 
1012
#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK              0x00000010L
 
1013
#define CLK_PIN_CNTL__DONT_USE_XTALIN                   0x00000010L
 
1014
#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK            0x00000020L
 
1015
#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE                 0x00000020L
 
1016
#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK             0x00000800L
 
1017
#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN                  0x00000800L
 
1018
#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK        0x00001000L
 
1019
#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN             0x00001000L
 
1020
#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK       0x00002000L
 
1021
#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND            0x00002000L
 
1022
#define CLK_PIN_CNTL__CG_SPARE_MASK                     0x00004000L
 
1023
#define CLK_PIN_CNTL__CG_SPARE                          0x00004000L
 
1024
#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK          0x00008000L
 
1025
#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL               0x00008000L
 
1026
#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK               0x00010000L
 
1027
#define CLK_PIN_CNTL__CP_CLK_RUNNING                    0x00010000L
 
1028
#define CLK_PIN_CNTL__CG_SPARE_RD_MASK                  0x00060000L
 
1029
#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK            0x00080000L
 
1030
#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb                 0x00080000L
 
1031
#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK                 0xff000000L
 
1032
 
 
1033
/* pllCLK_PWRMGT_CNTL */
 
1034
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT         0x00000000
 
1035
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT         0x00000001
 
1036
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT         0x00000002
 
1037
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT        0x00000003
 
1038
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT            0x00000004
 
1039
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT            0x00000005
 
1040
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT            0x00000006
 
1041
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT           0x00000007
 
1042
#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT              0x00000008
 
1043
#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT               0x00000009
 
1044
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT          0x0000000a
 
1045
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT      0x0000000c
 
1046
#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT         0x0000000d
 
1047
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT       0x0000000f
 
1048
#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT                 0x00000010
 
1049
#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT             0x00000011
 
1050
#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT               0x00000012
 
1051
#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT               0x00000013
 
1052
#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT                 0x00000014
 
1053
#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT           0x00000015
 
1054
#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT            0x00000018
 
1055
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT        0x0000001e
 
1056
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT           0x0000001f
 
1057
 
 
1058
/* pllP2PLL_CNTL */
 
1059
#define P2PLL_CNTL__P2PLL_RESET_MASK                    0x00000001L
 
1060
#define P2PLL_CNTL__P2PLL_RESET                         0x00000001L
 
1061
#define P2PLL_CNTL__P2PLL_SLEEP_MASK                    0x00000002L
 
1062
#define P2PLL_CNTL__P2PLL_SLEEP                         0x00000002L
 
1063
#define P2PLL_CNTL__P2PLL_TST_EN_MASK                   0x00000004L
 
1064
#define P2PLL_CNTL__P2PLL_TST_EN                        0x00000004L
 
1065
#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK               0x00000010L
 
1066
#define P2PLL_CNTL__P2PLL_REFCLK_SEL                    0x00000010L
 
1067
#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK                0x00000020L
 
1068
#define P2PLL_CNTL__P2PLL_FBCLK_SEL                     0x00000020L
 
1069
#define P2PLL_CNTL__P2PLL_TCPOFF_MASK                   0x00000040L
 
1070
#define P2PLL_CNTL__P2PLL_TCPOFF                        0x00000040L
 
1071
#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK                  0x00000080L
 
1072
#define P2PLL_CNTL__P2PLL_TVCOMAX                       0x00000080L
 
1073
#define P2PLL_CNTL__P2PLL_PCP_MASK                      0x00000700L
 
1074
#define P2PLL_CNTL__P2PLL_PVG_MASK                      0x00003800L
 
1075
#define P2PLL_CNTL__P2PLL_PDC_MASK                      0x0000c000L
 
1076
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK         0x00010000L
 
1077
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN              0x00010000L
 
1078
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK       0x00040000L
 
1079
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC            0x00040000L
 
1080
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK       0x00080000L
 
1081
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET            0x00080000L
 
1082
 
 
1083
/* pllPIXCLKS_CNTL */
 
1084
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT            0x00000000
 
1085
#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT             0x00000004
 
1086
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT         0x00000005
 
1087
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT         0x00000006
 
1088
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT     0x00000007
 
1089
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT          0x00000008
 
1090
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT    0x0000000b
 
1091
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT       0x0000000c
 
1092
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
 
1093
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT     0x0000000e
 
1094
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT     0x0000000f
 
1095
 
 
1096
 
 
1097
/* pllPIXCLKS_CNTL */
 
1098
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK              0x00000003L
 
1099
#define PIXCLKS_CNTL__PIX2CLK_INVERT                    0x00000010L
 
1100
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT                0x00000020L
 
1101
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb                0x00000040L
 
1102
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb            0x00000080L
 
1103
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL                 0x00000100L
 
1104
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb           0x00000800L
 
1105
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb              0x00001000L
 
1106
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb        0x00002000L
 
1107
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb            0x00004000L
 
1108
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb            0x00008000L
 
1109
#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb   (1 << 9)
 
1110
#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb            (1 << 10)
 
1111
#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb        (1 << 13)
 
1112
#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb      (1 << 16)
 
1113
#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb        (1 << 17)
 
1114
#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb           (1 << 18)
 
1115
#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb       (1 << 19)
 
1116
#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
 
1117
 
 
1118
 
 
1119
/* pllP2PLL_DIV_0 */
 
1120
#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK                  0x000007ffL
 
1121
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK         0x00008000L
 
1122
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W              0x00008000L
 
1123
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK         0x00008000L
 
1124
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R              0x00008000L
 
1125
#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK                0x00070000L
 
1126
 
 
1127
/* pllSCLK_CNTL */
 
1128
#define SCLK_CNTL__SCLK_SRC_SEL_MASK                    0x00000007L
 
1129
#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT                  0x00000008L
 
1130
#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT                 0x00000010L
 
1131
#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT                  0x00000020L
 
1132
#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT                  0x00000040L
 
1133
#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT                  0x00000080L
 
1134
#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT                0x00000100L
 
1135
#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT                 0x00000200L
 
1136
#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT                  0x00000400L
 
1137
#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT                  0x00000800L
 
1138
#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT                 0x00001000L
 
1139
#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT                 0x00002000L
 
1140
#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT                  0x00004000L
 
1141
#define SCLK_CNTL__DYN_STOP_LAT_MASK                    0x00007ff8
 
1142
#define SCLK_CNTL__FORCE_DISP2                          0x00008000L
 
1143
#define SCLK_CNTL__FORCE_CP                             0x00010000L
 
1144
#define SCLK_CNTL__FORCE_HDP                            0x00020000L
 
1145
#define SCLK_CNTL__FORCE_DISP1                          0x00040000L
 
1146
#define SCLK_CNTL__FORCE_TOP                            0x00080000L
 
1147
#define SCLK_CNTL__FORCE_E2                             0x00100000L
 
1148
#define SCLK_CNTL__FORCE_SE                             0x00200000L
 
1149
#define SCLK_CNTL__FORCE_IDCT                           0x00400000L
 
1150
#define SCLK_CNTL__FORCE_VIP                            0x00800000L
 
1151
#define SCLK_CNTL__FORCE_RE                             0x01000000L
 
1152
#define SCLK_CNTL__FORCE_PB                             0x02000000L
 
1153
#define SCLK_CNTL__FORCE_TAM                            0x04000000L
 
1154
#define SCLK_CNTL__FORCE_TDM                            0x08000000L
 
1155
#define SCLK_CNTL__FORCE_RB                             0x10000000L
 
1156
#define SCLK_CNTL__FORCE_TV_SCLK                        0x20000000L
 
1157
#define SCLK_CNTL__FORCE_SUBPIC                         0x40000000L
 
1158
#define SCLK_CNTL__FORCE_OV0                            0x80000000L
 
1159
#define SCLK_CNTL__R300_FORCE_VAP                       (1<<21)
 
1160
#define SCLK_CNTL__R300_FORCE_SR                        (1<<25)
 
1161
#define SCLK_CNTL__R300_FORCE_PX                        (1<<26)
 
1162
#define SCLK_CNTL__R300_FORCE_TX                        (1<<27)
 
1163
#define SCLK_CNTL__R300_FORCE_US                        (1<<28)
 
1164
#define SCLK_CNTL__R300_FORCE_SU                        (1<<30)
 
1165
#define SCLK_CNTL__FORCEON_MASK                         0xffff8000L
 
1166
 
 
1167
/* pllSCLK_CNTL2 */
 
1168
#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT           (1<<10)
 
1169
#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT            (1<<11)
 
1170
#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT           (1<<12)
 
1171
#define SCLK_CNTL2__R300_FORCE_TCL                      (1<<13)
 
1172
#define SCLK_CNTL2__R300_FORCE_CBA                      (1<<14)
 
1173
#define SCLK_CNTL2__R300_FORCE_GA                       (1<<15)
 
1174
 
 
1175
/* SCLK_MORE_CNTL */
 
1176
#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT       0x00000001L
 
1177
#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT         0x00000002L
 
1178
#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT        0x00000004L
 
1179
#define SCLK_MORE_CNTL__FORCE_DISPREGS                  0x00000100L
 
1180
#define SCLK_MORE_CNTL__FORCE_MC_GUI                    0x00000200L
 
1181
#define SCLK_MORE_CNTL__FORCE_MC_HOST                   0x00000400L
 
1182
#define SCLK_MORE_CNTL__STOP_SCLK_EN                    0x00001000L
 
1183
#define SCLK_MORE_CNTL__STOP_SCLK_A                     0x00002000L
 
1184
#define SCLK_MORE_CNTL__STOP_SCLK_B                     0x00004000L
 
1185
#define SCLK_MORE_CNTL__STOP_SCLK_C                     0x00008000L
 
1186
#define SCLK_MORE_CNTL__HALF_SPEED_SCLK                 0x00010000L
 
1187
#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP              0x00020000L
 
1188
#define SCLK_MORE_CNTL__TVFB_SOFT_RESET                 0x00040000L
 
1189
#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC               0x00080000L
 
1190
#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK            0x00400000L
 
1191
#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK              0x00800000L
 
1192
#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK              0xff000000L
 
1193
#define SCLK_MORE_CNTL__FORCEON                         0x00000700L
 
1194
 
 
1195
/* MCLK_CNTL */
 
1196
#define MCLK_CNTL__MCLKA_SRC_SEL_MASK                   0x00000007L
 
1197
#define MCLK_CNTL__YCLKA_SRC_SEL_MASK                   0x00000070L
 
1198
#define MCLK_CNTL__MCLKB_SRC_SEL_MASK                   0x00000700L
 
1199
#define MCLK_CNTL__YCLKB_SRC_SEL_MASK                   0x00007000L
 
1200
#define MCLK_CNTL__FORCE_MCLKA_MASK                     0x00010000L
 
1201
#define MCLK_CNTL__FORCE_MCLKA                          0x00010000L
 
1202
#define MCLK_CNTL__FORCE_MCLKB_MASK                     0x00020000L
 
1203
#define MCLK_CNTL__FORCE_MCLKB                          0x00020000L
 
1204
#define MCLK_CNTL__FORCE_YCLKA_MASK                     0x00040000L
 
1205
#define MCLK_CNTL__FORCE_YCLKA                          0x00040000L
 
1206
#define MCLK_CNTL__FORCE_YCLKB_MASK                     0x00080000L
 
1207
#define MCLK_CNTL__FORCE_YCLKB                          0x00080000L
 
1208
#define MCLK_CNTL__FORCE_MC_MASK                        0x00100000L
 
1209
#define MCLK_CNTL__FORCE_MC                             0x00100000L
 
1210
#define MCLK_CNTL__FORCE_AIC_MASK                       0x00200000L
 
1211
#define MCLK_CNTL__FORCE_AIC                            0x00200000L
 
1212
#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK                 0x03000000L
 
1213
#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK                 0x0c000000L
 
1214
#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK                 0x30000000L
 
1215
#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK                 0xc0000000L
 
1216
#define MCLK_CNTL__R300_DISABLE_MC_MCLKA                (1 << 21)
 
1217
#define MCLK_CNTL__R300_DISABLE_MC_MCLKB                (1 << 21)
 
1218
 
 
1219
/* MCLK_MISC */
 
1220
#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK      0x00000003L
 
1221
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK          0x00000004L
 
1222
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL               0x00000004L
 
1223
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK           0x00000008L
 
1224
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL                0x00000008L
 
1225
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK      0x00000010L
 
1226
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN           0x00000010L
 
1227
#define MCLK_MISC__DLL_READY_LAT_MASK                   0x00000100L
 
1228
#define MCLK_MISC__DLL_READY_LAT                        0x00000100L
 
1229
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK        0x00001000L
 
1230
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT             0x00001000L
 
1231
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK        0x00002000L
 
1232
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT             0x00002000L
 
1233
#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK              0x00004000L
 
1234
#define MCLK_MISC__MC_MCLK_DYN_ENABLE                   0x00004000L
 
1235
#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK              0x00008000L
 
1236
#define MCLK_MISC__IO_MCLK_DYN_ENABLE                   0x00008000L
 
1237
#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK               0x00010000L
 
1238
#define MCLK_MISC__CGM_CLK_TO_OUTPIN                    0x00010000L
 
1239
#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK                0x00020000L
 
1240
#define MCLK_MISC__CLK_OR_COUNT_SEL                     0x00020000L
 
1241
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK     0x00040000L
 
1242
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND          0x00040000L
 
1243
#define MCLK_MISC__CGM_SPARE_RD_MASK                    0x00300000L
 
1244
#define MCLK_MISC__CGM_SPARE_A_RD_MASK                  0x00c00000L
 
1245
#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK                0x01000000L
 
1246
#define MCLK_MISC__TCLK_TO_YCLKB_EN                     0x01000000L
 
1247
#define MCLK_MISC__CGM_SPARE_A_MASK                     0x0e000000L
 
1248
 
 
1249
/* VCLK_ECP_CNTL */
 
1250
#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK                0x00000003L
 
1251
#define VCLK_ECP_CNTL__VCLK_INVERT                      0x00000010L
 
1252
#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT                0x00000020L
 
1253
#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb                0x00000040L
 
1254
#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb            0x00000080L
 
1255
#define VCLK_ECP_CNTL__ECP_DIV_MASK                     0x00000300L
 
1256
#define VCLK_ECP_CNTL__ECP_FORCE_ON                     0x00040000L
 
1257
#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON                  0x00080000L
 
1258
#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF  (1<<23)
 
1259
 
 
1260
/* PLL_PWRMGT_CNTL */
 
1261
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK              0x00000001L
 
1262
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF                   0x00000001L
 
1263
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK              0x00000002L
 
1264
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF                   0x00000002L
 
1265
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK              0x00000004L
 
1266
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF                   0x00000004L
 
1267
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK             0x00000008L
 
1268
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF                  0x00000008L
 
1269
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK             0x00000010L
 
1270
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF                  0x00000010L
 
1271
#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK       0x000001e0L
 
1272
#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK           0x00000600L
 
1273
#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK           0x00001800L
 
1274
#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK               0x00002000L
 
1275
#define PLL_PWRMGT_CNTL__PM_MODE_SEL                    0x00002000L
 
1276
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK       0x00004000L
 
1277
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND            0x00004000L
 
1278
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK       0x00008000L
 
1279
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND            0x00008000L
 
1280
#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK                 0x00010000L
 
1281
#define PLL_PWRMGT_CNTL__MOBILE_SU                      0x00010000L
 
1282
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK          0x00020000L
 
1283
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK               0x00020000L
 
1284
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK          0x00040000L
 
1285
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK               0x00040000L
 
1286
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK        0x00080000L
 
1287
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE             0x00080000L
 
1288
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK        0x00100000L
 
1289
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE             0x00100000L
 
1290
#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK        0x00200000L
 
1291
#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD            0x00200000L
 
1292
#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK              0xff000000L
 
1293
 
 
1294
/* CLK_PWRMGT_CNTL */
 
1295
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK           0x00000001L
 
1296
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF                0x00000001L
 
1297
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK           0x00000002L
 
1298
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF                0x00000002L
 
1299
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK           0x00000004L
 
1300
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF                0x00000004L
 
1301
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK          0x00000008L
 
1302
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF               0x00000008L
 
1303
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK              0x00000010L
 
1304
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF                   0x00000010L
 
1305
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK              0x00000020L
 
1306
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF                   0x00000020L
 
1307
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK              0x00000040L
 
1308
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF                   0x00000040L
 
1309
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK             0x00000080L
 
1310
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF                  0x00000080L
 
1311
#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK                0x00000100L
 
1312
#define CLK_PWRMGT_CNTL__MC_CH_MODE                     0x00000100L
 
1313
#define CLK_PWRMGT_CNTL__TEST_MODE_MASK                 0x00000200L
 
1314
#define CLK_PWRMGT_CNTL__TEST_MODE                      0x00000200L
 
1315
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK            0x00000400L
 
1316
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN                 0x00000400L
 
1317
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK        0x00001000L
 
1318
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE             0x00001000L
 
1319
#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK           0x00006000L
 
1320
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK         0x00008000L
 
1321
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT              0x00008000L
 
1322
#define CLK_PWRMGT_CNTL__MC_BUSY_MASK                   0x00010000L
 
1323
#define CLK_PWRMGT_CNTL__MC_BUSY                        0x00010000L
 
1324
#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK               0x00020000L
 
1325
#define CLK_PWRMGT_CNTL__MC_INT_CNTL                    0x00020000L
 
1326
#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK                 0x00040000L
 
1327
#define CLK_PWRMGT_CNTL__MC_SWITCH                      0x00040000L
 
1328
#define CLK_PWRMGT_CNTL__DLL_READY_MASK                 0x00080000L
 
1329
#define CLK_PWRMGT_CNTL__DLL_READY                      0x00080000L
 
1330
#define CLK_PWRMGT_CNTL__DISP_PM_MASK                   0x00100000L
 
1331
#define CLK_PWRMGT_CNTL__DISP_PM                        0x00100000L
 
1332
#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK             0x00e00000L
 
1333
#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK              0x3f000000L
 
1334
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK          0x40000000L
 
1335
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF               0x40000000L
 
1336
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK             0x80000000L
 
1337
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF                  0x80000000L
 
1338
 
 
1339
/* BUS_CNTL1 */
 
1340
#define BUS_CNTL1__PMI_IO_DISABLE_MASK                  0x00000001L
 
1341
#define BUS_CNTL1__PMI_IO_DISABLE                       0x00000001L
 
1342
#define BUS_CNTL1__PMI_MEM_DISABLE_MASK                 0x00000002L
 
1343
#define BUS_CNTL1__PMI_MEM_DISABLE                      0x00000002L
 
1344
#define BUS_CNTL1__PMI_BM_DISABLE_MASK                  0x00000004L
 
1345
#define BUS_CNTL1__PMI_BM_DISABLE                       0x00000004L
 
1346
#define BUS_CNTL1__PMI_INT_DISABLE_MASK                 0x00000008L
 
1347
#define BUS_CNTL1__PMI_INT_DISABLE                      0x00000008L
 
1348
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK      0x00000020L
 
1349
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE           0x00000020L
 
1350
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK      0x00000100L
 
1351
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS           0x00000100L
 
1352
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK      0x00000200L
 
1353
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS           0x00000200L
 
1354
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK      0x00000400L
 
1355
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS           0x00000400L
 
1356
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
 
1357
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS     0x00000800L
 
1358
#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK             0x0c000000L
 
1359
#define BUS_CNTL1__SEND_SBA_LATENCY_MASK                0x70000000L
 
1360
#define BUS_CNTL1__AGPCLK_VALID_MASK                    0x80000000L
 
1361
#define BUS_CNTL1__AGPCLK_VALID                         0x80000000L
 
1362
 
 
1363
/* BUS_CNTL1 */
 
1364
#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT                0x00000000
 
1365
#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT               0x00000001
 
1366
#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT                0x00000002
 
1367
#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT               0x00000003
 
1368
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT    0x00000005
 
1369
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT    0x00000008
 
1370
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT    0x00000009
 
1371
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT    0x0000000a
 
1372
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
 
1373
#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT           0x0000001a
 
1374
#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT              0x0000001c
 
1375
#define BUS_CNTL1__AGPCLK_VALID__SHIFT                  0x0000001f
 
1376
 
 
1377
/* CRTC_OFFSET_CNTL */
 
1378
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK           0x0000000fL
 
1379
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK     0x000000f0L
 
1380
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK       0x00004000L
 
1381
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT            0x00004000L
 
1382
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK             0x00008000L
 
1383
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN                  0x00008000L
 
1384
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK    0x00010000L
 
1385
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL         0x00010000L
 
1386
#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK    0x00020000L
 
1387
#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN         0x00020000L
 
1388
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK      0x000c0000L
 
1389
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK  0x00100000L
 
1390
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN       0x00100000L
 
1391
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK         0x00200000L
 
1392
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC              0x00200000L
 
1393
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
 
1394
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN  0x10000000L
 
1395
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
 
1396
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
 
1397
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK     0x40000000L
 
1398
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET          0x40000000L
 
1399
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK         0x80000000L
 
1400
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK              0x80000000L
 
1401
 
 
1402
/* CRTC_GEN_CNTL */
 
1403
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK            0x00000001L
 
1404
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN                 0x00000001L
 
1405
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK           0x00000002L
 
1406
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN                0x00000002L
 
1407
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK              0x00000010L
 
1408
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN                   0x00000010L
 
1409
#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK              0x00000f00L
 
1410
#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK                0x00008000L
 
1411
#define CRTC_GEN_CNTL__CRTC_ICON_EN                     0x00008000L
 
1412
#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK                 0x00010000L
 
1413
#define CRTC_GEN_CNTL__CRTC_CUR_EN                      0x00010000L
 
1414
#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK             0x00060000L
 
1415
#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK               0x00700000L
 
1416
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK            0x01000000L
 
1417
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN                 0x01000000L
 
1418
#define CRTC_GEN_CNTL__CRTC_EN_MASK                     0x02000000L
 
1419
#define CRTC_GEN_CNTL__CRTC_EN                          0x02000000L
 
1420
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK          0x04000000L
 
1421
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B               0x04000000L
 
1422
 
 
1423
/* CRTC2_GEN_CNTL */
 
1424
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK          0x00000001L
 
1425
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN               0x00000001L
 
1426
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK         0x00000002L
 
1427
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN              0x00000002L
 
1428
#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK        0x00000010L
 
1429
#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE             0x00000010L
 
1430
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK       0x00000020L
 
1431
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE            0x00000020L
 
1432
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK       0x00000040L
 
1433
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE            0x00000040L
 
1434
#define CRTC2_GEN_CNTL__CRT2_ON_MASK                    0x00000080L
 
1435
#define CRTC2_GEN_CNTL__CRT2_ON                         0x00000080L
 
1436
#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK            0x00000f00L
 
1437
#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK              0x00008000L
 
1438
#define CRTC2_GEN_CNTL__CRTC2_ICON_EN                   0x00008000L
 
1439
#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK               0x00010000L
 
1440
#define CRTC2_GEN_CNTL__CRTC2_CUR_EN                    0x00010000L
 
1441
#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK             0x00700000L
 
1442
#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK          0x00800000L
 
1443
#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS               0x00800000L
 
1444
#define CRTC2_GEN_CNTL__CRTC2_EN_MASK                   0x02000000L
 
1445
#define CRTC2_GEN_CNTL__CRTC2_EN                        0x02000000L
 
1446
#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK        0x04000000L
 
1447
#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B             0x04000000L
 
1448
#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK            0x08000000L
 
1449
#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN                 0x08000000L
 
1450
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK            0x10000000L
 
1451
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS                 0x10000000L
 
1452
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK            0x20000000L
 
1453
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS                 0x20000000L
 
1454
 
 
1455
/* AGP_CNTL */
 
1456
#define AGP_CNTL__MAX_IDLE_CLK_MASK                     0x000000ffL
 
1457
#define AGP_CNTL__HOLD_RD_FIFO_MASK                     0x00000100L
 
1458
#define AGP_CNTL__HOLD_RD_FIFO                          0x00000100L
 
1459
#define AGP_CNTL__HOLD_RQ_FIFO_MASK                     0x00000200L
 
1460
#define AGP_CNTL__HOLD_RQ_FIFO                          0x00000200L
 
1461
#define AGP_CNTL__EN_2X_STBB_MASK                       0x00000400L
 
1462
#define AGP_CNTL__EN_2X_STBB                            0x00000400L
 
1463
#define AGP_CNTL__FORCE_FULL_SBA_MASK                   0x00000800L
 
1464
#define AGP_CNTL__FORCE_FULL_SBA                        0x00000800L
 
1465
#define AGP_CNTL__SBA_DIS_MASK                          0x00001000L
 
1466
#define AGP_CNTL__SBA_DIS                               0x00001000L
 
1467
#define AGP_CNTL__AGP_REV_ID_MASK                       0x00002000L
 
1468
#define AGP_CNTL__AGP_REV_ID                            0x00002000L
 
1469
#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK                0x00004000L
 
1470
#define AGP_CNTL__REG_CRIPPLE_AGP4X                     0x00004000L
 
1471
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK              0x00008000L
 
1472
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X                   0x00008000L
 
1473
#define AGP_CNTL__FORCE_INT_VREF_MASK                   0x00010000L
 
1474
#define AGP_CNTL__FORCE_INT_VREF                        0x00010000L
 
1475
#define AGP_CNTL__PENDING_SLOTS_VAL_MASK                0x00060000L
 
1476
#define AGP_CNTL__PENDING_SLOTS_SEL_MASK                0x00080000L
 
1477
#define AGP_CNTL__PENDING_SLOTS_SEL                     0x00080000L
 
1478
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK            0x00100000L
 
1479
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X                 0x00100000L
 
1480
#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK               0x00200000L
 
1481
#define AGP_CNTL__DIS_QUEUED_GNT_FIX                    0x00200000L
 
1482
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK          0x00400000L
 
1483
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET               0x00400000L
 
1484
#define AGP_CNTL__EN_RBFCALM_MASK                       0x00800000L
 
1485
#define AGP_CNTL__EN_RBFCALM                            0x00800000L
 
1486
#define AGP_CNTL__FORCE_EXT_VREF_MASK                   0x01000000L
 
1487
#define AGP_CNTL__FORCE_EXT_VREF                        0x01000000L
 
1488
#define AGP_CNTL__DIS_RBF_MASK                          0x02000000L
 
1489
#define AGP_CNTL__DIS_RBF                               0x02000000L
 
1490
#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK               0x04000000L
 
1491
#define AGP_CNTL__DELAY_FIRST_SBA_EN                    0x04000000L
 
1492
#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK              0x38000000L
 
1493
#define AGP_CNTL__AGP_MISC_MASK                         0xc0000000L
 
1494
 
 
1495
/* AGP_CNTL */
 
1496
#define AGP_CNTL__MAX_IDLE_CLK__SHIFT                   0x00000000
 
1497
#define AGP_CNTL__HOLD_RD_FIFO__SHIFT                   0x00000008
 
1498
#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT                   0x00000009
 
1499
#define AGP_CNTL__EN_2X_STBB__SHIFT                     0x0000000a
 
1500
#define AGP_CNTL__FORCE_FULL_SBA__SHIFT                 0x0000000b
 
1501
#define AGP_CNTL__SBA_DIS__SHIFT                        0x0000000c
 
1502
#define AGP_CNTL__AGP_REV_ID__SHIFT                     0x0000000d
 
1503
#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT              0x0000000e
 
1504
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT            0x0000000f
 
1505
#define AGP_CNTL__FORCE_INT_VREF__SHIFT                 0x00000010
 
1506
#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT              0x00000011
 
1507
#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT              0x00000013
 
1508
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT          0x00000014
 
1509
#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT             0x00000015
 
1510
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT        0x00000016
 
1511
#define AGP_CNTL__EN_RBFCALM__SHIFT                     0x00000017
 
1512
#define AGP_CNTL__FORCE_EXT_VREF__SHIFT                 0x00000018
 
1513
#define AGP_CNTL__DIS_RBF__SHIFT                        0x00000019
 
1514
#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT             0x0000001a
 
1515
#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT            0x0000001b
 
1516
#define AGP_CNTL__AGP_MISC__SHIFT                       0x0000001e
 
1517
 
 
1518
/* DISP_MISC_CNTL */
 
1519
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK         0x00000001L
 
1520
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP              0x00000001L
 
1521
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK       0x00000002L
 
1522
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP            0x00000002L
 
1523
#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK          0x00000004L
 
1524
#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP               0x00000004L
 
1525
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK       0x00000010L
 
1526
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK            0x00000010L
 
1527
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK     0x00000020L
 
1528
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK          0x00000020L
 
1529
#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK        0x00000040L
 
1530
#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK             0x00000040L
 
1531
#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK              0x00000300L
 
1532
#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK           0x00000400L
 
1533
#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN                0x00000400L
 
1534
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK        0x00001000L
 
1535
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP             0x00001000L
 
1536
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK      0x00008000L
 
1537
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK           0x00008000L
 
1538
#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK            0x00010000L
 
1539
#define DISP_MISC_CNTL__SOFT_RESET_LVDS                 0x00010000L
 
1540
#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK            0x00020000L
 
1541
#define DISP_MISC_CNTL__SOFT_RESET_TMDS                 0x00020000L
 
1542
#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK        0x00040000L
 
1543
#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS             0x00040000L
 
1544
#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK              0x00080000L
 
1545
#define DISP_MISC_CNTL__SOFT_RESET_TV                   0x00080000L
 
1546
#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK     0x00f00000L
 
1547
#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK      0x0f000000L
 
1548
#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK      0xf0000000L
 
1549
 
 
1550
/* DISP_PWR_MAN */
 
1551
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK      0x00000001L
 
1552
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN           0x00000001L
 
1553
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK    0x00000010L
 
1554
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN         0x00000010L
 
1555
#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK            0x00000300L
 
1556
#define DISP_PWR_MAN__DISP_D3_RST_MASK                  0x00010000L
 
1557
#define DISP_PWR_MAN__DISP_D3_RST                       0x00010000L
 
1558
#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK              0x00020000L
 
1559
#define DISP_PWR_MAN__DISP_D3_REG_RST                   0x00020000L
 
1560
#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK             0x00040000L
 
1561
#define DISP_PWR_MAN__DISP_D3_GRPH_RST                  0x00040000L
 
1562
#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK           0x00080000L
 
1563
#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST                0x00080000L
 
1564
#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK              0x00100000L
 
1565
#define DISP_PWR_MAN__DISP_D3_OV0_RST                   0x00100000L
 
1566
#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK           0x00200000L
 
1567
#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST                0x00200000L
 
1568
#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK         0x00400000L
 
1569
#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST              0x00400000L
 
1570
#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK            0x00800000L
 
1571
#define DISP_PWR_MAN__DISP_D1D2_OV0_RST                 0x00800000L
 
1572
#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK          0x01000000L
 
1573
#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST               0x01000000L
 
1574
#define DISP_PWR_MAN__TV_ENABLE_RST_MASK                0x02000000L
 
1575
#define DISP_PWR_MAN__TV_ENABLE_RST                     0x02000000L
 
1576
#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK                0x04000000L
 
1577
#define DISP_PWR_MAN__AUTO_PWRUP_EN                     0x04000000L
 
1578
 
 
1579
/* MC_IND_INDEX */
 
1580
#define MC_IND_INDEX__MC_IND_ADDR_MASK                  0x0000001fL
 
1581
#define MC_IND_INDEX__MC_IND_WR_EN_MASK                 0x00000100L
 
1582
#define MC_IND_INDEX__MC_IND_WR_EN                      0x00000100L
 
1583
 
 
1584
/* MC_IND_DATA */
 
1585
#define MC_IND_DATA__MC_IND_DATA_MASK                   0xffffffffL
 
1586
 
 
1587
/* MC_CHP_IO_CNTL_A1 */
 
1588
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT         0x00000000
 
1589
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT          0x00000001
 
1590
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT        0x00000002
 
1591
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT        0x00000003
 
1592
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT         0x00000004
 
1593
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT          0x00000005
 
1594
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT        0x00000006
 
1595
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT        0x00000007
 
1596
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT         0x00000008
 
1597
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT       0x00000009
 
1598
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT       0x0000000a
 
1599
#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT          0x0000000c
 
1600
#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT           0x0000000e
 
1601
#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT            0x00000010
 
1602
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT          0x00000012
 
1603
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT          0x00000014
 
1604
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT       0x00000016
 
1605
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT      0x00000017
 
1606
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT          0x00000018
 
1607
#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT          0x0000001a
 
1608
#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT          0x0000001c
 
1609
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT      0x0000001e
 
1610
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT      0x0000001f
 
1611
 
 
1612
/* MC_CHP_IO_CNTL_B1 */
 
1613
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT         0x00000000
 
1614
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT          0x00000001
 
1615
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT        0x00000002
 
1616
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT        0x00000003
 
1617
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT         0x00000004
 
1618
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT          0x00000005
 
1619
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT        0x00000006
 
1620
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT        0x00000007
 
1621
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT         0x00000008
 
1622
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT       0x00000009
 
1623
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT       0x0000000a
 
1624
#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT          0x0000000c
 
1625
#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT           0x0000000e
 
1626
#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT            0x00000010
 
1627
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT          0x00000012
 
1628
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT          0x00000014
 
1629
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT       0x00000016
 
1630
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT      0x00000017
 
1631
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT          0x00000018
 
1632
#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT          0x0000001a
 
1633
#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT          0x0000001c
 
1634
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT      0x0000001e
 
1635
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT      0x0000001f
 
1636
 
 
1637
/* MC_CHP_IO_CNTL_A1 */
 
1638
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK           0x00000001L
 
1639
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA                0x00000001L
 
1640
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK            0x00000002L
 
1641
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA                 0x00000002L
 
1642
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK          0x00000004L
 
1643
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA               0x00000004L
 
1644
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK          0x00000008L
 
1645
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA               0x00000008L
 
1646
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK           0x00000010L
 
1647
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA                0x00000010L
 
1648
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK            0x00000020L
 
1649
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA                 0x00000020L
 
1650
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK          0x00000040L
 
1651
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA               0x00000040L
 
1652
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK          0x00000080L
 
1653
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA               0x00000080L
 
1654
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK           0x00000100L
 
1655
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA                0x00000100L
 
1656
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK         0x00000200L
 
1657
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA              0x00000200L
 
1658
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK         0x00000400L
 
1659
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA              0x00000400L
 
1660
#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK            0x00003000L
 
1661
#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK             0x0000c000L
 
1662
#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK              0x00030000L
 
1663
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK            0x000c0000L
 
1664
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK            0x00300000L
 
1665
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK         0x00400000L
 
1666
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA              0x00400000L
 
1667
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK        0x00800000L
 
1668
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA             0x00800000L
 
1669
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK            0x03000000L
 
1670
#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK            0x0c000000L
 
1671
#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK            0x10000000L
 
1672
#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA                 0x10000000L
 
1673
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK        0x40000000L
 
1674
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A             0x40000000L
 
1675
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK        0x80000000L
 
1676
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A             0x80000000L
 
1677
 
 
1678
/* MC_CHP_IO_CNTL_B1 */
 
1679
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK           0x00000001L
 
1680
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB                0x00000001L
 
1681
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK            0x00000002L
 
1682
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB                 0x00000002L
 
1683
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK          0x00000004L
 
1684
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB               0x00000004L
 
1685
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK          0x00000008L
 
1686
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB               0x00000008L
 
1687
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK           0x00000010L
 
1688
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB                0x00000010L
 
1689
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK            0x00000020L
 
1690
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB                 0x00000020L
 
1691
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK          0x00000040L
 
1692
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB               0x00000040L
 
1693
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK          0x00000080L
 
1694
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB               0x00000080L
 
1695
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK           0x00000100L
 
1696
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB                0x00000100L
 
1697
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK         0x00000200L
 
1698
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB              0x00000200L
 
1699
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK         0x00000400L
 
1700
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB              0x00000400L
 
1701
#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK            0x00003000L
 
1702
#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK             0x0000c000L
 
1703
#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK              0x00030000L
 
1704
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK            0x000c0000L
 
1705
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK            0x00300000L
 
1706
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK         0x00400000L
 
1707
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB              0x00400000L
 
1708
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK        0x00800000L
 
1709
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB             0x00800000L
 
1710
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK            0x03000000L
 
1711
#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK            0x0c000000L
 
1712
#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK            0x10000000L
 
1713
#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB                 0x10000000L
 
1714
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK        0x40000000L
 
1715
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B             0x40000000L
 
1716
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK        0x80000000L
 
1717
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B             0x80000000L
 
1718
 
 
1719
/* MEM_SDRAM_MODE_REG */
 
1720
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK           0x00007fffL
 
1721
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK         0x000f0000L
 
1722
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK        0x00700000L
 
1723
#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK        0x00800000L
 
1724
#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY             0x00800000L
 
1725
#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK        0x01000000L
 
1726
#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY             0x01000000L
 
1727
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK       0x02000000L
 
1728
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD            0x02000000L
 
1729
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK      0x04000000L
 
1730
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA           0x04000000L
 
1731
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK       0x08000000L
 
1732
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR            0x08000000L
 
1733
#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK       0x10000000L
 
1734
#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE            0x10000000L
 
1735
#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK            0x20000000L
 
1736
#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL                 0x20000000L
 
1737
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK           0x40000000L
 
1738
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE                0x40000000L
 
1739
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK        0x80000000L
 
1740
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET             0x80000000L
 
1741
 
 
1742
/* MEM_SDRAM_MODE_REG */
 
1743
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT         0x00000000
 
1744
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT       0x00000010
 
1745
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT      0x00000014
 
1746
#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT      0x00000017
 
1747
#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT      0x00000018
 
1748
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT     0x00000019
 
1749
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT    0x0000001a
 
1750
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT     0x0000001b
 
1751
#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT     0x0000001c
 
1752
#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT          0x0000001d
 
1753
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT         0x0000001e
 
1754
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT      0x0000001f
 
1755
 
 
1756
/* MEM_REFRESH_CNTL */
 
1757
#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK         0x000000ffL
 
1758
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK          0x00000100L
 
1759
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS               0x00000100L
 
1760
#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK          0x00000200L
 
1761
#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE               0x00000200L
 
1762
#define MEM_REFRESH_CNTL__MEM_TRFC_MASK                 0x0000f000L
 
1763
#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK         0x00010000L
 
1764
#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE              0x00010000L
 
1765
#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK        0x00020000L
 
1766
#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE             0x00020000L
 
1767
#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK         0x00040000L
 
1768
#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE              0x00040000L
 
1769
#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK        0x00080000L
 
1770
#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE             0x00080000L
 
1771
#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK        0x00100000L
 
1772
#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE             0x00100000L
 
1773
#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK          0x00c00000L
 
1774
#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK         0x01000000L
 
1775
#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE              0x01000000L
 
1776
#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK        0x02000000L
 
1777
#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE             0x02000000L
 
1778
#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK         0x04000000L
 
1779
#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE              0x04000000L
 
1780
#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK        0x08000000L
 
1781
#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE             0x08000000L
 
1782
#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK        0x10000000L
 
1783
#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE             0x10000000L
 
1784
#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK          0xc0000000L
 
1785
 
 
1786
/* MC_STATUS */
 
1787
#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK               0x00000001L
 
1788
#define MC_STATUS__MEM_PWRUP_COMPL_A                    0x00000001L
 
1789
#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK               0x00000002L
 
1790
#define MC_STATUS__MEM_PWRUP_COMPL_B                    0x00000002L
 
1791
#define MC_STATUS__MC_IDLE_MASK                         0x00000004L
 
1792
#define MC_STATUS__MC_IDLE                              0x00000004L
 
1793
#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK              0x00000078L
 
1794
#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK              0x00000780L
 
1795
#define MC_STATUS__TEST_OUT_R_BACK_MASK                 0x00000800L
 
1796
#define MC_STATUS__TEST_OUT_R_BACK                      0x00000800L
 
1797
#define MC_STATUS__DUMMY_OUT_R_BACK_MASK                0x00001000L
 
1798
#define MC_STATUS__DUMMY_OUT_R_BACK                     0x00001000L
 
1799
#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK            0x0001e000L
 
1800
#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK            0x001e0000L
 
1801
#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK           0x01e00000L
 
1802
#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK           0x1e000000L
 
1803
 
 
1804
/* MDLL_CKO */
 
1805
#define MDLL_CKO__MCKOA_SLEEP_MASK                      0x00000001L
 
1806
#define MDLL_CKO__MCKOA_SLEEP                           0x00000001L
 
1807
#define MDLL_CKO__MCKOA_RESET_MASK                      0x00000002L
 
1808
#define MDLL_CKO__MCKOA_RESET                           0x00000002L
 
1809
#define MDLL_CKO__MCKOA_RANGE_MASK                      0x0000000cL
 
1810
#define MDLL_CKO__ERSTA_SOUTSEL_MASK                    0x00000030L
 
1811
#define MDLL_CKO__MCKOA_FB_SEL_MASK                     0x000000c0L
 
1812
#define MDLL_CKO__MCKOA_REF_SKEW_MASK                   0x00000700L
 
1813
#define MDLL_CKO__MCKOA_FB_SKEW_MASK                    0x00007000L
 
1814
#define MDLL_CKO__MCKOA_BP_SEL_MASK                     0x00008000L
 
1815
#define MDLL_CKO__MCKOA_BP_SEL                          0x00008000L
 
1816
#define MDLL_CKO__MCKOB_SLEEP_MASK                      0x00010000L
 
1817
#define MDLL_CKO__MCKOB_SLEEP                           0x00010000L
 
1818
#define MDLL_CKO__MCKOB_RESET_MASK                      0x00020000L
 
1819
#define MDLL_CKO__MCKOB_RESET                           0x00020000L
 
1820
#define MDLL_CKO__MCKOB_RANGE_MASK                      0x000c0000L
 
1821
#define MDLL_CKO__ERSTB_SOUTSEL_MASK                    0x00300000L
 
1822
#define MDLL_CKO__MCKOB_FB_SEL_MASK                     0x00c00000L
 
1823
#define MDLL_CKO__MCKOB_REF_SKEW_MASK                   0x07000000L
 
1824
#define MDLL_CKO__MCKOB_FB_SKEW_MASK                    0x70000000L
 
1825
#define MDLL_CKO__MCKOB_BP_SEL_MASK                     0x80000000L
 
1826
#define MDLL_CKO__MCKOB_BP_SEL                          0x80000000L
 
1827
 
 
1828
/* MDLL_RDCKA */
 
1829
#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK                  0x00000001L
 
1830
#define MDLL_RDCKA__MRDCKA0_SLEEP                       0x00000001L
 
1831
#define MDLL_RDCKA__MRDCKA0_RESET_MASK                  0x00000002L
 
1832
#define MDLL_RDCKA__MRDCKA0_RESET                       0x00000002L
 
1833
#define MDLL_RDCKA__MRDCKA0_RANGE_MASK                  0x0000000cL
 
1834
#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK                0x00000030L
 
1835
#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK                 0x000000c0L
 
1836
#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK               0x00000700L
 
1837
#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK                 0x00000800L
 
1838
#define MDLL_RDCKA__MRDCKA0_SINSEL                      0x00000800L
 
1839
#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK                0x00007000L
 
1840
#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK                 0x00008000L
 
1841
#define MDLL_RDCKA__MRDCKA0_BP_SEL                      0x00008000L
 
1842
#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK                  0x00010000L
 
1843
#define MDLL_RDCKA__MRDCKA1_SLEEP                       0x00010000L
 
1844
#define MDLL_RDCKA__MRDCKA1_RESET_MASK                  0x00020000L
 
1845
#define MDLL_RDCKA__MRDCKA1_RESET                       0x00020000L
 
1846
#define MDLL_RDCKA__MRDCKA1_RANGE_MASK                  0x000c0000L
 
1847
#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK                0x00300000L
 
1848
#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK                 0x00c00000L
 
1849
#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK               0x07000000L
 
1850
#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK                 0x08000000L
 
1851
#define MDLL_RDCKA__MRDCKA1_SINSEL                      0x08000000L
 
1852
#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK                0x70000000L
 
1853
#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK                 0x80000000L
 
1854
#define MDLL_RDCKA__MRDCKA1_BP_SEL                      0x80000000L
 
1855
 
 
1856
/* MDLL_RDCKB */
 
1857
#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK                  0x00000001L
 
1858
#define MDLL_RDCKB__MRDCKB0_SLEEP                       0x00000001L
 
1859
#define MDLL_RDCKB__MRDCKB0_RESET_MASK                  0x00000002L
 
1860
#define MDLL_RDCKB__MRDCKB0_RESET                       0x00000002L
 
1861
#define MDLL_RDCKB__MRDCKB0_RANGE_MASK                  0x0000000cL
 
1862
#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK                0x00000030L
 
1863
#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK                 0x000000c0L
 
1864
#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK               0x00000700L
 
1865
#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK                 0x00000800L
 
1866
#define MDLL_RDCKB__MRDCKB0_SINSEL                      0x00000800L
 
1867
#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK                0x00007000L
 
1868
#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK                 0x00008000L
 
1869
#define MDLL_RDCKB__MRDCKB0_BP_SEL                      0x00008000L
 
1870
#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK                  0x00010000L
 
1871
#define MDLL_RDCKB__MRDCKB1_SLEEP                       0x00010000L
 
1872
#define MDLL_RDCKB__MRDCKB1_RESET_MASK                  0x00020000L
 
1873
#define MDLL_RDCKB__MRDCKB1_RESET                       0x00020000L
 
1874
#define MDLL_RDCKB__MRDCKB1_RANGE_MASK                  0x000c0000L
 
1875
#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK                0x00300000L
 
1876
#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK                 0x00c00000L
 
1877
#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK               0x07000000L
 
1878
#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK                 0x08000000L
 
1879
#define MDLL_RDCKB__MRDCKB1_SINSEL                      0x08000000L
 
1880
#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK                0x70000000L
 
1881
#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK                 0x80000000L
 
1882
#define MDLL_RDCKB__MRDCKB1_BP_SEL                      0x80000000L
 
1883
 
 
1884
#define MDLL_R300_RDCK__MRDCKA_SLEEP                    0x00000001L
 
1885
#define MDLL_R300_RDCK__MRDCKA_RESET                    0x00000002L
 
1886
#define MDLL_R300_RDCK__MRDCKB_SLEEP                    0x00000004L
 
1887
#define MDLL_R300_RDCK__MRDCKB_RESET                    0x00000008L
 
1888
#define MDLL_R300_RDCK__MRDCKC_SLEEP                    0x00000010L
 
1889
#define MDLL_R300_RDCK__MRDCKC_RESET                    0x00000020L
 
1890
#define MDLL_R300_RDCK__MRDCKD_SLEEP                    0x00000040L
 
1891
#define MDLL_R300_RDCK__MRDCKD_RESET                    0x00000080L
 
1892
 
 
1893
#define pllCLK_PIN_CNTL                         0x0001
 
1894
#define pllPPLL_CNTL                            0x0002
 
1895
#define pllPPLL_REF_DIV                         0x0003
 
1896
#define pllPPLL_DIV_0                           0x0004
 
1897
#define pllPPLL_DIV_1                           0x0005
 
1898
#define pllPPLL_DIV_2                           0x0006
 
1899
#define pllPPLL_DIV_3                           0x0007
 
1900
#define pllVCLK_ECP_CNTL                        0x0008
 
1901
#define pllHTOTAL_CNTL                          0x0009
 
1902
#define pllM_SPLL_REF_FB_DIV                    0x000A
 
1903
#define pllAGP_PLL_CNTL                         0x000B
 
1904
#define pllSPLL_CNTL                            0x000C
 
1905
#define pllSCLK_CNTL                            0x000D
 
1906
#define pllMPLL_CNTL                            0x000E
 
1907
#define pllMDLL_CKO                             0x000F
 
1908
#define pllMDLL_RDCKA                           0x0010
 
1909
#define pllMDLL_RDCKB                           0x0011
 
1910
#define pllMCLK_CNTL                            0x0012
 
1911
#define pllPLL_TEST_CNTL                        0x0013
 
1912
#define pllCLK_PWRMGT_CNTL                      0x0014
 
1913
#define pllPLL_PWRMGT_CNTL                      0x0015
 
1914
#define pllCG_TEST_MACRO_RW_WRITE               0x0016
 
1915
#define pllCG_TEST_MACRO_RW_READ                0x0017
 
1916
#define pllCG_TEST_MACRO_RW_DATA                0x0018
 
1917
#define pllCG_TEST_MACRO_RW_CNTL                0x0019
 
1918
#define pllDISP_TEST_MACRO_RW_WRITE             0x001A
 
1919
#define pllDISP_TEST_MACRO_RW_READ              0x001B
 
1920
#define pllDISP_TEST_MACRO_RW_DATA              0x001C
 
1921
#define pllDISP_TEST_MACRO_RW_CNTL              0x001D
 
1922
#define pllSCLK_CNTL2                           0x001E
 
1923
#define pllMCLK_MISC                            0x001F
 
1924
#define pllTV_PLL_FINE_CNTL                     0x0020
 
1925
#define pllTV_PLL_CNTL                          0x0021
 
1926
#define pllTV_PLL_CNTL1                         0x0022
 
1927
#define pllTV_DTO_INCREMENTS                    0x0023
 
1928
#define pllSPLL_AUX_CNTL                        0x0024
 
1929
#define pllMPLL_AUX_CNTL                        0x0025
 
1930
#define pllP2PLL_CNTL                           0x002A
 
1931
#define pllP2PLL_REF_DIV                        0x002B
 
1932
#define pllP2PLL_DIV_0                          0x002C
 
1933
#define pllPIXCLKS_CNTL                         0x002D
 
1934
#define pllHTOTAL2_CNTL                         0x002E
 
1935
#define pllSSPLL_CNTL                           0x0030
 
1936
#define pllSSPLL_REF_DIV                        0x0031
 
1937
#define pllSSPLL_DIV_0                          0x0032
 
1938
#define pllSS_INT_CNTL                          0x0033
 
1939
#define pllSS_TST_CNTL                          0x0034
 
1940
#define pllSCLK_MORE_CNTL                       0x0035
 
1941
 
 
1942
#define ixMC_PERF_CNTL                          0x0000
 
1943
#define ixMC_PERF_SEL                           0x0001
 
1944
#define ixMC_PERF_REGION_0                      0x0002
 
1945
#define ixMC_PERF_REGION_1                      0x0003
 
1946
#define ixMC_PERF_COUNT_0                       0x0004
 
1947
#define ixMC_PERF_COUNT_1                       0x0005
 
1948
#define ixMC_PERF_COUNT_2                       0x0006
 
1949
#define ixMC_PERF_COUNT_3                       0x0007
 
1950
#define ixMC_PERF_COUNT_MEMCH_A                 0x0008
 
1951
#define ixMC_PERF_COUNT_MEMCH_B                 0x0009
 
1952
#define ixMC_IMP_CNTL                           0x000A
 
1953
#define ixMC_CHP_IO_CNTL_A0                     0x000B
 
1954
#define ixMC_CHP_IO_CNTL_A1                     0x000C
 
1955
#define ixMC_CHP_IO_CNTL_B0                     0x000D
 
1956
#define ixMC_CHP_IO_CNTL_B1                     0x000E
 
1957
#define ixMC_IMP_CNTL_0                         0x000F
 
1958
#define ixTC_MISMATCH_1                         0x0010
 
1959
#define ixTC_MISMATCH_2                         0x0011
 
1960
#define ixMC_BIST_CTRL                          0x0012
 
1961
#define ixREG_COLLAR_WRITE                      0x0013
 
1962
#define ixREG_COLLAR_READ                       0x0014
 
1963
#define ixR300_MC_IMP_CNTL                      0x0018
 
1964
#define ixR300_MC_CHP_IO_CNTL_A0                0x0019
 
1965
#define ixR300_MC_CHP_IO_CNTL_A1                0x001a
 
1966
#define ixR300_MC_CHP_IO_CNTL_B0                0x001b
 
1967
#define ixR300_MC_CHP_IO_CNTL_B1                0x001c
 
1968
#define ixR300_MC_CHP_IO_CNTL_C0                0x001d
 
1969
#define ixR300_MC_CHP_IO_CNTL_C1                0x001e
 
1970
#define ixR300_MC_CHP_IO_CNTL_D0                0x001f
 
1971
#define ixR300_MC_CHP_IO_CNTL_D1                0x0020
 
1972
#define ixR300_MC_IMP_CNTL_0                    0x0021
 
1973
#define ixR300_MC_ELPIDA_CNTL                   0x0022
 
1974
#define ixR300_MC_CHP_IO_OE_CNTL_CD             0x0023
 
1975
#define ixR300_MC_READ_CNTL_CD                  0x0024
 
1976
#define ixR300_MC_MC_INIT_WR_LAT_TIMER          0x0025
 
1977
#define ixR300_MC_DEBUG_CNTL                    0x0026
 
1978
#define ixR300_MC_BIST_CNTL_0                   0x0028
 
1979
#define ixR300_MC_BIST_CNTL_1                   0x0029
 
1980
#define ixR300_MC_BIST_CNTL_2                   0x002a
 
1981
#define ixR300_MC_BIST_CNTL_3                   0x002b
 
1982
#define ixR300_MC_BIST_CNTL_4                   0x002c
 
1983
#define ixR300_MC_BIST_CNTL_5                   0x002d
 
1984
#define ixR300_MC_IMP_STATUS                    0x002e
 
1985
#define ixR300_MC_DLL_CNTL                      0x002f
 
1986
#define NB_TOM                                  0x15C
 
1987
 
 
1988
#endif  /* _RADEON_H */