2
* Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
3
* Author: Tor Krill <tor@excito.com>
5
* SPDX-License-Identifier: GPL-2.0+
7
* This is a driver for Silicon Image sil3114 sata chip modelled on
15
#include <asm/byteorder.h>
20
#include "sata_sil3114.h"
22
/* Convert sectorsize to wordsize */
23
#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
26
u8 sil3114_spin_up (int num);
27
u8 sil3114_spin_down (int num);
28
static int sata_bus_softreset (int num);
29
static void sata_identify (int num, int dev);
30
static u8 check_power_mode (int num);
31
static void sata_port (struct sata_ioports *ioport);
32
static void set_Feature_cmd (int num, int dev);
33
static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
34
unsigned int max, u8 usealtstatus);
35
static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
36
static void msleep (int count);
38
static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
40
static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
42
static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
45
__raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
49
static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
52
*sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
57
static int sata_bus_softreset (int num)
61
port[num].dev_mask = 1;
63
port[num].ctl_reg = 0x08; /*Default value of control reg */
64
writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
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writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
68
writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
70
/* spec mandates ">= 2ms" before checking status.
71
* We wait 150ms, because that was the magic delay used for
72
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
73
* between when the ATA command register is written, and then
74
* status is checked. Because waiting for "a while" before
75
* checking status is fine, post SRST, we perform this magic
79
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
80
while ((status & ATA_BUSY)) {
82
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
85
if (status & ATA_BUSY) {
86
printf ("ata%u is slow to respond,plz be patient\n", num);
89
while ((status & ATA_BUSY)) {
91
status = sata_chk_status (&port[num].ioaddr, 0);
94
if (status & ATA_BUSY) {
95
printf ("ata%u failed to respond : ", num);
96
printf ("bus reset failed\n");
97
port[num].dev_mask = 0;
103
static void sata_identify (int num, int dev)
105
u8 cmd = 0, status = 0, devno = num;
106
u16 iobuf[ATA_SECTOR_WORDS];
109
memset (iobuf, 0, sizeof (iobuf));
111
if (!(port[num].dev_mask & 0x01)) {
112
printf ("dev%d is not present on port#%d\n", dev, num);
116
debug ("port=%d dev=%d\n", num, dev);
119
cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
120
writeb (cmd, port[num].ioaddr.command_addr);
121
readb (port[num].ioaddr.altstatus_addr);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
125
if (status & ATA_ERR) {
126
printf ("\ndevice not responding\n");
127
port[num].dev_mask &= ~0x01;
131
input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
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ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
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debug ("Specific config: %x\n", iobuf[2]);
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/* we require LBA and DMA support (bits 8 & 9 of word 49) */
138
if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
139
debug ("ata%u: no dma/lba\n", num);
144
n_sectors = ata_id_n_sectors (iobuf);
146
if (n_sectors == 0) {
147
port[num].dev_mask &= ~0x01;
150
ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
151
ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
152
ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
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ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
154
ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
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ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
157
/* TODO - atm we asume harddisk ie not removable */
158
sata_dev_desc[devno].removable = 0;
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sata_dev_desc[devno].lba = (u32) n_sectors;
161
debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
164
if (iobuf[83] & (1 << 10)) {
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sata_dev_desc[devno].lba48 = 1;
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sata_dev_desc[devno].lba48 = 0;
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sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
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sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
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sata_dev_desc[devno].lun = 0; /* just to fill something in... */
177
static void set_Feature_cmd (int num, int dev)
181
if (!(port[num].dev_mask & 0x01)) {
182
debug ("dev%d is not present on port#%d\n", dev, num);
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writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
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writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
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writeb (0, port[num].ioaddr.lbal_addr);
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writeb (0, port[num].ioaddr.lbam_addr);
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writeb (0, port[num].ioaddr.lbah_addr);
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writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
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writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
198
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
199
if ((status & (ATA_BUSY | ATA_ERR))) {
200
printf ("Error : status 0x%02x\n", status);
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port[num].dev_mask &= ~0x01;
205
u8 sil3114_spin_down (int num)
209
debug ("Spin down disk\n");
211
if (!(port[num].dev_mask & 0x01)) {
212
debug ("Device ata%d is not present\n", num);
216
if ((status = check_power_mode (num)) == 0x00) {
217
debug ("Already in standby\n");
221
if (status == 0x01) {
222
printf ("Failed to check power mode on ata%d\n", num);
226
if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
227
printf ("Device ata%d not ready\n", num);
231
writeb (0x00, port[num].ioaddr.feature_addr);
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writeb (0x00, port[num].ioaddr.nsect_addr);
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writeb (0x00, port[num].ioaddr.lbal_addr);
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writeb (0x00, port[num].ioaddr.lbam_addr);
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writeb (0x00, port[num].ioaddr.lbah_addr);
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writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
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writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
242
if ((status & (ATA_BUSY | ATA_ERR))) {
243
printf ("Error waiting for disk spin down: status 0x%02x\n",
245
port[num].dev_mask &= ~0x01;
251
u8 sil3114_spin_up (int num)
255
debug ("Spin up disk\n");
257
if (!(port[num].dev_mask & 0x01)) {
258
debug ("Device ata%d is not present\n", num);
262
if ((status = check_power_mode (num)) != 0x00) {
263
if (status == 0x01) {
264
printf ("Failed to check power mode on ata%d\n", num);
267
/* should be up and running already */
272
if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
273
printf ("Device ata%d not ready\n", num);
277
debug ("Stautus of device check: %d\n", status);
279
writeb (0x00, port[num].ioaddr.feature_addr);
281
writeb (0x00, port[num].ioaddr.nsect_addr);
282
writeb (0x00, port[num].ioaddr.lbal_addr);
283
writeb (0x00, port[num].ioaddr.lbam_addr);
284
writeb (0x00, port[num].ioaddr.lbah_addr);
286
writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
287
writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
289
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
290
if ((status & (ATA_BUSY | ATA_ERR))) {
291
printf ("Error waiting for disk spin up: status 0x%02x\n",
293
port[num].dev_mask &= ~0x01;
297
/* Wait for disk to enter Active state */
300
status = check_power_mode (num);
301
} while ((status == 0x00) || (status == 0x80));
303
if (status == 0x01) {
304
printf ("Falied waiting for disk to spin up\n");
311
/* Return value is not the usual here
312
* 0x00 - Device stand by
313
* 0x01 - Operation failed
315
* 0xff - Device active
317
static u8 check_power_mode (int num)
321
if (!(port[num].dev_mask & 0x01)) {
322
debug ("Device ata%d is not present\n", num);
326
if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
327
printf ("Device ata%d not ready\n", num);
331
writeb (0, port[num].ioaddr.feature_addr);
332
writeb (0, port[num].ioaddr.nsect_addr);
333
writeb (0, port[num].ioaddr.lbal_addr);
334
writeb (0, port[num].ioaddr.lbam_addr);
335
writeb (0, port[num].ioaddr.lbah_addr);
337
writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
338
writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
340
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
341
if ((status & (ATA_BUSY | ATA_ERR))) {
343
("Error waiting for check power mode complete : status 0x%02x\n",
345
port[num].dev_mask &= ~0x01;
348
res = readb (port[num].ioaddr.nsect_addr);
349
debug ("Check powermode: %d\n", res);
354
static void sata_port (struct sata_ioports *ioport)
356
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
357
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
358
ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
359
ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
360
ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
361
ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
362
ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
363
ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
364
ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
365
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
368
static u8 wait_for_irq (int num, unsigned int max)
371
u32 port = iobase[5];
374
port += VND_TF_CNST_CH0;
377
port += VND_TF_CNST_CH1;
380
port += VND_TF_CNST_CH2;
383
port += VND_TF_CNST_CH3;
390
if (readl (port) & VND_TF_CNST_INTST) {
400
static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
401
unsigned int max, u8 usealtstatus)
406
if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
411
} while ((status & bits) && (max > 0));
416
static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
419
return readb (ioaddr->status_addr);
421
return readb (ioaddr->altstatus_addr);
425
static void msleep (int count)
429
for (i = 0; i < count; i++)
433
/* Read up to 255 sectors
435
* Returns sectors read
437
static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
443
u64 blknr = (u64) block;
445
if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
446
printf ("Device ata%d not ready\n", device);
450
/* Set up transfer */
453
/* write high bits */
454
writeb (0, port[device].ioaddr.nsect_addr);
455
writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
456
writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
457
writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
460
writeb (blkcnt, port[device].ioaddr.nsect_addr);
461
writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
462
writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
463
writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
467
writeb (ATA_LBA, port[device].ioaddr.device_addr);
468
writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
472
writeb (ATA_LBA | ((blknr >> 24) & 0xF),
473
port[device].ioaddr.device_addr);
474
writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
477
status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
479
if (status & ATA_BUSY) {
482
printf ("Device %d not responding status %d\n", device, status);
483
err = readb (port[device].ioaddr.error_addr);
484
printf ("Error reg = 0x%x\n", err);
490
if (wait_for_irq (device, 500)) {
491
printf ("ata%u irq failed\n", device);
495
status = sata_chk_status (&port[device].ioaddr, 0);
496
if (status & ATA_ERR) {
497
printf ("ata%u error %d\n", device,
498
readb (port[device].ioaddr.error_addr));
501
/* Read one sector */
502
input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
503
buff += ATA_SECTOR_WORDS;
510
ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
513
u16 *buffer = (u16 *) buff;
515
u64 blknr = (u64) block;
516
unsigned char lba48 = 0;
519
if (blknr > 0xfffffff) {
520
if (!sata_dev_desc[device].lba48) {
521
printf ("Drive doesn't support 48-bit addressing\n");
524
/* more than 28 bits used, use 48bit mode */
537
status = do_one_read (device, blknr, sread, buffer, lba48);
538
if (status != sread) {
539
printf ("Read failed\n");
546
buffer += sread * ATA_SECTOR_WORDS;
551
ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
554
u16 *buffer = (u16 *) buff;
555
unsigned char status = 0, num = 0;
556
u64 blknr = (u64) block;
558
unsigned char lba48 = 0;
560
if (blknr > 0xfffffff) {
561
if (!sata_dev_desc[device].lba48) {
562
printf ("Drive doesn't support 48-bit addressing\n");
565
/* more than 28 bits used, use 48bit mode */
572
while (blkcnt-- > 0) {
573
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
574
if (status & ATA_BUSY) {
575
printf ("ata%u failed to respond\n", port[num].port_no);
580
/* write high bits */
581
writeb (0, port[num].ioaddr.nsect_addr);
582
writeb ((blknr >> 24) & 0xFF,
583
port[num].ioaddr.lbal_addr);
584
writeb ((blknr >> 32) & 0xFF,
585
port[num].ioaddr.lbam_addr);
586
writeb ((blknr >> 40) & 0xFF,
587
port[num].ioaddr.lbah_addr);
590
writeb (1, port[num].ioaddr.nsect_addr);
591
writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
592
writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
593
writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
596
writeb (ATA_LBA, port[num].ioaddr.device_addr);
597
writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
601
writeb (ATA_LBA | ((blknr >> 24) & 0xF),
602
port[num].ioaddr.device_addr);
603
writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
607
/*may take up to 4 sec */
608
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
609
if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
610
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
611
device, (ulong) blknr, status);
615
output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
616
readb (port[num].ioaddr.altstatus_addr);
621
buffer += ATA_SECTOR_WORDS;
626
/* Driver implementation */
627
static u8 sil_get_device_cache_line (pci_dev_t pdev)
630
pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
634
int init_sata (int dev)
636
static u8 init_done = 0;
649
if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
654
/* Read out all BARs, even though we only use MMIO from BAR5 */
655
pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
656
pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
657
pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
658
pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
659
pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
660
pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
662
if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
663
(iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
664
(iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
665
printf ("Error no base addr for SATA controller\n");
670
/* mask off unused bits */
671
iobase[0] &= 0xfffffffc;
672
iobase[1] &= 0xfffffff8;
673
iobase[2] &= 0xfffffffc;
674
iobase[3] &= 0xfffffff8;
675
iobase[4] &= 0xfffffff0;
676
iobase[5] &= 0xfffffc00;
678
/* from sata_sil in Linux kernel */
679
cls = sil_get_device_cache_line (devno);
682
cls++; /* cls = (line_size/8)+1 */
683
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
684
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
685
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
686
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
688
printf ("Cache line not set. Driver may not function\n");
691
/* Enable operation */
692
pci_read_config_word (devno, PCI_COMMAND, &cmd);
693
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
694
pci_write_config_word (devno, PCI_COMMAND, cmd);
696
/* Disable interrupt usage */
697
pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
698
sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
699
pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
705
/* Check if device is connected to port */
706
int sata_bus_probe (int portno)
708
u32 port = iobase[5];
712
port += VND_SSTATUS_CH0;
715
port += VND_SSTATUS_CH1;
718
port += VND_SSTATUS_CH2;
721
port += VND_SSTATUS_CH3;
727
if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
734
int sata_phy_reset (int portno)
736
u32 port = iobase[5];
740
port += VND_SCONTROL_CH0;
743
port += VND_SCONTROL_CH1;
746
port += VND_SCONTROL_CH2;
749
port += VND_SCONTROL_CH3;
755
writel (val | SATA_SC_DET_RST, port);
757
writel (val & ~SATA_SC_DET_RST, port);
761
int scan_sata (int dev)
763
/* A bit brain dead, but the code has a legacy */
767
port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
768
port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
769
(iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
770
port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
772
#if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
775
port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
776
port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
777
(iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
778
port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
780
#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
783
port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
784
port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
785
(iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
786
port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
788
#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
791
port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
792
port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
793
(iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
794
port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
798
printf ("Tried to scan unknown port: ata%d\n", dev);
802
/* Initialize other registers */
803
sata_port (&port[dev].ioaddr);
805
/* Check for attached device */
806
if (!sata_bus_probe (dev)) {
807
port[dev].port_state = 0;
808
debug ("SATA#%d port is not present\n", dev);
810
debug ("SATA#%d port is present\n", dev);
811
if (sata_bus_softreset (dev)) {
812
/* soft reset failed, try a hard one */
813
sata_phy_reset (dev);
814
if (sata_bus_softreset (dev)) {
815
port[dev].port_state = 0;
817
port[dev].port_state = 1;
820
port[dev].port_state = 1;
823
if (port[dev].port_state == 1) {
824
/* Probe device and set xfer mode */
825
sata_identify (dev, 0);
826
set_Feature_cmd (dev, 0);