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Viewing changes to roms/u-boot/include/faraday/ftsdmc020.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/include/faraday/ftsdmc020.h
 
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/*
 
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 * (C) Copyright 2009 Faraday Technology
 
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 * Po-Yu Chuang <ratbert@faraday-tech.com>
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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/*
 
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 * SDRAM Controller
 
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 */
 
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#ifndef __FTSDMC020_H
 
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#define __FTSDMC020_H
 
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#define FTSDMC020_OFFSET_TP0            0x00
 
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#define FTSDMC020_OFFSET_TP1            0x04
 
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#define FTSDMC020_OFFSET_CR             0x08
 
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#define FTSDMC020_OFFSET_BANK0_BSR      0x0C
 
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#define FTSDMC020_OFFSET_BANK1_BSR      0x10
 
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#define FTSDMC020_OFFSET_BANK2_BSR      0x14
 
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#define FTSDMC020_OFFSET_BANK3_BSR      0x18
 
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#define FTSDMC020_OFFSET_BANK4_BSR      0x1C
 
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#define FTSDMC020_OFFSET_BANK5_BSR      0x20
 
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#define FTSDMC020_OFFSET_BANK6_BSR      0x24
 
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#define FTSDMC020_OFFSET_BANK7_BSR      0x28
 
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#define FTSDMC020_OFFSET_ACR            0x34
 
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/*
 
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 * Timing Parametet 0 Register
 
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 */
 
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#define FTSDMC020_TP0_TCL(x)    ((x) & 0x3)
 
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#define FTSDMC020_TP0_TWR(x)    (((x) & 0x3) << 4)
 
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#define FTSDMC020_TP0_TRF(x)    (((x) & 0xf) << 8)
 
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#define FTSDMC020_TP0_TRCD(x)   (((x) & 0x7) << 12)
 
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#define FTSDMC020_TP0_TRP(x)    (((x) & 0xf) << 16)
 
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#define FTSDMC020_TP0_TRAS(x)   (((x) & 0xf) << 20)
 
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/*
 
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 * Timing Parametet 1 Register
 
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 */
 
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#define FTSDMC020_TP1_REF_INTV(x)       ((x) & 0xffff)
 
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#define FTSDMC020_TP1_INI_REFT(x)       (((x) & 0xf) << 16)
 
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#define FTSDMC020_TP1_INI_PREC(x)       (((x) & 0xf) << 20)
 
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/*
 
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 * Configuration Register
 
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 */
 
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#define FTSDMC020_CR_SREF       (1 << 0)
 
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#define FTSDMC020_CR_PWDN       (1 << 1)
 
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#define FTSDMC020_CR_ISMR       (1 << 2)
 
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#define FTSDMC020_CR_IREF       (1 << 3)
 
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#define FTSDMC020_CR_IPREC      (1 << 4)
 
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#define FTSDMC020_CR_REFTYPE    (1 << 5)
 
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/*
 
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 * SDRAM External Bank Base/Size Register
 
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 */
 
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#define FTSDMC020_BANK_ENABLE           (1 << 28)
 
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#define FTSDMC020_BANK_BASE(addr)       (((addr) >> 20) << 16)
 
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#define FTSDMC020_BANK_DDW_X4           (0 << 12)
 
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#define FTSDMC020_BANK_DDW_X8           (1 << 12)
 
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#define FTSDMC020_BANK_DDW_X16          (2 << 12)
 
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#define FTSDMC020_BANK_DDW_X32          (3 << 12)
 
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#define FTSDMC020_BANK_DSZ_16M          (0 << 8)
 
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#define FTSDMC020_BANK_DSZ_64M          (1 << 8)
 
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#define FTSDMC020_BANK_DSZ_128M         (2 << 8)
 
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#define FTSDMC020_BANK_DSZ_256M         (3 << 8)
 
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#define FTSDMC020_BANK_MBW_8            (0 << 4)
 
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#define FTSDMC020_BANK_MBW_16           (1 << 4)
 
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#define FTSDMC020_BANK_MBW_32           (2 << 4)
 
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#define FTSDMC020_BANK_SIZE_1M          0x0
 
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#define FTSDMC020_BANK_SIZE_2M          0x1
 
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#define FTSDMC020_BANK_SIZE_4M          0x2
 
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#define FTSDMC020_BANK_SIZE_8M          0x3
 
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#define FTSDMC020_BANK_SIZE_16M         0x4
 
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#define FTSDMC020_BANK_SIZE_32M         0x5
 
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#define FTSDMC020_BANK_SIZE_64M         0x6
 
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#define FTSDMC020_BANK_SIZE_128M        0x7
 
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#define FTSDMC020_BANK_SIZE_256M        0x8
 
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/*
 
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 * Arbiter Control Register
 
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 */
 
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#define FTSDMC020_ACR_TOC(x)    ((x) & 0x1f)
 
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#define FTSDMC020_ACR_TOE       (1 << 8)
 
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#endif  /* __FTSDMC020_H */