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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/include/configs/t3corp.h
 
1
/*
 
2
 * (C) Copyright 2010
 
3
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 
4
 *
 
5
 * SPDX-License-Identifier:     GPL-2.0+
 
6
 */
 
7
 
 
8
/*
 
9
 * t3corp.h - configuration for T3CORP (460GT)
 
10
 */
 
11
#ifndef __CONFIG_H
 
12
#define __CONFIG_H
 
13
 
 
14
/*
 
15
 * High Level Configuration Options
 
16
 */
 
17
#define CONFIG_460GT            1       /* Specific PPC460GT    */
 
18
#define CONFIG_440              1
 
19
 
 
20
#ifndef CONFIG_SYS_TEXT_BASE
 
21
#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
 
22
#endif
 
23
 
 
24
#define CONFIG_HOSTNAME         t3corp
 
25
 
 
26
/*
 
27
 * Include common defines/options for all AMCC/APM eval boards
 
28
 */
 
29
#include "amcc-common.h"
 
30
 
 
31
#define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
 
32
 
 
33
#define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
 
34
#define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
 
35
#define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
 
36
#define CONFIG_BOARD_TYPES              1       /* support board types */
 
37
#define CONFIG_FIT
 
38
#define CFG_ALT_MEMTEST
 
39
 
 
40
/*
 
41
 * Base addresses -- Note these are effective addresses where the
 
42
 * actual resources get mapped (not physical addresses)
 
43
 */
 
44
#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory */
 
45
#define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs */
 
46
#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
 
47
 
 
48
#define CONFIG_SYS_PCIE_MEMBASE         0xb0000000      /* mapped PCIe mem */
 
49
#define CONFIG_SYS_PCIE_MEMSIZE         0x08000000      /* incr for PCIe */
 
50
#define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
 
51
 
 
52
#define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
 
53
#define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
 
54
#define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
 
55
#define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
 
56
 
 
57
#define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit phys addr */
 
58
 
 
59
/* base address of inbound PCIe window */
 
60
#define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit phys addr */
 
61
 
 
62
/* EBC stuff */
 
63
#define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped here */
 
64
#define CONFIG_SYS_FLASH_SIZE           (64 << 20)
 
65
 
 
66
#define CONFIG_SYS_FPGA1_BASE           0xe0000000
 
67
#define CONFIG_SYS_FPGA2_BASE           0xe2000000
 
68
#define CONFIG_SYS_FPGA3_BASE           0xe4000000
 
69
 
 
70
#define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space */
 
71
#define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
 
72
#define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
 
73
#define CONFIG_SYS_FLASH_BASE_PHYS \
 
74
        (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
 
75
        | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 
76
 
 
77
#define CONFIG_SYS_OCM_BASE             0xE7000000      /* OCM: 64k */
 
78
#define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k */
 
79
#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
 
80
#define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
 
81
 
 
82
/*
 
83
 * Initial RAM & stack pointer (placed in OCM)
 
84
 */
 
85
#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM */
 
86
#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
 
87
#define CONFIG_SYS_GBL_DATA_OFFSET \
 
88
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
89
#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 
90
 
 
91
/*
 
92
 * Serial Port
 
93
 */
 
94
#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 
95
 
 
96
/*
 
97
 * Environment
 
98
 */
 
99
/*
 
100
 * Define here the location of the environment variables (flash).
 
101
 */
 
102
#define CONFIG_ENV_IS_IN_FLASH          /* use flash for environment vars */
 
103
 
 
104
/*
 
105
 * Flash related
 
106
 */
 
107
#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 
108
#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 
109
#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 
110
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 
111
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method      */
 
112
#define CONFIG_SYS_FLASH_PROTECTION     /* use hardware flash protection */
 
113
 
 
114
#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 
115
                        (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
 
116
#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff,      /* don't set    */ \
 
117
                        0xbddf }                /* set async read mode  */
 
118
#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks */
 
119
#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors p. chip*/
 
120
 
 
121
#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms*/
 
122
#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms*/
 
123
 
 
124
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buff'd writes (20x faster)*/
 
125
#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 
126
 
 
127
#define CONFIG_ENV_SECT_SIZE            0x20000 /* sector size */
 
128
#define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - \
 
129
                                         CONFIG_ENV_SECT_SIZE)
 
130
#define CONFIG_ENV_SIZE                 0x4000  /* env sector size */
 
131
 
 
132
/* Address and size of Redundant Environment Sector     */
 
133
#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 
134
#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 
135
 
 
136
/*
 
137
 * DDR2 SDRAM
 
138
 */
 
139
#define CONFIG_SYS_MBYTES_SDRAM         256
 
140
#define CONFIG_DDR_ECC
 
141
#define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 
142
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 
143
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 
144
#undef CONFIG_PPC4xx_DDR_METHOD_A
 
145
#define CONFIG_DDR_RFDC_FIXED           0x000001D7 /* optimal value */
 
146
 
 
147
/* DDR1/2 SDRAM Device Control Register Data Values */
 
148
/* Memory Queue */
 
149
#define CONFIG_SYS_SDRAM_R0BAS          (SDRAM_RXBAS_SDBA_ENCODE(0) | \
 
150
                                         SDRAM_RXBAS_SDSZ_256)
 
151
#define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 
152
#define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 
153
#define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 
154
#define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 
155
#define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 
156
#define CONFIG_SYS_SDRAM_CONF1LL        0x80001C00
 
157
#define CONFIG_SYS_SDRAM_CONF1HB        0x80001C80
 
158
#define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 
159
 
 
160
#define CAS_LATENCY                     JEDEC_MA_MR_CL_DDR2_5_0_CLK
 
161
 
 
162
/* DDR1/2 SDRAM Device Control Register Data Values */
 
163
#define CONFIG_SYS_SDRAM0_MB0CF         (SDRAM_RXBAS_SDAM_MODE7         | \
 
164
                                         SDRAM_RXBAS_SDBE_ENABLE)
 
165
#define CONFIG_SYS_SDRAM0_MB1CF         SDRAM_RXBAS_SDBE_DISABLE
 
166
#define CONFIG_SYS_SDRAM0_MB2CF         SDRAM_RXBAS_SDBE_DISABLE
 
167
#define CONFIG_SYS_SDRAM0_MB3CF         SDRAM_RXBAS_SDBE_DISABLE
 
168
#define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_MCHK_GEN          | \
 
169
                                         SDRAM_MCOPT1_PMU_OPEN          | \
 
170
                                         SDRAM_MCOPT1_DMWD_32           | \
 
171
                                         SDRAM_MCOPT1_8_BANKS           | \
 
172
                                         SDRAM_MCOPT1_DDR2_TYPE         | \
 
173
                                         SDRAM_MCOPT1_QDEP              | \
 
174
                                         SDRAM_MCOPT1_RWOO_DISABLED     | \
 
175
                                         SDRAM_MCOPT1_WOOO_DISABLED     | \
 
176
                                         SDRAM_MCOPT1_DREF_NORMAL)
 
177
#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 
178
#define CONFIG_SYS_SDRAM0_MODT0         SDRAM_MODT_EB0W_ENABLE
 
179
#define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 
180
#define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 
181
#define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 
182
#define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 
183
                                         SDRAM_CODT_DQS_1_8_V_DDR2      | \
 
184
                                         SDRAM_CODT_IO_NMODE)
 
185
#define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 
186
#define CONFIG_SYS_SDRAM0_INITPLR0                                      \
 
187
        (SDRAM_INITPLR_ENABLE                                           | \
 
188
         SDRAM_INITPLR_IMWT_ENCODE(80)                                  | \
 
189
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 
190
#define CONFIG_SYS_SDRAM0_INITPLR1                                      \
 
191
        (SDRAM_INITPLR_ENABLE                                           | \
 
192
         SDRAM_INITPLR_IMWT_ENCODE(3)                                   | \
 
193
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)                 | \
 
194
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 
195
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 
196
#define CONFIG_SYS_SDRAM0_INITPLR2                                      \
 
197
        (SDRAM_INITPLR_ENABLE                                           | \
 
198
         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 
199
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 
200
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                        | \
 
201
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 
202
#define CONFIG_SYS_SDRAM0_INITPLR3                                      \
 
203
        (SDRAM_INITPLR_ENABLE                                           | \
 
204
         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 
205
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 
206
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                        | \
 
207
         SDRAM_INITPLR_IMA_ENCODE(0))
 
208
#define CONFIG_SYS_SDRAM0_INITPLR4                                      \
 
209
        (SDRAM_INITPLR_ENABLE                                           | \
 
210
         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 
211
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 
212
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 
213
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE               | \
 
214
                                  JEDEC_MA_EMR_RTT_150OHM))
 
215
#define CONFIG_SYS_SDRAM0_INITPLR5                                      \
 
216
        (SDRAM_INITPLR_ENABLE                                           | \
 
217
         SDRAM_INITPLR_IMWT_ENCODE(200)                                 | \
 
218
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 
219
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 
220
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC             | \
 
221
                                  CAS_LATENCY                           | \
 
222
                                  JEDEC_MA_MR_BLEN_4                    | \
 
223
                                  JEDEC_MA_MR_DLL_RESET))
 
224
#define CONFIG_SYS_SDRAM0_INITPLR6                                      \
 
225
        (SDRAM_INITPLR_ENABLE                                           | \
 
226
         SDRAM_INITPLR_IMWT_ENCODE(3)                                   | \
 
227
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)                 | \
 
228
         SDRAM_INITPLR_IBA_ENCODE(0x0)                                  | \
 
229
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 
230
#define CONFIG_SYS_SDRAM0_INITPLR7                                      \
 
231
        (SDRAM_INITPLR_ENABLE                                           | \
 
232
         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 
233
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 
234
#define CONFIG_SYS_SDRAM0_INITPLR8                                      \
 
235
        (SDRAM_INITPLR_ENABLE                                           | \
 
236
         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 
237
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 
238
#define CONFIG_SYS_SDRAM0_INITPLR9                                      \
 
239
        (SDRAM_INITPLR_ENABLE                                           | \
 
240
         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 
241
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 
242
#define CONFIG_SYS_SDRAM0_INITPLR10                                     \
 
243
        (SDRAM_INITPLR_ENABLE                                           | \
 
244
         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 
245
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 
246
#define CONFIG_SYS_SDRAM0_INITPLR11                                     \
 
247
        (SDRAM_INITPLR_ENABLE                                           | \
 
248
         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 
249
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 
250
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 
251
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC             | \
 
252
                                  CAS_LATENCY                           | \
 
253
                                  JEDEC_MA_MR_BLEN_4))
 
254
#define CONFIG_SYS_SDRAM0_INITPLR12                                     \
 
255
        (SDRAM_INITPLR_ENABLE                                           | \
 
256
         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 
257
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 
258
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 
259
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER                | \
 
260
                                  JEDEC_MA_EMR_RDQS_DISABLE             | \
 
261
                                  JEDEC_MA_EMR_DQS_ENABLE               | \
 
262
                                  JEDEC_MA_EMR_RTT_150OHM               | \
 
263
                                  JEDEC_MA_EMR_ODS_NORMAL))
 
264
#define CONFIG_SYS_SDRAM0_INITPLR13                                     \
 
265
        (SDRAM_INITPLR_ENABLE                                           | \
 
266
         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 
267
         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 
268
         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 
269
         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT                 | \
 
270
                                  JEDEC_MA_EMR_RDQS_DISABLE             | \
 
271
                                  JEDEC_MA_EMR_DQS_ENABLE               | \
 
272
                                  JEDEC_MA_EMR_RTT_150OHM               | \
 
273
                                  JEDEC_MA_EMR_ODS_NORMAL))
 
274
#define CONFIG_SYS_SDRAM0_INITPLR14     SDRAM_INITPLR_DISABLE
 
275
#define CONFIG_SYS_SDRAM0_INITPLR15     SDRAM_INITPLR_DISABLE
 
276
#define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE         | \
 
277
                                         SDRAM_RQDC_RQFD_ENCODE(56))
 
278
#define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(599)
 
279
#define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 
280
#define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 
281
                                         SDRAM_DLCR_DLCS_CONT_DONE      | \
 
282
                                         SDRAM_DLCR_DLCV_ENCODE(155))
 
283
#define CONFIG_SYS_SDRAM0_CLKTR         SDRAM_CLKTR_CLKP_90_DEG_ADV
 
284
#define CONFIG_SYS_SDRAM0_WRDTR         SDRAM_WRDTR_WTR_90_DEG_ADV
 
285
#define CONFIG_SYS_SDRAM0_SDTR1         (SDRAM_SDTR1_LDOF_2_CLK         | \
 
286
                                         SDRAM_SDTR1_RTW_2_CLK          | \
 
287
                                         SDRAM_SDTR1_RTRO_1_CLK)
 
288
#define CONFIG_SYS_SDRAM0_SDTR2         (SDRAM_SDTR2_RCD_3_CLK          | \
 
289
                                         SDRAM_SDTR2_WTR_2_CLK          | \
 
290
                                         SDRAM_SDTR2_XSNR_32_CLK        | \
 
291
                                         SDRAM_SDTR2_WPC_4_CLK          | \
 
292
                                         SDRAM_SDTR2_RPC_2_CLK          | \
 
293
                                         SDRAM_SDTR2_RP_3_CLK           | \
 
294
                                         SDRAM_SDTR2_RRD_2_CLK)
 
295
#define CONFIG_SYS_SDRAM0_SDTR3         (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 
296
                                         SDRAM_SDTR3_RC_ENCODE(11)      | \
 
297
                                         SDRAM_SDTR3_XCS                | \
 
298
                                         SDRAM_SDTR3_RFC_ENCODE(26))
 
299
#define CONFIG_SYS_SDRAM0_MMODE         (SDRAM_MMODE_WR_DDR2_3_CYC      | \
 
300
                                         CAS_LATENCY                    | \
 
301
                                         SDRAM_MMODE_BLEN_4)
 
302
#define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_ENABLE        | \
 
303
                                         SDRAM_MEMODE_RTT_150OHM)
 
304
 
 
305
/*
 
306
 * I2C
 
307
 */
 
308
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0                   400000
 
309
 
 
310
#define CONFIG_SYS_I2C_MULTI_EEPROMS
 
311
#define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 
312
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 
313
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 
314
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 
315
 
 
316
/* I2C bootstrap EEPROM */
 
317
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 
318
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 
319
#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 
320
 
 
321
/*
 
322
 * Ethernet
 
323
 */
 
324
#define CONFIG_IBM_EMAC4_V4     1
 
325
 
 
326
#define CONFIG_HAS_ETH0
 
327
 
 
328
#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 
329
#define CONFIG_M88E1111_PHY
 
330
/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
 
331
#define CONFIG_M88E1111_DISABLE_FIBER
 
332
 
 
333
#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 
334
#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 
335
#define CONFIG_PHY_DYNAMIC_ANEG 1
 
336
 
 
337
/*
 
338
 * Default environment variables
 
339
 */
 
340
#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 
341
        CONFIG_AMCC_DEF_ENV                                             \
 
342
        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 
343
        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 
344
        "kernel_addr=fc000000\0"                                        \
 
345
        "fdt_addr=fc1e0000\0"                                           \
 
346
        "ramdisk_addr=fc200000\0"                                       \
 
347
        "pciconfighost=1\0"                                             \
 
348
        "pcie_mode=RP:RP\0"                                             \
 
349
        "unlock=yes\0"                                                  \
 
350
        ""
 
351
 
 
352
/*
 
353
 * Commands additional to the ones defined in amcc-common.h
 
354
 */
 
355
#define CONFIG_CMD_CHIP_CONFIG
 
356
#define CONFIG_CMD_ECCTEST
 
357
#define CONFIG_CMD_PCI
 
358
#define CONFIG_CMD_SDRAM
 
359
 
 
360
/*
 
361
 * PCI stuff
 
362
 */
 
363
/* General PCI */
 
364
#define CONFIG_PCI                      /* include pci support          */
 
365
#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 
366
#define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 
367
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 
368
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
369
 
 
370
/* Board-specific PCI, no PCI support, only PCIe */
 
371
#undef CONFIG_SYS_PCI_TARGET_INIT
 
372
#undef CONFIG_SYS_PCI_MASTER_INIT
 
373
 
 
374
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM */
 
375
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 
376
 
 
377
 
 
378
/*
 
379
 * External Bus Controller (EBC) Setup
 
380
 */
 
381
 
 
382
/*
 
383
 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
 
384
 * boot EBC mapping only supports a maximum of 16MBytes
 
385
 * (4.ff00.0000 - 4.ffff.ffff).
 
386
 * To solve this problem, the flash has to get remapped to another
 
387
 * EBC address which accepts bigger regions:
 
388
 *
 
389
 * 0xfc00.0000 -> 4.cc00.0000
 
390
 */
 
391
 
 
392
/* Memory Bank 0 (NOR-flash) */
 
393
#define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_DISABLED          |       \
 
394
                                 EBC_BXAP_TWT_ENCODE(16)        |       \
 
395
                                 EBC_BXAP_BCE_DISABLE           |       \
 
396
                                 EBC_BXAP_BCT_2TRANS            |       \
 
397
                                 EBC_BXAP_CSN_ENCODE(1)         |       \
 
398
                                 EBC_BXAP_OEN_ENCODE(1)         |       \
 
399
                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 
400
                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 
401
                                 EBC_BXAP_TH_ENCODE(7)          |       \
 
402
                                 EBC_BXAP_RE_DISABLED           |       \
 
403
                                 EBC_BXAP_SOR_DELAYED           |       \
 
404
                                 EBC_BXAP_BEM_WRITEONLY         |       \
 
405
                                 EBC_BXAP_PEN_DISABLED)
 
406
#define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
 
407
                                 EBC_BXCR_BS_16MB               |       \
 
408
                                 EBC_BXCR_BU_RW                 |       \
 
409
                                 EBC_BXCR_BW_16BIT)
 
410
 
 
411
/* Memory Bank 1 (FPGA 1) */
 
412
#define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED          |       \
 
413
                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 
414
                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 
415
                                 EBC_BXAP_OEN_ENCODE(3)         |       \
 
416
                                 EBC_BXAP_WBN_ENCODE(0)         |       \
 
417
                                 EBC_BXAP_WBF_ENCODE(0)         |       \
 
418
                                 EBC_BXAP_TH_ENCODE(1)          |       \
 
419
                                 EBC_BXAP_RE_ENABLED            |       \
 
420
                                 EBC_BXAP_SOR_DELAYED           |       \
 
421
                                 EBC_BXAP_BEM_RW                |       \
 
422
                                 EBC_BXAP_PEN_DISABLED)
 
423
#define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
 
424
                                 EBC_BXCR_BS_32MB               |       \
 
425
                                 EBC_BXCR_BU_RW                 |       \
 
426
                                 EBC_BXCR_BW_32BIT)
 
427
 
 
428
/* Memory Bank 2 (FPGA 2) */
 
429
#define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 
430
                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 
431
                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 
432
                                 EBC_BXAP_OEN_ENCODE(3)         |       \
 
433
                                 EBC_BXAP_WBN_ENCODE(0)         |       \
 
434
                                 EBC_BXAP_WBF_ENCODE(0)         |       \
 
435
                                 EBC_BXAP_TH_ENCODE(1)          |       \
 
436
                                 EBC_BXAP_RE_ENABLED            |       \
 
437
                                 EBC_BXAP_SOR_DELAYED           |       \
 
438
                                 EBC_BXAP_BEM_RW                |       \
 
439
                                 EBC_BXAP_PEN_DISABLED)
 
440
#define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
 
441
                                 EBC_BXCR_BS_16MB               |       \
 
442
                                 EBC_BXCR_BU_RW                 |       \
 
443
                                 EBC_BXCR_BW_32BIT)
 
444
 
 
445
/* Memory Bank 3 (FPGA 3) */
 
446
#define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_DISABLED          |       \
 
447
                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 
448
                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 
449
                                 EBC_BXAP_OEN_ENCODE(3)         |       \
 
450
                                 EBC_BXAP_WBN_ENCODE(0)         |       \
 
451
                                 EBC_BXAP_WBF_ENCODE(0)         |       \
 
452
                                 EBC_BXAP_TH_ENCODE(1)          |       \
 
453
                                 EBC_BXAP_RE_ENABLED            |       \
 
454
                                 EBC_BXAP_SOR_DELAYED           |       \
 
455
                                 EBC_BXAP_BEM_RW                |       \
 
456
                                 EBC_BXAP_PEN_DISABLED)
 
457
#define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
 
458
                                 EBC_BXCR_BS_16MB               |       \
 
459
                                 EBC_BXCR_BU_RW                 |       \
 
460
                                 EBC_BXCR_BW_32BIT)
 
461
 
 
462
/*
 
463
 * PPC4xx GPIO Configuration
 
464
 */
 
465
 
 
466
#define CONFIG_SYS_4xx_GPIO_TABLE { /*            GPIO  Alternate1      Alternate2      Alternate3 */ \
 
467
{                                                                                       \
 
468
/* GPIO Core 0 */                                                                       \
 
469
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 
470
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 
471
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 
472
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 
473
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 
474
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 
475
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 
476
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 
477
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 
478
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 
479
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 
480
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 
481
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 
482
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 
483
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 
484
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 
485
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 
486
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 
487
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 
488
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 
489
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 
490
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 
491
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 
492
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 
493
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 
494
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 
495
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 
496
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 
497
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 
498
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 
499
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 
500
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 
501
},                                                                                      \
 
502
{                                                                                       \
 
503
/* GPIO Core 1 */                                                                       \
 
504
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 
505
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 
506
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 
507
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 
508
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 
509
{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 
510
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 
511
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 
512
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 
513
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 
514
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 
515
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 
516
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 
517
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 
518
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 
519
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 
520
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 
521
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 
522
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 
523
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 
524
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 
525
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 
526
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 
527
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 
528
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 
529
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 
530
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 
531
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 
532
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 
533
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 
534
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 
535
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 
536
}                                                                                       \
 
537
}
 
538
 
 
539
#endif  /* __CONFIG_H */