~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.

eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.

/* Offset for Memory Mapped Registers. */

/* 32 bit registers */

#define ASF_STAT 0x00 /* ASF status register */

#define CHIPID 0x04 /* Chip ID regsiter */

#define MIB_DATA 0x10 /* MIB data register */

#define MIB_ADDR 0x14 /* MIB address register */

#define STAT0 0x30 /* Status0 register */

#define INT0 0x38 /* Interrupt0 register */

#define INTEN0 0x40 /* Interrupt0 enable register*/

#define CMD0 0x48 /* Command0 register */

#define CMD2 0x50 /* Command2 register */

#define CMD3 0x54 /* Command3 resiter */

#define CMD7 0x64 /* Command7 register */

#define CTRL1 0x6C /* Control1 register */

#define CTRL2 0x70 /* Control2 register */

#define XMT_RING_LIMIT 0x7C /* Transmit ring limit register */

#define AUTOPOLL0 0x88 /* Auto-poll0 register */

#define AUTOPOLL1 0x8A /* Auto-poll1 register */

#define AUTOPOLL2 0x8C /* Auto-poll2 register */

#define AUTOPOLL3 0x8E /* Auto-poll3 register */

#define AUTOPOLL4 0x90 /* Auto-poll4 register */

#define AUTOPOLL5 0x92 /* Auto-poll5 register */

#define AP_VALUE 0x98 /* Auto-poll value register */

#define DLY_INT_A 0xA8 /* Group A delayed interrupt register */

#define DLY_INT_B 0xAC /* Group B delayed interrupt register */

#define FLOW_CONTROL 0xC8 /* Flow control register */

#define PHY_ACCESS 0xD0 /* PHY access register */

#define STVAL 0xD8 /* Software timer value register */

#define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */

#define XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */

#define XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */

#define XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */

#define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */

#define PMAT0 0x190 /* OnNow pattern register0 */

100

#define PMAT1 0x194 /* OnNow pattern register1 */

101

102

/* 16bit registers */

103

104

#define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */

105

#define XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */

106

#define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */

107

#define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */

108

109

#define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */

110

111

#define SRAM_SIZE 0x178 /* SRAM size register */

112

#define SRAM_BOUNDARY 0x17A /* SRAM boundary register */

113

114

/* 48bit register */

115

116

#define PADR 0x160 /* Physical address register */

117

118

#define IFS1 0x18C /* Inter-frame spacing Part1 register */

119

#define IFS 0x18D /* Inter-frame spacing register */

120

#define IPG 0x18E /* Inter-frame gap register */

121

/* 64bit register */

122

123

#define LADRF 0x168 /* Logical address filter register */

124

125

126

/* Register Bit Definitions */

127

typedef enum {

128

129

ASF_INIT_DONE = (1 << 1),

130

ASF_INIT_PRESENT = (1 << 0),

131

132

}STAT_ASF_BITS;

133

134

typedef enum {

135

136

MIB_CMD_ACTIVE = (1 << 15 ),

137

MIB_RD_CMD = (1 << 13 ),

138

MIB_CLEAR = (1 << 12 ),

139

MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|

140

(1 << 4) | (1 << 5),

141

}MIB_ADDR_BITS;

142

143

144

typedef enum {

145

146

PMAT_DET = (1 << 12),

147

MP_DET = (1 << 11),

148

LC_DET = (1 << 10),

149

SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),

150

FULL_DPLX = (1 << 6),

151

LINK_STATS = (1 << 5),

152

AUTONEG_COMPLETE = (1 << 4),

153

MIIPD = (1 << 3),

154

RX_SUSPENDED = (1 << 2),

155

TX_SUSPENDED = (1 << 1),

156

RUNNING = (1 << 0),

157

158

}STAT0_BITS;

159

160

#define PHY_SPEED_10 0x2

161

#define PHY_SPEED_100 0x3

162

163

/* INT0 0x38, 32bit register */

164

typedef enum {

165

166

INTR = (1 << 31),

167

PCSINT = (1 << 28),

168

LCINT = (1 << 27),

169

APINT5 = (1 << 26),

170

APINT4 = (1 << 25),

171

APINT3 = (1 << 24),

172

TINT_SUM = (1 << 23),

173

APINT2 = (1 << 22),

174

APINT1 = (1 << 21),

175

APINT0 = (1 << 20),

176

MIIPDTINT = (1 << 19),

177

MCCINT = (1 << 17),

178

MREINT = (1 << 16),

179

RINT_SUM = (1 << 15),

180

SPNDINT = (1 << 14),

181

MPINT = (1 << 13),

182

SINT = (1 << 12),

183

TINT3 = (1 << 11),

184

TINT2 = (1 << 10),

185

TINT1 = (1 << 9),

186

TINT0 = (1 << 8),

187

UINT = (1 << 7),

188

STINT = (1 << 4),

189

RINT0 = (1 << 0),

190

191

}INT0_BITS;

192

193

typedef enum {

194

195

VAL3 = (1 << 31), /* VAL bit for byte 3 */

196

VAL2 = (1 << 23), /* VAL bit for byte 2 */

197

VAL1 = (1 << 15), /* VAL bit for byte 1 */

198

VAL0 = (1 << 7), /* VAL bit for byte 0 */

199

200

}VAL_BITS;

201

202

typedef enum {

203

204

/* VAL3 */

205

LCINTEN = (1 << 27),

206

APINT5EN = (1 << 26),

207

APINT4EN = (1 << 25),

208

APINT3EN = (1 << 24),

209

/* VAL2 */

210

APINT2EN = (1 << 22),

211

APINT1EN = (1 << 21),

212

APINT0EN = (1 << 20),

213

MIIPDTINTEN = (1 << 19),

214

MCCIINTEN = (1 << 18),

215

MCCINTEN = (1 << 17),

216

MREINTEN = (1 << 16),

217

/* VAL1 */

218

SPNDINTEN = (1 << 14),

219

MPINTEN = (1 << 13),

220

TINTEN3 = (1 << 11),

221

SINTEN = (1 << 12),

222

TINTEN2 = (1 << 10),

223

TINTEN1 = (1 << 9),

224

TINTEN0 = (1 << 8),

225

/* VAL0 */

226

STINTEN = (1 << 4),

227

RINTEN0 = (1 << 0),

228

229

INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */

230

231

}INTEN0_BITS;

232

233

typedef enum {

234

/* VAL2 */

235

RDMD0 = (1 << 16),

236

/* VAL1 */

237

TDMD3 = (1 << 11),

238

TDMD2 = (1 << 10),

239

TDMD1 = (1 << 9),

240

TDMD0 = (1 << 8),

241

/* VAL0 */

242

UINTCMD = (1 << 6),

243

RX_FAST_SPND = (1 << 5),

244

TX_FAST_SPND = (1 << 4),

245

RX_SPND = (1 << 3),

246

TX_SPND = (1 << 2),

247

INTREN = (1 << 1),

248

RUN = (1 << 0),

249

250

CMD0_CLEAR = 0x000F0F7F, /* Command style register */

251

252

}CMD0_BITS;

253

254

typedef enum {

255

256

/* VAL3 */

257

CONDUIT_MODE = (1 << 29),

258

/* VAL2 */

259

RPA = (1 << 19),

260

DRCVPA = (1 << 18),

261

DRCVBC = (1 << 17),

262

PROM = (1 << 16),

263

/* VAL1 */

264

ASTRP_RCV = (1 << 13),

265

RCV_DROP0 = (1 << 12),

266

EMBA = (1 << 11),

267

DXMT2PD = (1 << 10),

268

LTINTEN = (1 << 9),

269

DXMTFCS = (1 << 8),

270

/* VAL0 */

271

APAD_XMT = (1 << 6),

272

DRTY = (1 << 5),

273

INLOOP = (1 << 4),

274

EXLOOP = (1 << 3),

275

REX_RTRY = (1 << 2),

276

REX_UFLO = (1 << 1),

277

REX_LCOL = (1 << 0),

278

279

CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */

280

281

}CMD2_BITS;

282

283

typedef enum {

284

285

/* VAL3 */

286

ASF_INIT_DONE_ALIAS = (1 << 29),

287

/* VAL2 */

288

JUMBO = (1 << 21),

289

VSIZE = (1 << 20),

290

VLONLY = (1 << 19),

291

VL_TAG_DEL = (1 << 18),

292

/* VAL1 */

293

EN_PMGR = (1 << 14),

294

INTLEVEL = (1 << 13),

295

FORCE_FULL_DUPLEX = (1 << 12),

296

FORCE_LINK_STATUS = (1 << 11),

297

APEP = (1 << 10),

298

MPPLBA = (1 << 9),

299

/* VAL0 */

300

RESET_PHY_PULSE = (1 << 2),

301

RESET_PHY = (1 << 1),

302

PHY_RST_POL = (1 << 0),

303

304

}CMD3_BITS;

305

306

307

typedef enum {

308

309

/* VAL0 */

310

PMAT_SAVE_MATCH = (1 << 4),

311

PMAT_MODE = (1 << 3),

312

MPEN_SW = (1 << 1),

313

LCMODE_SW = (1 << 0),

314

315

CMD7_CLEAR = 0x0000001B /* Command style register */

316

317

}CMD7_BITS;

318

319

320

typedef enum {

321

322

RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */

323

XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */

324

XMTSP_128 = (1 << 9), /* 9 */

325

XMTSP_64 = (1 << 8),

326

CACHE_ALIGN = (1 << 4),

327

BURST_LIMIT_MASK = (0xF << 0 ),

328

CTRL1_DEFAULT = 0x00010111,

329

330

}CTRL1_BITS;

331

332

typedef enum {

333

334

FMDC_MASK = (1 << 9)|(1 << 8), /* 9:8 */

335

XPHYRST = (1 << 7),

336

XPHYANE = (1 << 6),

337

XPHYFD = (1 << 5),

338

XPHYSP = (1 << 4) | (1 << 3), /* 4:3 */

339

APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */

340

341

}CTRL2_BITS;

342

343

/* XMT_RING_LIMIT 0x7C, 32bit register */

344

typedef enum {

345

346

XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */

347

XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */

348

XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */

349

350

}XMT_RING_LIMIT_BITS;

351

352

typedef enum {

353

354

AP_REG0_EN = (1 << 15),

355

AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */

356

AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */

357

358

}AUTOPOLL0_BITS;

359

360

/* AUTOPOLL1 0x8A, 16bit register */

361

typedef enum {

362

363

AP_REG1_EN = (1 << 15),

364

AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */

365

AP_PRE_SUP1 = (1 << 6),

366

AP_PHY1_DFLT = (1 << 5),

367

AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */

368

369

}AUTOPOLL1_BITS;

370

371

372

typedef enum {

373

374

AP_REG2_EN = (1 << 15),

375

AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */

376

AP_PRE_SUP2 = (1 << 6),

377

AP_PHY2_DFLT = (1 << 5),

378

AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */

379

380

}AUTOPOLL2_BITS;

381

382

typedef enum {

383

384

AP_REG3_EN = (1 << 15),

385

AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */

386

AP_PRE_SUP3 = (1 << 6),

387

AP_PHY3_DFLT = (1 << 5),

388

AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */

389

390

}AUTOPOLL3_BITS;

391

392

393

typedef enum {

394

395

AP_REG4_EN = (1 << 15),

396

AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */

397

AP_PRE_SUP4 = (1 << 6),

398

AP_PHY4_DFLT = (1 << 5),

399

AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */

400

401

}AUTOPOLL4_BITS;

402

403

404

typedef enum {

405

406

AP_REG5_EN = (1 << 15),

407

AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */

408

AP_PRE_SUP5 = (1 << 6),

409

AP_PHY5_DFLT = (1 << 5),

410

AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */

411

412

}AUTOPOLL5_BITS;

413

414

415

416

417

/* AP_VALUE 0x98, 32bit ragister */

418

typedef enum {

419

420

AP_VAL_ACTIVE = (1 << 31),

421

AP_VAL_RD_CMD = ( 1 << 29),

422

AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */

423

AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |

424

(0xF << 12), /* 15:0 */

425

426

}AP_VALUE_BITS;

427

428

typedef enum {

429

430

DLY_INT_A_R3 = (1 << 31),

431

DLY_INT_A_R2 = (1 << 30),

432

DLY_INT_A_R1 = (1 << 29),

433

DLY_INT_A_R0 = (1 << 28),

434

DLY_INT_A_T3 = (1 << 27),

435

DLY_INT_A_T2 = (1 << 26),

436

DLY_INT_A_T1 = (1 << 25),

437

DLY_INT_A_T0 = ( 1 << 24),

438

EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */

439

MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)|

440

(1 << 9) | (1 << 10), /* 10:0 */

441

442

}DLY_INT_A_BITS;

443

444

typedef enum {

445

446

DLY_INT_B_R3 = (1 << 31),

447

DLY_INT_B_R2 = (1 << 30),

448

DLY_INT_B_R1 = (1 << 29),

449

DLY_INT_B_R0 = (1 << 28),

450

DLY_INT_B_T3 = (1 << 27),

451

DLY_INT_B_T2 = (1 << 26),

452

DLY_INT_B_T1 = (1 << 25),

453

DLY_INT_B_T0 = ( 1 << 24),

454

EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */

455

MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|

456

(1 << 9) | (1 << 10), /* 10:0 */

457

}DLY_INT_B_BITS;

458

459

460

/* FLOW_CONTROL 0xC8, 32bit register */

461

typedef enum {

462

463

PAUSE_LEN_CHG = (1 << 30),

464

FTPE = (1 << 22),

465

FRPE = (1 << 21),

466

NAPA = (1 << 20),

467

NPA = (1 << 19),

468

FIXP = ( 1 << 18),

469

FCCMD = ( 1 << 16),

470

PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */

471

472

}FLOW_CONTROL_BITS;

473

474

/* PHY_ ACCESS 0xD0, 32bit register */

475

typedef enum {

476

477

PHY_CMD_ACTIVE = (1 << 31),

478

PHY_WR_CMD = (1 << 30),

479

PHY_RD_CMD = (1 << 29),

480

PHY_RD_ERR = (1 << 28),

481

PHY_PRE_SUP = (1 << 27),

482

PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)|

483

(1 << 24) |(1 << 25),/* 25:21 */

484

PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),/* 20:16 */

485

PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)|

486

(0xF << 12),/* 15:0 */

487

488

}PHY_ACCESS_BITS;

489

490

491

/* PMAT0 0x190, 32bit register */

492

typedef enum {

493

PMR_ACTIVE = (1 << 31),

494

PMR_WR_CMD = (1 << 30),

495

PMR_RD_CMD = (1 << 29),

496

PMR_BANK = (1 <<28),

497

PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)|

498

(1 << 22),/* 22:16 */

499

PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */

500

}PMAT0_BITS;

501

502

503

/* PMAT1 0x194, 32bit register */

504

typedef enum {

505

PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */

506

PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */

507

PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */

508

PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */

509

}PMAT1_BITS;

510

511

/************************************************************************/

512

/* */

513

/* MIB counter definitions */

514

/* */

515

/************************************************************************/

516

517

#define rcv_miss_pkts 0x00

518

#define rcv_octets 0x01

519

#define rcv_broadcast_pkts 0x02

520

#define rcv_multicast_pkts 0x03

521

#define rcv_undersize_pkts 0x04

522

#define rcv_oversize_pkts 0x05

523

#define rcv_fragments 0x06

524

#define rcv_jabbers 0x07

525

#define rcv_unicast_pkts 0x08

526

#define rcv_alignment_errors 0x09

527

#define rcv_fcs_errors 0x0A

528

#define rcv_good_octets 0x0B

529

#define rcv_mac_ctrl 0x0C

530

#define rcv_flow_ctrl 0x0D

531

#define rcv_pkts_64_octets 0x0E

532

#define rcv_pkts_65to127_octets 0x0F

533

#define rcv_pkts_128to255_octets 0x10

534

#define rcv_pkts_256to511_octets 0x11

535

#define rcv_pkts_512to1023_octets 0x12

536

#define rcv_pkts_1024to1518_octets 0x13

537

#define rcv_unsupported_opcode 0x14

538

#define rcv_symbol_errors 0x15

539

#define rcv_drop_pkts_ring1 0x16

540

#define rcv_drop_pkts_ring2 0x17

541

#define rcv_drop_pkts_ring3 0x18

542

#define rcv_drop_pkts_ring4 0x19

543

#define rcv_jumbo_pkts 0x1A

544

545

#define xmt_underrun_pkts 0x20

546

#define xmt_octets 0x21

547

#define xmt_packets 0x22

548

#define xmt_broadcast_pkts 0x23

549

#define xmt_multicast_pkts 0x24

550

#define xmt_collisions 0x25

551

#define xmt_unicast_pkts 0x26

552

#define xmt_one_collision 0x27

553

#define xmt_multiple_collision 0x28

554

#define xmt_deferred_transmit 0x29

555

#define xmt_late_collision 0x2A

556

#define xmt_excessive_defer 0x2B

557

#define xmt_loss_carrier 0x2C

558

#define xmt_excessive_collision 0x2D

559

#define xmt_back_pressure 0x2E

560

#define xmt_flow_ctrl 0x2F

561

#define xmt_pkts_64_octets 0x30

562

#define xmt_pkts_65to127_octets 0x31

563

#define xmt_pkts_128to255_octets 0x32

564

#define xmt_pkts_256to511_octets 0x33

565

#define xmt_pkts_512to1023_octets 0x34

566

#define xmt_pkts_1024to1518_octet 0x35

567

#define xmt_oversize_pkts 0x36

568

#define xmt_jumbo_pkts 0x37

569

570

/* ipg parameters */

571

#define DEFAULT_IPG 0x60

572

#define IFS1_DELTA 36

573

#define IPG_CONVERGE_JIFFIES (HZ/2)

574

#define IPG_STABLE_TIME 5

575

#define MIN_IPG 96

576

#define MAX_IPG 255

577

#define IPG_STEP 16

578

#define CSTATE 1

579

#define SSTATE 2

580

581

/* amd8111e descriptor flag definitions */

582

typedef enum {

583

584

OWN_BIT = (1 << 15),

585

ADD_FCS_BIT = (1 << 13),

586

LTINT_BIT = (1 << 12),

587

STP_BIT = (1 << 9),

588

ENP_BIT = (1 << 8),

589

KILL_BIT = (1 << 6),

590

TCC_VLAN_INSERT = (1 << 1),

591

TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0),

592

593

}TX_FLAG_BITS;

594

595

typedef enum {

596

ERR_BIT = (1 << 14),

597

FRAM_BIT = (1 << 13),

598

OFLO_BIT = (1 << 12),

599

CRC_BIT = (1 << 11),

600

PAM_BIT = (1 << 6),

601

LAFM_BIT = (1 << 5),

602

BAM_BIT = (1 << 4),

603

TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */

604

TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */

605

606

}RX_FLAG_BITS;

607

608

#define RESET_RX_FLAGS 0x0000

609

#define TT_MASK 0x000c

610

#define TCC_MASK 0x0003

611

612

/* driver ioctl parameters */

613

#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)

614

615

/* crc generator constants */

616

#define CRC32 0xedb88320

617

#define INITCRC 0xFFFFFFFF

618

619

/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.

620

BUG? */

621

#define amd8111e_writeq(_UlData,_memMap) \

622

writel(*(u32*)(&_UlData), _memMap); \

623

writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)

624

625

/* maps the external speed options to internal value */

626

typedef enum {

627

SPEED_AUTONEG,

628

SPEED10_HALF,

629

SPEED10_FULL,

630

SPEED100_HALF,

631

SPEED100_FULL,

632

}EXT_PHY_OPTION;

633

634

635

#endif /* _AMD8111E_H */

636

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