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Viewing changes to roms/u-boot/board/freescale/mpc8548cds/tlb.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/freescale/mpc8548cds/tlb.c
 
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/*
 
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 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
 
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 *
 
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 * (C) Copyright 2000
 
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 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/mmu.h>
 
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struct fsl_e_tlb_entry tlb_table[] = {
 
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        /* TLB 0 - for temp stack in cache */
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        /* TLB 1 */
 
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        /*
 
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         * Entry 0:
 
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         * FLASH(cover boot page)       16M     Non-cacheable, guarded
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 0, BOOKE_PAGESZ_16M, 1),
 
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        /*
 
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         * Entry 1:
 
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         * CCSRBAR      1M      Non-cacheable, guarded
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 1, BOOKE_PAGESZ_1M, 1),
 
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        /*
 
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         * Entry 2:
 
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         * LBC SDRAM    64M     Cacheable, non-guarded
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
 
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                      CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 2, BOOKE_PAGESZ_64M, 1),
 
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        /*
 
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         * Entry 3:
 
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         * CADMUS registers     1M      Non-cacheable, guarded
 
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         */
 
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        SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 3, BOOKE_PAGESZ_1M, 1),
 
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        /*
 
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         * Entry 4:
 
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         * PCI and PCIe MEM     1G      Non-cacheable, guarded
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 4, BOOKE_PAGESZ_1G, 1),
 
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        /*
 
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         * Entry 5:
 
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         * PCI1 IO      1M      Non-cacheable, guarded
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
 
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                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 5, BOOKE_PAGESZ_1M, 1),
 
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        /*
 
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         * Entry 6:
 
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         * PCIe IO      1M      Non-cacheable, guarded
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
 
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                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 6, BOOKE_PAGESZ_1M, 1),
 
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};
 
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int num_tlb_entries = ARRAY_SIZE(tlb_table);