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* Texas Instruments, <www.ti.com>
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* Tom Rini <trini@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Jian Zhang <jzhang@ti.com>
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* SPDX-License-Identifier: GPL-2.0+
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#include <linux/mtd/nand.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
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/* nand_command: Send a flash command to the flash chip */
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static void nand_command(u8 command)
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writeb(command, &gpmc_config->cs[0].nand_cmd);
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if (command == NAND_CMD_RESET) {
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unsigned char ret_val;
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writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
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/* Wait until ready */
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ret_val = readl(&gpmc_config->cs[0].nand_dat);
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} while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
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* Many boards will want to know the results of the NAND_CMD_READID command
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* in order to decide what to do about DDR initialization. This function
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* allows us to do that very early and to pass those results back to the
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* board so it can make whatever decisions need to be made.
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void identify_nand_chip(int *mfr, int *id)
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/* Make sure that we have setup GPMC for NAND correctly. */
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writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
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writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
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writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
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writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
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writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
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writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
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* Enable the config. The CS size goes in bits 11:8. We set
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* bit 6 to enable the CS and the base address goes into bits 5:0.
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writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
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((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
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&gpmc_config->cs[0].config7);
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/* Issue a RESET and then READID */
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nand_command(NAND_CMD_RESET);
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nand_command(NAND_CMD_READID);
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/* Set the address to read to 0x0 */
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writeb(0x0, &gpmc_config->cs[0].nand_adr);
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/* Read off the manufacturer and device id. */
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*mfr = readb(&gpmc_config->cs[0].nand_dat);
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*id = readb(&gpmc_config->cs[0].nand_dat);