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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
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* SPDX-License-Identifier: GPL-2.0+
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* U-Boot - Startup Code for MPC5xxx CPUs
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#include <asm-offsets.h>
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#include <ppc_asm.tmpl>
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#include <asm/cache.h>
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#include <asm/u-boot.h>
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/* We don't want the MMU yet.
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/* Floating Point enable, Machine Check and Recoverable Interr. */
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#define MSR_KERNEL (MSR_FP|MSR_RI)
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#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
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#ifndef CONFIG_SPL_BUILD
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* Set up GOT: Global Offset Table
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* Use r12 to access the GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__bss_start)
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.ascii U_BOOT_VERSION_STRING, "\0"
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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* This is the entry of the real U-Boot from a board port
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* that supports SPL booting on the MPC5200. We only need
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* to call board_init_f() here. Everything else has already
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* been done in the SPL u-boot version.
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GET_GOT /* initialize GOT access */
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bl board_init_f /* run 1st part of board init code (in Flash)*/
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/* NOTREACHED - board_init_f() does not return */
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mfmsr r5 /* save msr contents */
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/* Move CSBoot and adjust instruction pointer */
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/*--------------------------------------------------------------*/
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#if defined(CONFIG_SYS_LOWBOOT)
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# if defined(CONFIG_SYS_RAMBOOT)
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# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
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# endif /* CONFIG_SYS_RAMBOOT */
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lis r4, CONFIG_SYS_DEFAULT_MBAR@h
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lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
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ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
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stw r3, 0x4(r4) /* CS0 start */
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lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
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ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
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stw r3, 0x8(r4) /* CS0 stop */
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ori r3, r3, 0x02010000@l
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stw r3, 0x54(r4) /* CS0 and Boot enable */
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lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */
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ori r3, r3, lowboot_reentry@l /* to the address space the linker used */
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lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
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ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
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stw r3, 0x4c(r4) /* Boot start */
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lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
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ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
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stw r3, 0x50(r4) /* Boot stop */
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ori r3, r3, 0x02000001@l
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stw r3, 0x54(r4) /* Boot enable, CS0 disable */
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#endif /* CONFIG_SYS_LOWBOOT */
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#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
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lis r3, CONFIG_SYS_MBAR@h
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ori r3, r3, CONFIG_SYS_MBAR@l
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/* MBAR is mirrored into the MBAR SPR */
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rlwinm r3, r3, 16, 16, 31
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lis r4, CONFIG_SYS_DEFAULT_MBAR@h
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#endif /* CONFIG_SYS_DEFAULT_MBAR */
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/* Initialise the MPC5xxx processor core */
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/*--------------------------------------------------------------*/
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/* initialize some things that are hard to access from C */
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/*--------------------------------------------------------------*/
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/* set up stack in on-chip SRAM */
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lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
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ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
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ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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/* let the C-code set up the rest */
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/* Be careful to keep code relocatable ! */
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/*--------------------------------------------------------------*/
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#ifndef CONFIG_SPL_BUILD
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GET_GOT /* initialize GOT access */
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bl cpu_init_f /* run low-level CPU init code (in Flash)*/
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bl board_init_f /* run 1st part of board init code (in Flash)*/
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/* NOTREACHED - board_init_f() does not return */
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#ifndef CONFIG_SPL_BUILD
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.globl _start_of_vectors
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STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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/* Data Storage exception. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
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/* Program check exception */
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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/* I guess we could implement decrementer, and may have
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* to someday for timekeeping.
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STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
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STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
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STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
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STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
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STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
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STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
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STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
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* This exception occurs when the program counter matches the
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* Instruction Address Breakpoint Register (IABR).
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* I want the cpu to halt if this occurs so I can hunt around
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* with the debugger and look at things.
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* When DEBUG is defined, both machine check enable (in the MSR)
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* and checkstop reset enable (in the reset mode register) are
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* turned off and so a checkstop condition will result in the cpu
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* I force the cpu into a checkstop condition by putting an illegal
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* instruction here (at least this is the theory).
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* well - that didnt work, so just do an infinite loop!
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STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
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STD_EXCEPTION(0x1400, SMI, UnknownException)
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STD_EXCEPTION(0x1500, Trap_15, UnknownException)
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STD_EXCEPTION(0x1600, Trap_16, UnknownException)
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STD_EXCEPTION(0x1700, Trap_17, UnknownException)
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STD_EXCEPTION(0x1800, Trap_18, UnknownException)
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STD_EXCEPTION(0x1900, Trap_19, UnknownException)
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STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
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STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
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STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
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STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
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STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
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STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
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STD_EXCEPTION(0x2000, Trap_20, UnknownException)
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STD_EXCEPTION(0x2100, Trap_21, UnknownException)
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STD_EXCEPTION(0x2200, Trap_22, UnknownException)
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STD_EXCEPTION(0x2300, Trap_23, UnknownException)
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STD_EXCEPTION(0x2400, Trap_24, UnknownException)
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STD_EXCEPTION(0x2500, Trap_25, UnknownException)
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STD_EXCEPTION(0x2600, Trap_26, UnknownException)
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STD_EXCEPTION(0x2700, Trap_27, UnknownException)
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STD_EXCEPTION(0x2800, Trap_28, UnknownException)
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STD_EXCEPTION(0x2900, Trap_29, UnknownException)
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STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
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STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
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STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
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STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
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STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
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STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
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.globl _end_of_vectors
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* This code finishes saving the registers to the exception frame
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* and jumps to the appropriate handler for the exception.
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* Register r21 is pointer into trap frame, r1 has new stack pointer.
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.globl transfer_to_handler
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andi. r24,r23,0x3f00 /* get vector offset */
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lwz r24,0(r23) /* virtual address of handler */
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lwz r23,4(r23) /* where to go when done */
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rfi /* jump to handler, enable MMU */
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mfmsr r28 /* Disable interrupts */
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SYNC /* Some chip revs need this... */
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lwz r2,_NIP(r1) /* Restore environment */
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#endif /* CONFIG_SPL_BUILD */
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* This code initialises the MPC5xxx processor core
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* (conforms to PowerPC 603e spec)
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* Note: expects original MSR contents to be in r5.
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/* Initialize machine status; enable machine check interrupt */
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/*--------------------------------------------------------------*/
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li r3, MSR_KERNEL /* Set ME and RI flags */
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rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
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rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
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SYNC /* Some chip revs need this... */
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mtspr SRR1, r3 /* Make SRR1 match MSR */
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/* Initialize the Hardware Implementation-dependent Registers */
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/* HID0 also contains cache control */
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/*--------------------------------------------------------------*/
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lis r3, CONFIG_SYS_HID0_INIT@h
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ori r3, r3, CONFIG_SYS_HID0_INIT@l
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lis r3, CONFIG_SYS_HID0_FINAL@h
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ori r3, r3, CONFIG_SYS_HID0_FINAL@l
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/* clear all BAT's */
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/*--------------------------------------------------------------*/
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/* invalidate all tlb's */
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/* From the 603e User Manual: "The 603e provides the ability to */
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/* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
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/* instruction invalidates the TLB entry indexed by the EA, and */
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/* operates on both the instruction and data TLBs simultaneously*/
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/* invalidating four TLB entries (both sets in each TLB). The */
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/* index corresponds to bits 15-19 of the EA. To invalidate all */
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/* entries within both TLBs, 32 tlbie instructions should be */
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/* issued, incrementing this field by one each time." */
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/* "Note that the tlbia instruction is not implemented on the */
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/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
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/* incrementing by 0x1000 each time. The code below is sort of */
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/* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
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/*--------------------------------------------------------------*/
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/*--------------------------------------------------------------*/
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* Note: requires that all cache bits in
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* HID0 are in the low half word.
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ori r4, r4, HID0_ILOCK
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ori r4, r3, HID0_ICFI
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mtspr HID0, r4 /* sets enable and invalidate, clears lock */
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mtspr HID0, r3 /* clears invalidate */
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.globl icache_disable
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ori r4, r4, HID0_ICE|HID0_ILOCK
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ori r4, r3, HID0_ICFI
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mtspr HID0, r4 /* sets invalidate, clears enable and lock */
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mtspr HID0, r3 /* clears invalidate */
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rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
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ori r4, r4, HID0_DLOCK
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mtspr HID0, r4 /* sets enable and invalidate, clears lock */
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mtspr HID0, r3 /* clears invalidate */
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.globl dcache_disable
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ori r4, r4, HID0_DCE|HID0_DLOCK
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mtspr HID0, r4 /* sets invalidate, clears enable and lock */
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mtspr HID0, r3 /* clears invalidate */
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rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
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#ifndef CONFIG_SPL_BUILD
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/*------------------------------------------------------------------------------*/
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* void relocate_code (addr_sp, gd, addr_moni)
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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* r5 = length in bytes
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mr r1, r3 /* Set new stack pointer */
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mr r9, r4 /* Save copy of Global Data pointer */
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mr r10, r5 /* Save copy of Destination Address */
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mr r3, r5 /* Destination Address */
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lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
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ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
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lwz r5, GOT(__init_end)
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li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
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* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
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/* First our own GOT */
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/* then the one used by the C code */
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beq cr1,4f /* In place copy is not necessary */
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beq 7f /* Protect against 0 count */
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* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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beq 7f /* Always flush prefetch queue in any case */
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mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
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rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
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sync /* Wait for all dcbst to complete on bus */
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9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
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rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
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7: sync /* Wait for all icbi to complete on bus */
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
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* Relocation Function, r12 point to got2+0x8000
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* Adjust got2 pointers, no need to check for 0, this code
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* already puts a few entries in the table.
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li r0,__got2_entries@sectoff@l
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la r3,GOT(_GOT2_TABLE_)
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lwz r11,GOT(_GOT2_TABLE_)
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* Now adjust the fixups and the pointers to the fixups
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* in case we need to move ourselves again.
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li r0,__fixup_entries@sectoff@l
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lwz r3,GOT(_FIXUP_TABLE_)
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* Now clear BSS segment
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lwz r3,GOT(__bss_start)
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lwz r4,GOT(__bss_end)
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mr r3, r9 /* Global Data pointer */
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mr r4, r10 /* Destination Address */
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* Copy exception vector code to low memory
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* r7: source address, r8: end address, r9: target address
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mflr r4 /* save link register */
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lwz r8, GOT(_end_of_vectors)
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li r9, 0x100 /* reset vector always at 0x100 */
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bgelr /* return if r7>=r8 - just in case */
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* relocate `hdlr' and `int_return' entries
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li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
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li r8, Alignment - _start + EXC_OFF_SYS_RESET
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addi r7, r7, 0x100 /* next exception vector */
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li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
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li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
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li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
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li r8, SystemCall - _start + EXC_OFF_SYS_RESET
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addi r7, r7, 0x100 /* next exception vector */
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li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
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li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
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addi r7, r7, 0x100 /* next exception vector */
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mfmsr r3 /* now that the vectors have */
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lis r7, MSR_IP@h /* relocated into low memory */
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ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
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andc r3, r3, r7 /* (if it was on) */
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SYNC /* Some chip revs need this... */
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mtlr r4 /* restore link register */
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#endif /* CONFIG_SPL_BUILD */