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Viewing changes to roms/u-boot/include/configs/icon.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/include/configs/icon.h
 
1
/*
 
2
 * (C) Copyright 2009-2010
 
3
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 
4
 *
 
5
 * SPDX-License-Identifier:     GPL-2.0+
 
6
 */
 
7
 
 
8
/*
 
9
 * icon.h - configuration for Mosaixtech ICON (440SPe)
 
10
 */
 
11
 
 
12
#ifndef __CONFIG_H
 
13
#define __CONFIG_H
 
14
 
 
15
/*
 
16
 * High Level Configuration Options
 
17
 */
 
18
#define CONFIG_ICON             1               /* Board is icon        */
 
19
#define CONFIG_440              1               /* ... PPC440 family    */
 
20
#define CONFIG_440SPE           1               /* Specifc SPe support  */
 
21
 
 
22
#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
 
23
 
 
24
#define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
 
25
#define CONFIG_SYS_4xx_RESET_TYPE 0x2   /* use chip reset on this board */
 
26
 
 
27
/*
 
28
 * Include common defines/options for all AMCC eval boards
 
29
 */
 
30
#define CONFIG_HOSTNAME         icon
 
31
#include "amcc-common.h"
 
32
 
 
33
#define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init  */
 
34
#define CONFIG_BOARD_EARLY_INIT_R       /* Call board_early_init_r */
 
35
 
 
36
/*
 
37
 * Base addresses -- Note these are effective addresses where the
 
38
 * actual resources get mapped (not physical addresses)
 
39
 */
 
40
#define CONFIG_SYS_FLASH_BASE   0xfc000000      /* later mapped to this addr */
 
41
#define CONFIG_SYS_ISRAM_BASE   0x90000000      /* internal SRAM        */
 
42
 
 
43
#define CONFIG_SYS_PCI_MEMBASE  0x80000000      /* mapped PCI memory    */
 
44
#define CONFIG_SYS_PCI_BASE     0xd0000000      /* internal PCI regs    */
 
45
#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
 
46
 
 
47
#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
 
48
#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* incr for PCIe port */
 
49
#define CONFIG_SYS_PCIE_BASE    0xe0000000      /* PCIe UTL regs */
 
50
 
 
51
#define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
 
52
#define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
 
53
#define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
 
54
#define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
 
55
#define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
 
56
#define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
 
57
 
 
58
/* base address of inbound PCIe window */
 
59
#define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
 
60
 
 
61
/* System RAM mapped to PCI space */
 
62
#define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
 
63
#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
 
64
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
 
65
 
 
66
#define CONFIG_SYS_ACE_BASE             0xfb000000      /* Xilinx ACE CF */
 
67
#define CONFIG_SYS_ACE_BASE_PHYS_H      0x4
 
68
#define CONFIG_SYS_ACE_BASE_PHYS_L      0xfe000000
 
69
 
 
70
#define CONFIG_SYS_FLASH_SIZE           (64 << 20)
 
71
#define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space */
 
72
#define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
 
73
#define CONFIG_SYS_FLASH_BASE_PHYS_L    0xEC000000
 
74
#define CONFIG_SYS_FLASH_BASE_PHYS      (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
 
75
                                         (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 
76
 
 
77
/*
 
78
 * Initial RAM & stack pointer (placed in internal SRAM)
 
79
 */
 
80
#define CONFIG_SYS_TEMP_STACK_OCM       1
 
81
#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
 
82
#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Init RAM */
 
83
#define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* size of used area */
 
84
 
 
85
#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 
86
                                         GENERATED_GBL_DATA_SIZE)
 
87
#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
88
 
 
89
/*
 
90
 * Serial Port
 
91
 */
 
92
#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 
93
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
 
94
 
 
95
/*
 
96
 * DDR2 SDRAM
 
97
 */
 
98
#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 
99
#define SPD_EEPROM_ADDRESS      { 0x51 } /* SPD I2C SPD addresses       */
 
100
#define CONFIG_DDR_ECC                  /* with ECC support             */
 
101
#define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 
102
 
 
103
/*
 
104
 * I2C
 
105
 */
 
106
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0   100000
 
107
 
 
108
#define CONFIG_SYS_SPD_BUS_NUM  0       /* The I2C bus for SPD          */
 
109
 
 
110
#define CONFIG_SYS_I2C_MULTI_EEPROMS
 
111
#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 
112
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 
113
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 
114
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
115
 
 
116
/* I2C bootstrap EEPROM */
 
117
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 
118
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 
119
#define CONFIG_4xx_CONFIG_BLOCKSIZE             8
 
120
 
 
121
/* I2C RTC */
 
122
#define CONFIG_RTC_M41T11
 
123
#define CONFIG_SYS_RTC_BUS_NUM  1       /* The I2C bus for RTC          */
 
124
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 
125
#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux       */
 
126
 
 
127
/*
 
128
 * Video options
 
129
 */
 
130
#define CONFIG_VIDEO
 
131
 
 
132
#ifdef CONFIG_VIDEO
 
133
#define CONFIG_VIDEO_SM501
 
134
#define CONFIG_VIDEO_SM501_32BPP
 
135
#define CONFIG_VIDEO_SM501_PCI
 
136
#define VIDEO_FB_LITTLE_ENDIAN
 
137
#define CONFIG_CFB_CONSOLE
 
138
#define CONFIG_VIDEO_LOGO
 
139
#define CONFIG_CONSOLE_EXTRA_INFO
 
140
#define CONFIG_VGA_AS_SINGLE_DEVICE
 
141
#define CONFIG_VIDEO_SW_CURSOR
 
142
#define CONFIG_VIDEO_BMP_RLE8
 
143
#define CONFIG_SPLASH_SCREEN
 
144
#define CFG_CONSOLE_IS_IN_ENV
 
145
#endif
 
146
 
 
147
/*
 
148
 * Environment
 
149
 */
 
150
#define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 
151
 
 
152
/*
 
153
 * Default environment variables
 
154
 */
 
155
#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 
156
        CONFIG_AMCC_DEF_ENV                                             \
 
157
        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 
158
        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 
159
        "kernel_addr=fc000000\0"                                        \
 
160
        "fdt_addr=fc1e0000\0"                                           \
 
161
        "ramdisk_addr=fc200000\0"                                       \
 
162
        "pciconfighost=1\0"                                             \
 
163
        "pcie_mode=RP:RP:RP\0"                                          \
 
164
        ""
 
165
 
 
166
/*
 
167
 * Commands additional to the ones defined in amcc-common.h
 
168
 */
 
169
#define CONFIG_CMD_CHIP_CONFIG
 
170
#define CONFIG_CMD_DATE
 
171
#define CONFIG_CMD_EXT2
 
172
#define CONFIG_CMD_FAT
 
173
#define CONFIG_CMD_PCI
 
174
#define CONFIG_CMD_SDRAM
 
175
#define CONFIG_CMD_SNTP
 
176
#ifdef CONFIG_VIDEO
 
177
#define CONFIG_CMD_BMP
 
178
#endif
 
179
 
 
180
#define CONFIG_IBM_EMAC4_V4             /* 440SPe has this EMAC version */
 
181
#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 
182
#define CONFIG_HAS_ETH0
 
183
#define CONFIG_PHY_RESET                /* reset phy upon startup       */
 
184
#define CONFIG_PHY_RESET_DELAY  1000
 
185
#define CONFIG_CIS8201_PHY              /* Enable RGMII mode for Cicada phy */
 
186
#define CONFIG_PHY_GIGE                 /* Include GbE speed/duplex det. */
 
187
 
 
188
/*
 
189
 * FLASH related
 
190
 */
 
191
#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 
192
#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 
193
#define CONFIG_SYS_FLASH_CFI_AMD_RESET  /* Use AMD (Spansion) reset cmd */
 
194
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method      */
 
195
 
 
196
#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 
197
#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of banks  */
 
198
#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors*/
 
199
 
 
200
#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 
201
#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 
202
 
 
203
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* use buffered writes  */
 
204
#define CONFIG_SYS_FLASH_EMPTY_INFO             /* 'E' for empty sector */
 
205
 
 
206
#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 
207
#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 
208
#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Env Sector     */
 
209
 
 
210
/* Address and size of Redundant Environment Sector     */
 
211
#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 
212
#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 
213
 
 
214
/*
 
215
 * PCI stuff
 
216
 */
 
217
/* General PCI */
 
218
#define CONFIG_PCI                      /* include pci support          */
 
219
#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 
220
#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 
221
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 
222
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
223
#define CONFIG_PCI_BOOTDELAY    1000    /* enable pci bootdelay variable*/
 
224
 
 
225
/* Board-specific PCI */
 
226
#define CONFIG_SYS_PCI_TARGET_INIT      /* let board init pci target    */
 
227
#undef  CONFIG_SYS_PCI_MASTER_INIT
 
228
 
 
229
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                  */
 
230
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever             */
 
231
 
 
232
/*
 
233
 * Xilinx System ACE support
 
234
 */
 
235
#define CONFIG_SYSTEMACE                /* Enable SystemACE support     */
 
236
#define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16 */
 
237
#define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
 
238
#define CONFIG_DOS_PARTITION
 
239
 
 
240
/*
 
241
 * External Bus Controller (EBC) Setup
 
242
 */
 
243
 
 
244
/* Memory Bank 0 (Flash) initialization                                 */
 
245
#define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_DISABLED      |           \
 
246
                                 EBC_BXAP_TWT_ENCODE(7)     |           \
 
247
                                 EBC_BXAP_BCE_DISABLE       |           \
 
248
                                 EBC_BXAP_BCT_2TRANS        |           \
 
249
                                 EBC_BXAP_CSN_ENCODE(0)     |           \
 
250
                                 EBC_BXAP_OEN_ENCODE(0)     |           \
 
251
                                 EBC_BXAP_WBN_ENCODE(0)     |           \
 
252
                                 EBC_BXAP_WBF_ENCODE(0)     |           \
 
253
                                 EBC_BXAP_TH_ENCODE(0)      |           \
 
254
                                 EBC_BXAP_RE_DISABLED       |           \
 
255
                                 EBC_BXAP_SOR_DELAYED       |           \
 
256
                                 EBC_BXAP_BEM_WRITEONLY     |           \
 
257
                                 EBC_BXAP_PEN_DISABLED)
 
258
#define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
 
259
                                 EBC_BXCR_BS_64MB                    |  \
 
260
                                 EBC_BXCR_BU_RW                      |  \
 
261
                                 EBC_BXCR_BW_16BIT)
 
262
 
 
263
/* Memory Bank 1 (Xilinx System ACE controller) initialization          */
 
264
#define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED      |           \
 
265
                                 EBC_BXAP_TWT_ENCODE(4)     |           \
 
266
                                 EBC_BXAP_BCE_DISABLE       |           \
 
267
                                 EBC_BXAP_BCT_2TRANS        |           \
 
268
                                 EBC_BXAP_CSN_ENCODE(0)     |           \
 
269
                                 EBC_BXAP_OEN_ENCODE(0)     |           \
 
270
                                 EBC_BXAP_WBN_ENCODE(0)     |           \
 
271
                                 EBC_BXAP_WBF_ENCODE(0)     |           \
 
272
                                 EBC_BXAP_TH_ENCODE(0)      |           \
 
273
                                 EBC_BXAP_RE_DISABLED       |           \
 
274
                                 EBC_BXAP_SOR_NONDELAYED    |           \
 
275
                                 EBC_BXAP_BEM_WRITEONLY     |           \
 
276
                                 EBC_BXAP_PEN_DISABLED)
 
277
#define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
 
278
                                 EBC_BXCR_BS_1MB                    |   \
 
279
                                 EBC_BXCR_BU_RW                     |   \
 
280
                                 EBC_BXCR_BW_16BIT)
 
281
 
 
282
/*
 
283
 * Initialize EBC CONFIG -
 
284
 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 
285
 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 
286
 */
 
287
#define CONFIG_SYS_EBC_CFG      (EBC_CFG_LE_UNLOCK    | \
 
288
                                 EBC_CFG_PTD_ENABLE   | \
 
289
                                 EBC_CFG_RTC_16PERCLK | \
 
290
                                 EBC_CFG_ATC_PREVIOUS | \
 
291
                                 EBC_CFG_DTC_PREVIOUS | \
 
292
                                 EBC_CFG_CTC_PREVIOUS | \
 
293
                                 EBC_CFG_OEO_PREVIOUS | \
 
294
                                 EBC_CFG_EMC_DEFAULT  | \
 
295
                                 EBC_CFG_PME_DISABLE  | \
 
296
                                 EBC_CFG_PR_16)
 
297
 
 
298
/*
 
299
 * GPIO Setup
 
300
 */
 
301
#define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
 
302
#define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
 
303
#define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
 
304
#define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
 
305
 
 
306
#define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 
307
                                 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 
308
                                 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 
309
                                 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 
310
#define CONFIG_SYS_GPIO_OR      GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 
311
#define CONFIG_SYS_GPIO_TCR     GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 
312
#define CONFIG_SYS_GPIO_ODR     0
 
313
 
 
314
#endif  /* __CONFIG_H */