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* Sascha Hauer, Pengutronix
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* SPDX-License-Identifier: GPL-2.0+
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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u32 mfi = GET_PLL_MFI(reg);
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s32 mfn = GET_PLL_MFN(reg);
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u32 mfd = GET_PLL_MFD(reg);
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u32 pd = GET_PLL_PD(reg);
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mfi = mfi <= 5 ? 5 : mfi;
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mfn = mfn >= 512 ? mfn - 1024 : mfn;
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return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
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static u32 mx31_get_mpl_dpdgck_clk(void)
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if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
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infreq = MXC_CLK32 * 1024;
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return mx31_decode_pll(readl(CCM_MPCTL), infreq);
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static u32 mx31_get_mcu_main_clk(void)
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/* For now we assume mpl_dpdgck_clk == mcu_main_clk
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* which should be correct for most boards
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return mx31_get_mpl_dpdgck_clk();
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static u32 mx31_get_ipg_clk(void)
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u32 freq = mx31_get_mcu_main_clk();
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u32 pdr0 = readl(CCM_PDR0);
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freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
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freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
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/* hsp is the clock for the ipu */
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static u32 mx31_get_hsp_clk(void)
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u32 freq = mx31_get_mcu_main_clk();
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u32 pdr0 = readl(CCM_PDR0);
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freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
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void mx31_dump_clocks(void)
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u32 cpufreq = mx31_get_mcu_main_clk();
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printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
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printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
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printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
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unsigned int mxc_get_clock(enum mxc_clock clk)
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return mx31_get_mcu_main_clk();
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return mx31_get_ipg_clk();
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return mx31_get_hsp_clk();
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u32 imx_get_uartclk(void)
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return mxc_get_clock(MXC_UART_CLK);
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void mx31_gpio_mux(unsigned long mode)
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unsigned long reg, shift, tmp;
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reg = IOMUXC_BASE + (mode & 0x1fc);
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shift = (~mode & 0x3) * 8;
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tmp &= ~(0xff << shift);
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tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
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void mx31_set_pad(enum iomux_pins pin, u32 config)
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pin &= IOMUX_PADNUM_MASK;
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reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
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field = (pin + 2) % 3;
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l &= ~(0x1ff << (field * 10));
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l |= config << (field * 10);
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void mx31_set_gpr(enum iomux_gp_func gp, char en)
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struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
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l = readl(&iomuxc->gpr);
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writel(l, &iomuxc->gpr);
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void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
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struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
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struct mx31_weim_cscr *cscr = &weim->cscr[cs];
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writel(weimcs->upper, &cscr->upper);
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writel(weimcs->lower, &cscr->lower);
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writel(weimcs->additional, &cscr->additional);
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struct mx3_cpu_type mx31_cpu_type[] = {
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{ .srev = 0x00, .v = 0x10 },
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{ .srev = 0x10, .v = 0x11 },
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{ .srev = 0x11, .v = 0x11 },
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{ .srev = 0x12, .v = 0x1F },
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{ .srev = 0x13, .v = 0x1F },
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{ .srev = 0x14, .v = 0x12 },
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{ .srev = 0x15, .v = 0x12 },
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{ .srev = 0x28, .v = 0x20 },
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{ .srev = 0x29, .v = 0x20 },
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u32 get_cpu_rev(void)
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/* read SREV register from IIM module */
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struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
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srev = readl(&iim->iim_srev);
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for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
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if (srev == mx31_cpu_type[i].srev)
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return mx31_cpu_type[i].v;
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return srev | 0x8000;
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static char *get_reset_cause(void)
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/* read RCSR register from CCM module */
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struct clock_control_regs *ccm =
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(struct clock_control_regs *)CCM_BASE;
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u32 cause = readl(&ccm->rcsr) & 0x07;
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return "ARM11P power gating";
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return "unknown reset";
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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u32 srev = get_cpu_rev();
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printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
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(srev & 0xF0) >> 4, (srev & 0x0F),
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((srev & 0x8000) ? " unknown" : ""),
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mx31_get_mcu_main_clk() / 1000000);
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printf("Reset cause: %s\n", get_reset_cause());