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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/xes/xpedite1000/init.S
 
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/*
 
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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*/
 
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#include <ppc_asm.tmpl>
 
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#include <asm/mmu.h>
 
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#include <config.h>
 
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#include <asm/ppc4xx.h>
 
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/*
 
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 * TLB TABLE
 
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 *
 
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 * This table is used by the cpu boot code to setup the initial tlb
 
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 * entries. Rather than make broad assumptions in the cpu source tree,
 
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 * this table lets each board set things up however they like.
 
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 *
 
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 * Pointer to the table is returned in r1
 
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 */
 
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        .section .bootpg,"ax"
 
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        .globl tlbtab
 
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tlbtab:
 
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        tlbtab_start
 
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        tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
 
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        tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
 
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        tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
 
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        tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
 
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        tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
 
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        tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
 
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        tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
 
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        tlbtab_end