2
* U-boot - Configuration file for BF561 EZKIT board
5
#ifndef __CONFIG_BF561_EZKIT_H__
6
#define __CONFIG_BF561_EZKIT_H__
8
#include <asm/config-pre.h>
14
#define CONFIG_BFIN_CPU bf561-0.3
15
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
20
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
23
/* CONFIG_CLKIN_HZ is any value in Hz */
24
#define CONFIG_CLKIN_HZ 30000000
25
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
27
#define CONFIG_CLKIN_HALF 0
28
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
30
#define CONFIG_PLL_BYPASS 0
31
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32
/* Values can range from 0-63 (where 0 means 64) */
33
#define CONFIG_VCO_MULT 20
34
/* CCLK_DIV controls the core clock divider */
35
/* Values can be 1, 2, 4, or 8 ONLY */
36
#define CONFIG_CCLK_DIV 1
37
/* SCLK_DIV controls the system clock divider */
38
/* Values can range from 1-15 */
39
#define CONFIG_SCLK_DIV 6
45
#define CONFIG_MEM_ADD_WDTH 9
46
#define CONFIG_MEM_SIZE 64
48
#define CONFIG_EBIU_SDRRC_VAL 0x306
49
#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
51
#define CONFIG_EBIU_AMGCTL_VAL 0x3F
52
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
55
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
62
#define ADI_CMDS_NETWORK 1
63
#define CONFIG_SMC91111 1
64
#define CONFIG_SMC91111_BASE 0x2C010300
65
#define CONFIG_SMC_USE_32_BIT 1
66
#define CONFIG_HOSTNAME bf561-ezkit
67
/* Uncomment next line to use fixed MAC address */
68
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
74
#define CONFIG_SYS_FLASH_CFI
75
#define CONFIG_FLASH_CFI_DRIVER
76
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
77
#define CONFIG_SYS_FLASH_BASE 0x20000000
78
#define CONFIG_SYS_MAX_FLASH_BANKS 1
79
#define CONFIG_SYS_MAX_FLASH_SECT 135
80
/* The BF561-EZKIT uses a top boot flash */
81
#define CONFIG_ENV_IS_IN_FLASH 1
82
#define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE)
83
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
84
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
85
#define CONFIG_ENV_SECT_SIZE 0x2000
91
#define CONFIG_SYS_I2C_SOFT
92
#ifdef CONFIG_SYS_I2C_SOFT
93
#define CONFIG_SYS_I2C
94
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
95
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
96
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
97
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
98
#define CONFIG_SYS_I2C_SOFT_SLAVE 0
104
#define CONFIG_UART_CONSOLE 0
105
#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
108
* Run core 1 from L1 SRAM start address when init uboot on core 0
110
/* #define CONFIG_CORE1_RUN 1 */
114
* Pull in common ADI header for remaining command/environment setup
116
#include <configs/bfin_adi_common.h>