3
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5
* SPDX-License-Identifier: GPL-2.0+
7
* modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
11
* db64460.c - main board support/init for the Galileo Eval board.
16
#include "../include/memory.h"
17
#include "../include/pci.h"
18
#include "../include/mv_gen_reg.h"
21
#include <linux/compiler.h>
40
/* ------------------------------------------------------------------------- */
42
/* this is the current GT register space location */
43
/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
45
/* Unfortunately, we cant change it while we are in flash, so we initialize it
46
* to the "final" value. This means that any debug_led calls before
47
* board_early_init_f wont work right (like in cpu_init_f).
48
* See also my_remap_gt_regs below. (NTL)
51
void board_prebootm_init (void);
52
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
53
int display_mem_map (void);
55
/* ------------------------------------------------------------------------- */
58
* This is a version of the GT register space remapping function that
59
* doesn't touch globals (meaning, it's ok to run from flash.)
61
* Unfortunately, this has the side effect that a writable
62
* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
65
void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
69
/* check and see if it's already moved */
71
/* original ppcboot 1.1.6 source
73
temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
74
if ((temp & 0xffff) == new_loc >> 20)
77
temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
78
0xffff0000) | (new_loc >> 20);
80
out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
82
while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
83
original ppcboot 1.1.6 source end */
85
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
86
if ((temp & 0xffff) == new_loc >> 16)
89
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
90
0xffff0000) | (new_loc >> 16);
92
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
94
while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
99
static void gt_pci_config (void)
102
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
104
/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
105
* config registers by writing ones to the bus and device.
106
* We then update the Virtual register with the correct value for the bus and device.
108
if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
109
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
111
GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
113
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
114
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
115
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
118
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
119
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
120
GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
122
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
123
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
124
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
128
PCI_MASTER_ENABLE (0, SELF);
129
PCI_MASTER_ENABLE (1, SELF);
131
/* Enable PCI0/1 Mem0 and IO 0 disable all others */
132
GT_REG_READ (BASE_ADDR_ENABLE, &stat);
133
stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
136
stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
137
GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
139
/* ronen- add write to pci remap registers for 64460.
140
in 64360 when writing to pci base go and overide remap automaticaly,
141
in 64460 it doesn't */
142
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
143
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
144
GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
146
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
147
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
148
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
150
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
151
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
152
GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
154
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
155
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
156
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
158
/* PCI interface settings */
159
/* Timeout set to retry forever */
160
GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
161
GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
163
/* ronen - enable only CS0 and Internal reg!! */
164
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
165
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
167
/*ronen update the pci internal registers base address.*/
169
for (stat = 0; stat <= PCI_HOST1; stat++)
170
pciWriteConfigReg (stat,
171
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
172
SELF, CONFIG_SYS_GT_REGS);
178
/* Setup CPU interface paramaters */
179
static void gt_cpu_config (void)
181
cpu_t cpu = get_cpu_type ();
184
/* cpu configuration register */
185
tmp = GTREGREAD (CPU_CONFIGURATION);
187
/* set the SINGLE_CPU bit see MV64460 P.399 */
188
#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
189
tmp |= CPU_CONF_SINGLE_CPU;
192
tmp &= ~CPU_CONF_AACK_DELAY_2;
194
tmp |= CPU_CONF_DP_VALID;
195
tmp |= CPU_CONF_AP_VALID;
197
tmp |= CPU_CONF_PIPELINE;
199
GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
201
/* CPU master control register */
202
tmp = GTREGREAD (CPU_MASTER_CONTROL);
204
tmp |= CPU_MAST_CTL_ARB_EN;
206
if ((cpu == CPU_7400) ||
207
(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
209
tmp |= CPU_MAST_CTL_CLEAN_BLK;
210
tmp |= CPU_MAST_CTL_FLUSH_BLK;
213
/* cleanblock must be cleared for CPUs
214
* that do not support this command (603e, 750)
216
tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
217
tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
219
GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
223
* board_early_init_f.
225
* set up gal. device mappings, etc.
227
int board_early_init_f (void)
232
* set up the GT the way the kernel wants it
233
* the call to move the GT register space will obviously
234
* fail if it has already been done, but we're going to assume
235
* that if it's not at the power-on location, it's where we put
236
* it last time. (huber)
239
my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
241
/* No PCI in first release of Port To_do: enable it. */
245
/* mask all external interrupt sources */
246
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
247
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
249
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
250
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
251
/* --------------------- */
252
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
253
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
254
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
255
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
256
/* does not exist in MV6446x
257
GT_REG_WRITE(CPU_INT_0_MASK, 0);
258
GT_REG_WRITE(CPU_INT_1_MASK, 0);
259
GT_REG_WRITE(CPU_INT_2_MASK, 0);
260
GT_REG_WRITE(CPU_INT_3_MASK, 0);
261
--------------------- */
264
/* ----- DEVICE BUS SETTINGS ------ */
271
* 3 - Flash checked 32Bit Intel Strata
272
* boot - BootCS checked 8Bit 29LV040B
280
* the dual 7450 module requires burst access to the boot
281
* device, so the serial rom copies the boot device to the
282
* on-board sram on the eval board, and updates the correct
283
* registers to boot from the sram. (device0)
285
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
288
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
290
memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
291
memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
292
memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
295
/* configure device timing */
296
#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
298
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
301
#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
302
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
304
#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
305
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
308
#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
309
/* detect if we are booting from the 32 bit flash */
310
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
311
/* 32 bit boot flash */
312
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
313
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
314
CONFIG_SYS_32BIT_BOOT_PAR);
316
/* 8 bit boot flash */
317
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
318
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
321
/* 8 bit boot flash only */
322
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
329
GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
330
GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
331
GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
332
GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
334
GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
342
/* various things to do after relocation */
357
/* disable the dcache and MMU */
363
void after_reloc (ulong dest_addr, gd_t * gd)
365
/* check to see if we booted from the sram. If so, move things
366
* back to the way they should be. (we're running from main
367
* memory at this point now */
368
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
369
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
370
memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
373
/* now, jump to the main ppcboot board init code */
374
board_init_r (gd, dest_addr);
378
/* ------------------------------------------------------------------------- */
381
* Check Board Identity:
383
* right now, assume borad type. (there is just one...after all)
386
int checkboard (void)
390
printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
394
/* utility functions */
395
void debug_led (int led, int mode)
397
volatile int *addr = 0;
398
__maybe_unused int dummy;
403
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
408
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
413
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
417
} else if (mode == 0) {
420
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
425
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
430
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
439
int display_mem_map (void)
442
unsigned int base, size, width;
445
printf ("SD (DDR) RAM\n");
446
for (i = 0; i <= BANK3; i++) {
447
base = memoryGetBankBaseAddress (i);
448
size = memoryGetBankSize (i);
450
printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
451
i, base, size >> 20);
455
/* CPU's PCI windows */
456
for (i = 0; i <= PCI_HOST1; i++) {
457
printf ("\nCPU's PCI %d windows\n", i);
458
base = pciGetSpaceBase (i, PCI_IO);
459
size = pciGetSpaceSize (i, PCI_IO);
460
printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
465
/*ronen currently only first PCI MEM is used 3 */ ;
467
base = pciGetSpaceBase (i, j);
468
size = pciGetSpaceSize (i, j);
469
printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
474
printf ("\nDEVICES\n");
475
for (i = 0; i <= DEVICE3; i++) {
476
base = memoryGetDeviceBaseAddress (i);
477
size = memoryGetDeviceSize (i);
478
width = memoryGetDeviceWidth (i) * 8;
479
printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
481
printf ("\t- EXT SRAM (actual - 1M)\n");
483
printf ("\t- RTC\n");
485
printf ("\t- UART\n");
487
printf ("\t- LARGE FLASH\n");
491
base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
492
size = memoryGetDeviceSize (BOOT_DEVICE);
493
width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
494
printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
495
base, size >> 20, width);
499
/* DRAM check routines copied from gw8260 */
501
#if defined (CONFIG_SYS_DRAM_TEST)
503
/*********************************************************************/
504
/* NAME: move64() - moves a double word (64-bit) */
507
/* this function performs a double word move from the data at */
508
/* the source pointer to the location at the destination pointer. */
511
/* unsigned long long *src - pointer to data to move */
514
/* unsigned long long *dest - pointer to locate to move data */
519
/* RESTRICTIONS/LIMITATIONS: */
520
/* May cloober fr0. */
522
/*********************************************************************/
523
static void move64 (unsigned long long *src, unsigned long long *dest)
525
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
526
"stfd 0, 0(4)" /* *dest = fpr0 */
527
: : : "fr0"); /* Clobbers fr0 */
532
#if defined (CONFIG_SYS_DRAM_TEST_DATA)
534
unsigned long long pattern[] = {
535
0xaaaaaaaaaaaaaaaaULL,
536
0xccccccccccccccccULL,
537
0xf0f0f0f0f0f0f0f0ULL,
538
0xff00ff00ff00ff00ULL,
539
0xffff0000ffff0000ULL,
540
0xffffffff00000000ULL,
541
0x00000000ffffffffULL,
542
0x0000ffff0000ffffULL,
543
0x00ff00ff00ff00ffULL,
544
0x0f0f0f0f0f0f0f0fULL,
545
0x3333333333333333ULL,
546
0x5555555555555555ULL,
549
/*********************************************************************/
550
/* NAME: mem_test_data() - test data lines for shorts and opens */
553
/* Tests data lines for shorts and opens by forcing adjacent data */
554
/* to opposite states. Because the data lines could be routed in */
555
/* an arbitrary manner the must ensure test patterns ensure that */
556
/* every case is tested. By using the following series of binary */
557
/* patterns every combination of adjacent bits is test regardless */
560
/* ...101010101010101010101010 */
561
/* ...110011001100110011001100 */
562
/* ...111100001111000011110000 */
563
/* ...111111110000000011111111 */
565
/* Carrying this out, gives us six hex patterns as follows: */
567
/* 0xaaaaaaaaaaaaaaaa */
568
/* 0xcccccccccccccccc */
569
/* 0xf0f0f0f0f0f0f0f0 */
570
/* 0xff00ff00ff00ff00 */
571
/* 0xffff0000ffff0000 */
572
/* 0xffffffff00000000 */
574
/* The number test patterns will always be given by: */
576
/* log(base 2)(number data bits) = log2 (64) = 6 */
578
/* To test for short and opens to other signals on our boards. we */
580
/* test with the 1's complemnt of the paterns as well. */
583
/* Displays failing test pattern */
586
/* 0 - Passed test */
587
/* 1 - Failed test */
589
/* RESTRICTIONS/LIMITATIONS: */
590
/* Assumes only one one SDRAM bank */
592
/*********************************************************************/
593
int mem_test_data (void)
595
unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
596
unsigned long long temp64 = 0;
597
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
601
for (i = 0; i < num_patterns; i++) {
602
move64 (&(pattern[i]), pmem);
603
move64 (pmem, &temp64);
605
/* hi = (temp64>>32) & 0xffffffff; */
606
/* lo = temp64 & 0xffffffff; */
607
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
609
hi = (pattern[i] >> 32) & 0xffffffff;
610
lo = pattern[i] & 0xffffffff;
611
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
613
if (temp64 != pattern[i]) {
614
printf ("\n Data Test Failed, pattern 0x%08x%08x",
622
#endif /* CONFIG_SYS_DRAM_TEST_DATA */
624
#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
625
/*********************************************************************/
626
/* NAME: mem_test_address() - test address lines */
629
/* This function performs a test to verify that each word im */
630
/* memory is uniquly addressable. The test sequence is as follows: */
632
/* 1) write the address of each word to each word. */
633
/* 2) verify that each location equals its address */
636
/* Displays failing test pattern and address */
639
/* 0 - Passed test */
640
/* 1 - Failed test */
642
/* RESTRICTIONS/LIMITATIONS: */
645
/*********************************************************************/
646
int mem_test_address (void)
648
volatile unsigned int *pmem =
649
(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
650
const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
653
/* write address to each location */
654
for (i = 0; i < size; i++) {
658
/* verify each loaction */
659
for (i = 0; i < size; i++) {
661
printf ("\n Address Test Failed at 0x%x", i);
667
#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
669
#if defined (CONFIG_SYS_DRAM_TEST_WALK)
670
/*********************************************************************/
671
/* NAME: mem_march() - memory march */
674
/* Marches up through memory. At each location verifies rmask if */
675
/* read = 1. At each location write wmask if write = 1. Displays */
676
/* failing address and pattern. */
679
/* volatile unsigned long long * base - start address of test */
680
/* unsigned int size - number of dwords(64-bit) to test */
681
/* unsigned long long rmask - read verify mask */
682
/* unsigned long long wmask - wrtie verify mask */
683
/* short read - verifies rmask if read = 1 */
684
/* short write - writes wmask if write = 1 */
687
/* Displays failing test pattern and address */
690
/* 0 - Passed test */
691
/* 1 - Failed test */
693
/* RESTRICTIONS/LIMITATIONS: */
696
/*********************************************************************/
697
int mem_march (volatile unsigned long long *base,
699
unsigned long long rmask,
700
unsigned long long wmask, short read, short write)
703
unsigned long long temp = 0;
704
unsigned int hitemp, lotemp, himask, lomask;
706
for (i = 0; i < size; i++) {
708
/* temp = base[i]; */
709
move64 ((unsigned long long *) &(base[i]), &temp);
711
hitemp = (temp >> 32) & 0xffffffff;
712
lotemp = temp & 0xffffffff;
713
himask = (rmask >> 32) & 0xffffffff;
714
lomask = rmask & 0xffffffff;
716
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
721
/* base[i] = wmask; */
722
move64 (&wmask, (unsigned long long *) &(base[i]));
727
#endif /* CONFIG_SYS_DRAM_TEST_WALK */
729
/*********************************************************************/
730
/* NAME: mem_test_walk() - a simple walking ones test */
733
/* Performs a walking ones through entire physical memory. The */
734
/* test uses as series of memory marches, mem_march(), to verify */
735
/* and write the test patterns to memory. The test sequence is as */
737
/* 1) march writing 0000...0001 */
738
/* 2) march verifying 0000...0001 , writing 0000...0010 */
739
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
740
/* the write mask equals 1000...0000 */
741
/* 4) march verifying 1000...0000 */
742
/* The test fails if any of the memory marches return a failure. */
745
/* Displays which pass on the memory test is executing */
748
/* 0 - Passed test */
749
/* 1 - Failed test */
751
/* RESTRICTIONS/LIMITATIONS: */
754
/*********************************************************************/
755
int mem_test_walk (void)
757
unsigned long long mask;
758
volatile unsigned long long *pmem =
759
(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
760
const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
766
printf ("Initial Pass");
767
mem_march (pmem, size, 0x0, 0x1, 0, 1);
769
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
772
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
774
for (i = 0; i < 63; i++) {
775
printf ("Pass %2d", i + 2);
776
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
777
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
781
printf ("\b\b\b\b\b\b\b");
784
printf ("Last Pass");
785
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
786
/* printf("mask: 0x%x", mask); */
789
printf ("\b\b\b\b\b\b\b\b\b");
791
printf ("\b\b\b\b\b\b\b\b\b");
796
/*********************************************************************/
797
/* NAME: testdram() - calls any enabled memory tests */
800
/* Runs memory tests if the environment test variables are set to */
804
/* testdramdata - If set to 'y', data test is run. */
805
/* testdramaddress - If set to 'y', address test is run. */
806
/* testdramwalk - If set to 'y', walking ones test is run */
812
/* 0 - Passed test */
813
/* 1 - Failed test */
815
/* RESTRICTIONS/LIMITATIONS: */
818
/*********************************************************************/
821
int rundata, runaddress, runwalk;
823
rundata = getenv_yesno("testdramdata") == 1;
824
runaddress = getenv_yesno("testdramaddress") == 1;
825
runwalk = getenv_yesno("testdramwalk") == 1;
828
/* runaddress = 0; */
831
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
832
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
834
#ifdef CONFIG_SYS_DRAM_TEST_DATA
836
printf ("Test DATA ... ");
837
if (mem_test_data () == 1) {
838
printf ("failed \n");
844
#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
845
if (runaddress == 1) {
846
printf ("Test ADDRESS ... ");
847
if (mem_test_address () == 1) {
848
printf ("failed \n");
854
#ifdef CONFIG_SYS_DRAM_TEST_WALK
856
printf ("Test WALKING ONEs ... ");
857
if (mem_test_walk () == 1) {
858
printf ("failed \n");
864
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
870
#endif /* CONFIG_SYS_DRAM_TEST */
872
/* ronen - the below functions are used by the bootm function */
873
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
874
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
875
/* the kernel data areas. */
876
/* - we diable and invalidate the icache and dcache. */
877
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
881
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
882
if ((temp & 0xffff) == new_loc >> 16)
885
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
886
0xffff0000) | (new_loc >> 16);
888
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
890
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
892
(INTERNAL_SPACE_DECODE)))))
897
void board_prebootm_init ()
900
/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
901
GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
903
/* Stop GigE Rx DMA engines */
904
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
905
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
906
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
908
/* Relocate MV64460 internal regs */
909
my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
915
int board_eth_init(bd_t *bis)
918
ret = pci_eth_init(bis);
920
ret = mv6446x_eth_initialize(bis);