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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/include/configs/GEN860T.h
 
1
/*
 
2
 * (C) Copyright 2000
 
3
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
4
 * Keith Outwater, keith_outwater@mvis.com
 
5
 *
 
6
 * SPDX-License-Identifier:     GPL-2.0+
 
7
 */
 
8
 
 
9
/*
 
10
 * board/config_GEN860T.h - board specific configuration options
 
11
 */
 
12
 
 
13
#ifndef __CONFIG_GEN860T_H
 
14
#define __CONFIG_H
 
15
 
 
16
/*
 
17
 * High Level Configuration Options
 
18
 */
 
19
#define CONFIG_MPC860
 
20
#define CONFIG_GEN860T
 
21
 
 
22
#define CONFIG_SYS_TEXT_BASE            0x40000000
 
23
 
 
24
/*
 
25
 * Identify the board
 
26
 */
 
27
#if !defined(CONFIG_SC)
 
28
#define CONFIG_IDENT_STRING             " B2"
 
29
#else
 
30
#define CONFIG_IDENT_STRING             " SC"
 
31
#endif
 
32
 
 
33
/*
 
34
 * Don't depend on the RTC clock to determine clock frequency -
 
35
 * the 860's internal rtc uses a 32.768 KHz clock which is
 
36
 * generated by the DS1337 - and the DS1337 clock can be turned off.
 
37
 */
 
38
#if !defined(CONFIG_SC)
 
39
#define CONFIG_8xx_GCLK_FREQ            66600000
 
40
#else
 
41
#define CONFIG_8xx_GCLK_FREQ            48000000
 
42
#endif
 
43
 
 
44
/*
 
45
 * The RS-232 console port is on SMC1
 
46
 */
 
47
#define CONFIG_8xx_CONS_SMC1
 
48
#define CONFIG_BAUDRATE                 38400
 
49
 
 
50
/*
 
51
 * Print console information
 
52
 */
 
53
#undef   CONFIG_SYS_CONSOLE_INFO_QUIET
 
54
 
 
55
/*
 
56
 * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
 
57
 */
 
58
#define CONFIG_BOOTDELAY                                5
 
59
 
 
60
/*
 
61
 * Pass the clock frequency to the Linux kernel in units of MHz
 
62
 */
 
63
#define CONFIG_CLOCKS_IN_MHZ
 
64
 
 
65
#define CONFIG_PREBOOT          \
 
66
        "echo;echo"
 
67
 
 
68
#undef  CONFIG_BOOTARGS
 
69
#define CONFIG_BOOTCOMMAND      \
 
70
        "bootp;" \
 
71
        "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
 
72
        "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
 
73
        "bootm"
 
74
 
 
75
/*
 
76
 * Turn off echo for serial download by default.  Allow baud rate to be changed
 
77
 * for downloads
 
78
 */
 
79
#undef  CONFIG_LOADS_ECHO
 
80
#define CONFIG_SYS_LOADS_BAUD_CHANGE
 
81
 
 
82
/*
 
83
 * Turn off the watchdog timer
 
84
 */
 
85
#undef  CONFIG_WATCHDOG
 
86
 
 
87
/*
 
88
 * Do not reboot if a panic occurs
 
89
 */
 
90
#define CONFIG_PANIC_HANG
 
91
 
 
92
/*
 
93
 * Enable the status LED
 
94
 */
 
95
#define CONFIG_STATUS_LED
 
96
 
 
97
/*
 
98
 * Reset address. We pick an address such that when an instruction
 
99
 * is executed at that address, a machine check exception occurs
 
100
 */
 
101
#define CONFIG_SYS_RESET_ADDRESS                                ((ulong) -1)
 
102
 
 
103
/*
 
104
 * BOOTP options
 
105
 */
 
106
#define CONFIG_BOOTP_SUBNETMASK
 
107
#define CONFIG_BOOTP_GATEWAY
 
108
#define CONFIG_BOOTP_HOSTNAME
 
109
#define CONFIG_BOOTP_BOOTPATH
 
110
#define CONFIG_BOOTP_BOOTFILESIZE
 
111
 
 
112
 
 
113
/*
 
114
 * The GEN860T network interface uses the on-chip 10/100 FEC with
 
115
 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 
116
 * MII address is hardwired on the board to zero.
 
117
 */
 
118
#define CONFIG_FEC_ENET
 
119
#define CONFIG_SYS_DISCOVER_PHY
 
120
#define CONFIG_MII
 
121
#define CONFIG_MII_INIT                 1
 
122
#define CONFIG_PHY_ADDR                 0
 
123
 
 
124
/*
 
125
 * Set default IP stuff just to get bootstrap entries into the
 
126
 * environment so that we can source the full default environment.
 
127
 */
 
128
#define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 
129
#define CONFIG_SERVERIP                                 10.0.4.201
 
130
#define CONFIG_IPADDR                                   10.0.4.111
 
131
 
 
132
/*
 
133
 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 
134
 * the MPC860T I2C interface.
 
135
 */
 
136
#define CONFIG_SYS_I2C_EEPROM_ADDR                              0x50
 
137
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS               6               /* 64 byte pages                */
 
138
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12              /* 10 mS w/ 20% margin  */
 
139
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN                  2               /* need 16 bit address  */
 
140
#define CONFIG_ENV_EEPROM_SIZE                          (32 * 1024)
 
141
 
 
142
/*
 
143
 * Enable I2C and select the hardware/software driver
 
144
 */
 
145
#define CONFIG_HARD_I2C         1               /* CPM based I2C */
 
146
#undef  CONFIG_SYS_I2C_SOFT                     /* Bit-banged I2C */
 
147
 
 
148
#ifdef CONFIG_HARD_I2C
 
149
#define CONFIG_SYS_I2C_SPEED            100000  /* clock speed in Hz */
 
150
#define CONFIG_SYS_I2C_SLAVE            0xFE    /* I2C slave address */
 
151
#endif
 
152
 
 
153
#ifdef CONFIG_SYS_I2C_SOFT
 
154
#define CONFIG_SYS_I2C
 
155
#define CONFIG_SYS_I2C_SOFT_SPEED       50000
 
156
#define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 
157
#define PB_SCL          0x00000020              /* PB 26 */
 
158
#define PB_SDA          0x00000010              /* PB 27 */
 
159
#define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 
160
#define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 
161
#define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 
162
#define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 
163
#define I2C_SDA(bit)    if (bit) \
 
164
                                immr->im_cpm.cp_pbdat |=  PB_SDA; \
 
165
                        else \
 
166
                                immr->im_cpm.cp_pbdat &= ~PB_SDA
 
167
#define I2C_SCL(bit)    if (bit) \
 
168
                                immr->im_cpm.cp_pbdat |=  PB_SCL; \
 
169
                        else \
 
170
                                immr->im_cpm.cp_pbdat &= ~PB_SCL
 
171
#define I2C_DELAY       udelay(5) /* 1/4 I2C clock duration */
 
172
#endif
 
173
 
 
174
/*
 
175
 * Allow environment overwrites by anyone
 
176
 */
 
177
#define CONFIG_ENV_OVERWRITE
 
178
 
 
179
#if !defined(CONFIG_SC)
 
180
/*
 
181
 * The MPC860's internal RTC is horribly broken in rev D masks. Three
 
182
 * internal MPC860T circuit nodes were inadvertently left floating; this
 
183
 * causes KAPWR current in power down mode to be three orders of magnitude
 
184
 * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 
185
 * reasonable battery can keep that kind RTC running during powerdown for any
 
186
 * length of time, so we use an external RTC on the I2C bus instead.
 
187
 */
 
188
#define CONFIG_RTC_DS1337
 
189
#define CONFIG_SYS_I2C_RTC_ADDR                         0x68
 
190
 
 
191
#else
 
192
/*
 
193
 * No external RTC on SC variant, so we're stuck with the internal one.
 
194
 */
 
195
#define CONFIG_RTC_MPC8xx
 
196
#endif
 
197
 
 
198
/*
 
199
 * Power On Self Test support
 
200
 */
 
201
#define CONFIG_POST                       ( CONFIG_SYS_POST_CACHE               | \
 
202
                                                                CONFIG_SYS_POST_MEMORY          | \
 
203
                                                                CONFIG_SYS_POST_CPU             | \
 
204
                                                                CONFIG_SYS_POST_UART            | \
 
205
                                                                CONFIG_SYS_POST_SPR )
 
206
 
 
207
 
 
208
/*
 
209
 * Command line configuration.
 
210
 */
 
211
#include <config_cmd_default.h>
 
212
 
 
213
#define CONFIG_CMD_ASKENV
 
214
#define CONFIG_CMD_DHCP
 
215
#define CONFIG_CMD_I2C
 
216
#define CONFIG_CMD_EEPROM
 
217
#define CONFIG_CMD_REGINFO
 
218
#define CONFIG_CMD_IMMAP
 
219
#define CONFIG_CMD_ELF
 
220
#define CONFIG_CMD_DATE
 
221
#define CONFIG_CMD_FPGA
 
222
#define CONFIG_CMD_MII
 
223
#define CONFIG_CMD_BEDBUG
 
224
 
 
225
#ifdef CONFIG_POST
 
226
#define CONFIG_CMD_DIAG
 
227
#endif
 
228
 
 
229
/*
 
230
 * There is no IDE/PCMCIA hardware support on the board.
 
231
 */
 
232
#undef  CONFIG_IDE_PCMCIA
 
233
#undef  CONFIG_IDE_LED
 
234
#undef  CONFIG_IDE_RESET
 
235
 
 
236
/*
 
237
 * Enable the call to misc_init_r() for miscellaneous platform
 
238
 * dependent initialization.
 
239
 */
 
240
#define CONFIG_MISC_INIT_R
 
241
 
 
242
/*
 
243
 * Enable call to last_stage_init() so we can twiddle some LEDS :)
 
244
 */
 
245
#define CONFIG_LAST_STAGE_INIT
 
246
 
 
247
/*
 
248
 * Virtex2 FPGA configuration support
 
249
 */
 
250
#define CONFIG_FPGA_COUNT               1
 
251
#define CONFIG_FPGA
 
252
#define CONFIG_FPGA_XILINX
 
253
#define CONFIG_FPGA_VIRTEX2
 
254
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
 
255
 
 
256
/*
 
257
 * Verbose help from command monitor.
 
258
 */
 
259
#define CONFIG_SYS_LONGHELP
 
260
#if !defined(CONFIG_SC)
 
261
#define CONFIG_SYS_PROMPT                       "B2> "
 
262
#else
 
263
#define CONFIG_SYS_PROMPT                       "SC> "
 
264
#endif
 
265
 
 
266
 
 
267
/*
 
268
 * Use the "hush" command parser
 
269
 */
 
270
#define CONFIG_SYS_HUSH_PARSER
 
271
 
 
272
/*
 
273
 * Set buffer size for console I/O
 
274
 */
 
275
#if defined(CONFIG_CMD_KGDB)
 
276
#define CONFIG_SYS_CBSIZE                       1024
 
277
#else
 
278
#define CONFIG_SYS_CBSIZE                       256
 
279
#endif
 
280
 
 
281
/*
 
282
 * Print buffer size
 
283
 */
 
284
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
285
 
 
286
/*
 
287
 * Maximum number of arguments that a command can accept
 
288
 */
 
289
#define CONFIG_SYS_MAXARGS                      16
 
290
 
 
291
/*
 
292
 * Boot argument buffer size
 
293
 */
 
294
#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 
295
 
 
296
/*
 
297
 * Default memory test range
 
298
 */
 
299
#define CONFIG_SYS_MEMTEST_START        0x0100000
 
300
#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START  + (128 * 1024))
 
301
 
 
302
/*
 
303
 * Select the more full-featured memory test
 
304
 */
 
305
#define CONFIG_SYS_ALT_MEMTEST
 
306
 
 
307
/*
 
308
 * Default load address
 
309
 */
 
310
#define CONFIG_SYS_LOAD_ADDR            0x01000000
 
311
 
 
312
/*
 
313
 * Device memory map (after SDRAM remap to 0x0):
 
314
 *
 
315
 * CS           Device                          Base Addr       Size
 
316
 * ----------------------------------------------------
 
317
 * CS0*         Flash                           0x40000000      64 M
 
318
 * CS1*         SDRAM                           0x00000000      16 M
 
319
 * CS2*         Disk-On-Chip            0x50000000      32 K
 
320
 * CS3*         FPGA                            0x60000000      64 M
 
321
 * CS4*         SelectMap                       0x70000000      32 K
 
322
 * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 
323
 * CS6*         Unused
 
324
 * CS7*         Unused
 
325
 * IMMR         860T Registers          0xfff00000
 
326
 */
 
327
 
 
328
/*
 
329
 * Base addresses and block sizes
 
330
 */
 
331
#define CONFIG_SYS_IMMR                 0xFF000000
 
332
 
 
333
#define SDRAM_BASE                      0x00000000
 
334
#define SDRAM_SIZE                      (64 * 1024 * 1024)
 
335
 
 
336
#define FLASH_BASE                      0x40000000
 
337
#define FLASH_SIZE                      (16 * 1024 * 1024)
 
338
 
 
339
#define DOC_BASE                        0x50000000
 
340
#define DOC_SIZE                        (32 * 1024)
 
341
 
 
342
#define FPGA_BASE                       0x60000000
 
343
#define FPGA_SIZE                       (64 * 1024 * 1024)
 
344
 
 
345
#define SELECTMAP_BASE          0x70000000
 
346
#define SELECTMAP_SIZE          (32 * 1024)
 
347
 
 
348
#define M1553_BASE                      0x80000000
 
349
#define M1553_SIZE                      (64 * 1024)
 
350
 
 
351
/*
 
352
 * Definitions for initial stack pointer and data area (in DPRAM)
 
353
 */
 
354
#define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SYS_IMMR
 
355
#define CONFIG_SYS_INIT_RAM_SIZE                0x2F00  /* Size of used area in DPRAM           */
 
356
#define CONFIG_SYS_INIT_DATA_SIZE               64      /* # bytes reserved for initial data*/
 
357
#define CONFIG_SYS_GBL_DATA_OFFSET              (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 
358
#define CONFIG_SYS_INIT_SP_OFFSET               CONFIG_SYS_GBL_DATA_OFFSET
 
359
 
 
360
/*
 
361
 * Start addresses for the final memory configuration
 
362
 * (Set up by the startup code)
 
363
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 
364
 */
 
365
#define CONFIG_SYS_SDRAM_BASE                   SDRAM_BASE
 
366
 
 
367
/*
 
368
 * FLASH organization
 
369
 */
 
370
#define CONFIG_SYS_FLASH_BASE                   FLASH_BASE
 
371
#define CONFIG_SYS_FLASH_SIZE                   FLASH_SIZE
 
372
#define CONFIG_SYS_FLASH_SECT_SIZE              (128 * 1024)
 
373
#define CONFIG_SYS_MAX_FLASH_BANKS              1
 
374
#define CONFIG_SYS_MAX_FLASH_SECT               128
 
375
 
 
376
/*
 
377
 * The timeout values are for an entire chip and are in milliseconds.
 
378
 * Yes I know that the write timeout is huge.  Accroding to the
 
379
 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 
380
 * case VCC and temp after 100K programming cycles.  It works out
 
381
 * to 280 minutes (might as well be forever).
 
382
 */
 
383
#define CONFIG_SYS_FLASH_ERASE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 5000)
 
384
#define CONFIG_SYS_FLASH_WRITE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
 
385
 
 
386
/*
 
387
 * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 
388
 */
 
389
#define CONFIG_SYS_DIRECT_FLASH_TFTP
 
390
 
 
391
/*
 
392
 * Reserve memory for U-Boot.
 
393
 */
 
394
#define CONFIG_SYS_MAX_UBOOT_SECTS              4
 
395
#define CONFIG_SYS_MONITOR_LEN                  (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
 
396
#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 
397
 
 
398
/*
 
399
 * Select environment placement.  NOTE that u-boot.lds must
 
400
 * be edited if this is changed!
 
401
 */
 
402
#undef  CONFIG_ENV_IS_IN_FLASH
 
403
#define CONFIG_ENV_IS_IN_EEPROM
 
404
 
 
405
#if defined(CONFIG_ENV_IS_IN_EEPROM)
 
406
#define CONFIG_ENV_SIZE                 (2 * 1024)
 
407
#define CONFIG_ENV_OFFSET                       (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
 
408
#else
 
409
#define CONFIG_ENV_SIZE                 0x1000
 
410
#define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SIZE
 
411
 
 
412
/*
 
413
 * This ultimately gets passed right into the linker script, so we have to
 
414
 * use a number :(
 
415
 */
 
416
#define CONFIG_ENV_OFFSET                       0x060000
 
417
#endif
 
418
 
 
419
/*
 
420
 * Reserve memory for malloc()
 
421
 */
 
422
#define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
 
423
 
 
424
/*
 
425
 * For booting Linux, the board info and command line data
 
426
 * have to be in the first 8 MB of memory, since this is
 
427
 * the maximum mapped by the Linux kernel during initialization.
 
428
 */
 
429
#define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
 
430
 
 
431
/*
 
432
 * Cache Configuration
 
433
 */
 
434
#define CONFIG_SYS_CACHELINE_SIZE               16      /* For all MPC8xx CPUs                          */
 
435
#if defined(CONFIG_CMD_KGDB)
 
436
#define CONFIG_SYS_CACHELINE_SHIFT              4       /* log base 2 of above value            */
 
437
#endif
 
438
 
 
439
/*------------------------------------------------------------------------
 
440
 * SYPCR - System Protection Control                                                    UM 11-9
 
441
 * -----------------------------------------------------------------------
 
442
 * SYPCR can only be written once after reset!
 
443
 *
 
444
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 
445
 */
 
446
#if defined(CONFIG_WATCHDOG)
 
447
#define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 
448
                                          SYPCR_BMT     | \
 
449
                                          SYPCR_BME     | \
 
450
                                          SYPCR_SWF     | \
 
451
                                          SYPCR_SWE     | \
 
452
                                          SYPCR_SWRI    | \
 
453
                                          SYPCR_SWP               \
 
454
                                        )
 
455
#else
 
456
#define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 
457
                                          SYPCR_BMT     | \
 
458
                                          SYPCR_BME     | \
 
459
                                          SYPCR_SWF     | \
 
460
                                          SYPCR_SWP               \
 
461
                                        )
 
462
#endif
 
463
 
 
464
/*-----------------------------------------------------------------------
 
465
 * SIUMCR - SIU Module Configuration                                                    UM 11-6
 
466
 *-----------------------------------------------------------------------
 
467
 * Set debug pin mux, enable SPKROUT and GPLB5*.
 
468
 */
 
469
#define CONFIG_SYS_SIUMCR       ( SIUMCR_DBGC11 | \
 
470
                                          SIUMCR_DBPC11 | \
 
471
                                          SIUMCR_MLRC11 | \
 
472
                                          SIUMCR_GB5E     \
 
473
                                        )
 
474
 
 
475
/*-----------------------------------------------------------------------
 
476
 * TBSCR - Time Base Status and Control                                                 UM 11-26
 
477
 *-----------------------------------------------------------------------
 
478
 * Clear Reference Interrupt Status, Timebase freeze enabled
 
479
 */
 
480
#define CONFIG_SYS_TBSCR        ( TBSCR_REFA | \
 
481
                                          TBSCR_REFB | \
 
482
                                          TBSCR_TBF        \
 
483
                                        )
 
484
 
 
485
/*-----------------------------------------------------------------------
 
486
 * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 
487
 *-----------------------------------------------------------------------
 
488
 */
 
489
#define CONFIG_SYS_RTCSC        ( RTCSC_SEC     | \
 
490
                                          RTCSC_ALR | \
 
491
                                          RTCSC_RTF | \
 
492
                                          RTCSC_RTE       \
 
493
                                        )
 
494
 
 
495
/*-----------------------------------------------------------------------
 
496
 * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 
497
 *-----------------------------------------------------------------------
 
498
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 
499
 */
 
500
#define CONFIG_SYS_PISCR        ( PISCR_PS              | \
 
501
                                          PISCR_PITF      \
 
502
                                        )
 
503
 
 
504
/*-----------------------------------------------------------------------
 
505
 * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 
506
 *-----------------------------------------------------------------------
 
507
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 
508
 * interrupt status bit. Set MF for 1:2:1 mode.
 
509
 */
 
510
#define CONFIG_SYS_PLPRCR       ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 
511
                                          PLPRCR_SPLSS  | \
 
512
                                          PLPRCR_TEXPS  | \
 
513
                                          PLPRCR_TMIST    \
 
514
                                        )
 
515
 
 
516
/*-----------------------------------------------------------------------
 
517
 * SCCR - System Clock and reset Control Register                               UM 15-27
 
518
 *-----------------------------------------------------------------------
 
519
 * Set clock output, timebase and RTC source and divider,
 
520
 * power management and some other internal clocks
 
521
 */
 
522
#define SCCR_MASK   SCCR_EBDF11
 
523
 
 
524
#if !defined(CONFIG_SC)
 
525
#define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 
526
                                          SCCR_COM00            |       /* full strength CLKOUT */ \
 
527
                                          SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 
528
                                          SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 
529
                                          SCCR_DFNL000          | \
 
530
                                          SCCR_DFNH000            \
 
531
                                        )
 
532
#else
 
533
#define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 
534
                                          SCCR_COM00            |       /* full strength CLKOUT */ \
 
535
                                          SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 
536
                                          SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 
537
                                          SCCR_DFNL000          | \
 
538
                                          SCCR_DFNH000          | \
 
539
                                          SCCR_RTDIV            | \
 
540
                                          SCCR_RTSEL              \
 
541
                                        )
 
542
#endif
 
543
 
 
544
/*-----------------------------------------------------------------------
 
545
 * DER - Debug Enable Register                                                                  UM 37-46
 
546
 *-----------------------------------------------------------------------
 
547
 * Mask all events that can cause entry into debug mode
 
548
 */
 
549
#define CONFIG_SYS_DER                          0
 
550
 
 
551
/*
 
552
 * Initialize Memory Controller:
 
553
 *
 
554
 * BR0 and OR0 (FLASH memory)
 
555
 */
 
556
#define FLASH_BASE0_PRELIM      FLASH_BASE
 
557
 
 
558
/*
 
559
 * Flash address mask
 
560
 */
 
561
#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
 
562
 
 
563
/*
 
564
 * FLASH timing:
 
565
 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 
566
 */
 
567
#define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM   | \
 
568
                                                          OR_ACS_DIV2   | \
 
569
                                                          OR_BI                 | \
 
570
                                                          OR_SCY_2_CLK  | \
 
571
                                                          OR_TRLX               | \
 
572
                                                          OR_EHTR                 \
 
573
                                                        )
 
574
 
 
575
#define CONFIG_SYS_OR0_PRELIM   ( CONFIG_SYS_PRELIM_OR_AM               | \
 
576
                                                  CONFIG_SYS_OR_TIMING_FLASH      \
 
577
                                                )
 
578
 
 
579
#define CONFIG_SYS_BR0_PRELIM   ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 
580
                                                  BR_MS_GPCM                                            | \
 
581
                                                  BR_PS_8                                                       | \
 
582
                                                  BR_V                                                            \
 
583
                                                )
 
584
 
 
585
/*
 
586
 * SDRAM configuration
 
587
 */
 
588
#define CONFIG_SYS_OR1_AM       0xfc000000
 
589
#define CONFIG_SYS_OR1          ( (CONFIG_SYS_OR1_AM & OR_AM_MSK)       | \
 
590
                                          OR_CSNT_SAM                             \
 
591
                                        )
 
592
 
 
593
#define CONFIG_SYS_BR1          ( (SDRAM_BASE & BR_BA_MSK)      | \
 
594
                                          BR_MS_UPMA                            | \
 
595
                                          BR_PS_32                                      | \
 
596
                                          BR_V                                            \
 
597
                                        )
 
598
 
 
599
/*
 
600
 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 
601
 * of 256 MBit SDRAM
 
602
 */
 
603
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
 
604
 
 
605
/*
 
606
 * Periodic timer for refresh @ 33 MHz system clock
 
607
 */
 
608
#define CONFIG_SYS_MAMR_PTA     64
 
609
 
 
610
/*
 
611
 * MAMR settings for SDRAM
 
612
 */
 
613
#define CONFIG_SYS_MAMR_8COL    ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)       | \
 
614
                                                  MAMR_PTAE                             | \
 
615
                                                  MAMR_AMA_TYPE_1                       | \
 
616
                                                  MAMR_DSA_1_CYCL                       | \
 
617
                                                  MAMR_G0CLA_A10                        | \
 
618
                                                  MAMR_RLFA_1X                          | \
 
619
                                                  MAMR_WLFA_1X                          | \
 
620
                                                  MAMR_TLFA_4X                            \
 
621
                                                )
 
622
 
 
623
/*
 
624
 * CS2* configuration for Disk On Chip:
 
625
 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 
626
 * no burst.
 
627
 */
 
628
#define CONFIG_SYS_OR2_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 
629
                                                  OR_CSNT_SAM                           | \
 
630
                                                  OR_ACS_DIV2                           | \
 
631
                                                  OR_BI                                         | \
 
632
                                                  OR_SCY_2_CLK                          | \
 
633
                                                  OR_TRLX                                       | \
 
634
                                                  OR_EHTR                                         \
 
635
                                                )
 
636
 
 
637
#define CONFIG_SYS_BR2_PRELIM   ( (DOC_BASE & BR_BA_MSK)        | \
 
638
                                                  BR_PS_8                                       | \
 
639
                                                  BR_MS_GPCM                            | \
 
640
                                                  BR_V                                            \
 
641
                                                )
 
642
 
 
643
/*
 
644
 * CS3* configuration for FPGA:
 
645
 * 33 MHz bus with SCY=15, no burst.
 
646
 * The FPGA uses TA and TEA to terminate bus cycles, but we
 
647
 * clear SETA and set the cycle length to a large number so that
 
648
 * the cycle will still complete even if there is a configuration
 
649
 * error that prevents TA from asserting on FPGA accesss.
 
650
 */
 
651
#define CONFIG_SYS_OR3_PRELIM   ( (0xfc000000 & OR_AM_MSK)  | \
 
652
                                                  OR_SCY_15_CLK                         | \
 
653
                                                  OR_BI                                   \
 
654
                                                )
 
655
 
 
656
#define CONFIG_SYS_BR3_PRELIM   ( (FPGA_BASE & BR_BA_MSK)       | \
 
657
                                                  BR_PS_32                                      | \
 
658
                                                  BR_MS_GPCM                            | \
 
659
                                                  BR_V                                            \
 
660
                                                )
 
661
/*
 
662
 * CS4* configuration for FPGA SelectMap configuration interface.
 
663
 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 
664
 * of GCLK1_50
 
665
 */
 
666
#define CONFIG_SYS_OR4_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 
667
                                                  OR_G5LS                                               | \
 
668
                                                  OR_BI                                                   \
 
669
                                                )
 
670
 
 
671
#define CONFIG_SYS_BR4_PRELIM   ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 
672
                                                  BR_PS_8                                               | \
 
673
                                                  BR_MS_UPMB                                    | \
 
674
                                                  BR_V                                                    \
 
675
                                                )
 
676
 
 
677
/*
 
678
 * CS5* configuration for Mil-Std 1553 databus interface.
 
679
 * 33 MHz bus, GPCM, no burst.
 
680
 * The 1553 interface  uses TA and TEA to terminate bus cycles,
 
681
 * but we clear SETA and set the cycle length to a large number so that
 
682
 * the cycle will still complete even if there is a configuration
 
683
 * error that prevents TA from asserting on FPGA accesss.
 
684
 */
 
685
#define CONFIG_SYS_OR5_PRELIM   ( (0xffff0000 & OR_AM_MSK)  | \
 
686
                                                  OR_SCY_15_CLK                         | \
 
687
                                                  OR_EHTR                                       | \
 
688
                                                  OR_TRLX                                       | \
 
689
                                                  OR_CSNT_SAM                           | \
 
690
                                                  OR_BI                                           \
 
691
                                                )
 
692
 
 
693
#define CONFIG_SYS_BR5_PRELIM   ( (M1553_BASE & BR_BA_MSK)      | \
 
694
                                                  BR_PS_16                                      | \
 
695
                                                  BR_MS_GPCM                            | \
 
696
                                                  BR_V                                            \
 
697
                                                )
 
698
 
 
699
/*
 
700
 * FEC interrupt assignment
 
701
 */
 
702
#define FEC_INTERRUPT   SIU_LEVEL1
 
703
 
 
704
/*
 
705
 * Sanity checks
 
706
 */
 
707
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 
708
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 
709
#endif
 
710
 
 
711
#endif  /* __CONFIG_GEN860T_H */