2
* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* SPDX-License-Identifier: GPL-2.0+
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* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
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* U-Boot port on NetTA4 board
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#ifdef CONFIG_HW_WATCHDOG
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int fec8xx_miiphy_read(char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value);
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int fec8xx_miiphy_write(char *devname, unsigned char addr,
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unsigned char reg, unsigned short value);
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/****************************************************************/
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/* some sane bit macros */
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#define _BD(_b) (1U << (31-(_b)))
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#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
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#define _BW(_b) (1U << (15-(_b)))
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#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
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#define _BB(_b) (1U << (7-(_b)))
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#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
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#define _B(_b) _BD(_b)
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#define _BR(_l, _h) _BDR(_l, _h)
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/****************************************************************/
45
* Check Board Identity:
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printf ("Intracom NETTA"
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#if defined(CONFIG_NETTA_ISDN)
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#if defined(CONFIG_NETTA_6412)
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/****************************************************************/
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#define _NOT_USED_ 0xFFFFFFFF
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/****************************************************************/
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#define CS_0000 0x00000000
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#define CS_0001 0x10000000
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#define CS_0010 0x20000000
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#define CS_0011 0x30000000
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#define CS_0100 0x40000000
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#define CS_0101 0x50000000
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#define CS_0110 0x60000000
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#define CS_0111 0x70000000
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#define CS_1000 0x80000000
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#define CS_1001 0x90000000
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#define CS_1010 0xA0000000
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#define CS_1011 0xB0000000
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#define CS_1100 0xC0000000
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#define CS_1101 0xD0000000
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#define CS_1110 0xE0000000
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#define CS_1111 0xF0000000
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#define BS_0000 0x00000000
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#define BS_0001 0x01000000
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#define BS_0010 0x02000000
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#define BS_0011 0x03000000
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#define BS_0100 0x04000000
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#define BS_0101 0x05000000
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#define BS_0110 0x06000000
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#define BS_0111 0x07000000
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#define BS_1000 0x08000000
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#define BS_1001 0x09000000
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#define BS_1010 0x0A000000
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#define BS_1011 0x0B000000
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#define BS_1100 0x0C000000
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#define BS_1101 0x0D000000
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#define BS_1110 0x0E000000
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#define BS_1111 0x0F000000
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#define A10_AAAA 0x00000000
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#define A10_AAA0 0x00200000
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#define A10_AAA1 0x00300000
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#define A10_000A 0x00800000
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#define A10_0000 0x00A00000
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#define A10_0001 0x00B00000
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#define A10_111A 0x00C00000
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#define A10_1110 0x00E00000
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#define A10_1111 0x00F00000
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#define RAS_0000 0x00000000
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#define RAS_0001 0x00040000
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#define RAS_1110 0x00080000
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#define RAS_1111 0x000C0000
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#define CAS_0000 0x00000000
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#define CAS_0001 0x00010000
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#define CAS_1110 0x00020000
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#define CAS_1111 0x00030000
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#define WE_0000 0x00000000
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#define WE_0001 0x00004000
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#define WE_1110 0x00008000
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#define WE_1111 0x0000C000
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#define GPL4_0000 0x00000000
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#define GPL4_0001 0x00001000
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#define GPL4_1110 0x00002000
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#define GPL4_1111 0x00003000
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#define GPL5_0000 0x00000000
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#define GPL5_0001 0x00000400
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#define GPL5_1110 0x00000800
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#define GPL5_1111 0x00000C00
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#define LOOP 0x00000080
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#define EXEN 0x00000040
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#define AMX_COL 0x00000000
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#define AMX_ROW 0x00000020
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#define AMX_MAR 0x00000030
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#define NA 0x00000008
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#define UTA 0x00000004
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#define TODT 0x00000002
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#define LAST 0x00000001
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/* #define CAS_LATENCY 3 */
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#define CAS_LATENCY 2
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const uint sdram_table[0x40] = {
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
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CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
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CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
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_NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
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CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
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CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
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_NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
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CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
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CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_,
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
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CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
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CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
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/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
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/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
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#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
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#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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void check_ram(unsigned int addr, unsigned int size)
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unsigned int i, j, v, vv;
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volatile unsigned int *p;
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p = (unsigned int *)addr;
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pv = (unsigned int)p;
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for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
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p = (unsigned int *)addr;
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for (i = 0; i < size / sizeof(unsigned int); i++) {
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printf("%p: read %08x instead of %08x\n", p, vv, v);
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for (j = 0; j < 5; j++) {
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case 0: v = 0x00000000; break;
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case 1: v = 0xffffffff; break;
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case 2: v = 0x55555555; break;
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case 3: v = 0xaaaaaaaa; break;
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default:v = 0xdeadbeef; break;
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p = (unsigned int *)addr;
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for (i = 0; i < size / sizeof(unsigned int); i++) {
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printf("%p: read %08x instead of %08x\n", p, vv, v);
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phys_size_t initdram(int board_type)
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
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* Preliminary prescaler for refresh
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memctl->memc_mptpr = MPTPR_PTP_DIV8;
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memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
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* Map controller bank 3 to the SDRAM bank at preliminary address.
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memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
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memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
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memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
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/* perform SDRAM initialisation sequence */
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memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
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memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
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memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
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memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
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*(volatile u32 *)0 = d1;
368
d2 = *(volatile u32 *)0;
370
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
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*(volatile u32 *)0 = d1;
376
d2 = *(volatile u32 *)0;
378
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
383
size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
387
check_ram(( 0 << 20), (2 << 20));
388
printf("check 16\n");
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check_ram((16 << 20), (2 << 20));
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printf("check 32\n");
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check_ram((32 << 20), (2 << 20));
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printf("check 48\n");
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check_ram((48 << 20), (2 << 20));
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printf("SIZE is zero: LOOP on 0\n");
399
*(volatile u32 *)0 = 0;
400
(void)*(volatile u32 *)0;
407
/* ------------------------------------------------------------------------- */
409
int misc_init_r(void)
414
void reset_phys(void)
419
/* reset the damn phys */
422
for (phyno = 0; phyno < 32; ++phyno) {
423
fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
426
fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
428
fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
429
BMCR_RESET | BMCR_ANENABLE);
434
extern int board_dsp_reset(void);
436
int last_stage_init(void)
441
r = board_dsp_reset();
443
printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
447
/* ------------------------------------------------------------------------- */
449
/* GP = general purpose, SP = special purpose (on chip peripheral) */
451
/* bits that can have a special purpose or can be configured as inputs/outputs */
452
#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11))
453
#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15))
454
#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5))
456
#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15))
457
#define PA_SP_DIRVAL 0
459
#define PB_GP_INMASK (_B(28) | _B(31))
460
#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
461
#define PB_SP_MASK (_BR(22, 25))
463
#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
464
#define PB_SP_DIRVAL 0
466
#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
467
#define PC_GP_OUTMASK (_BW(6) | _BW(12))
468
#define PC_SP_MASK (_BW(4) | _BW(8))
470
#define PC_INTVAL _BW(7)
471
#define PC_GP_OUTVAL (_BW(6) | _BW(12))
472
#define PC_SP_DIRVAL 0
474
#define PD_GP_INMASK 0
475
#define PD_GP_OUTMASK _BWR(3, 15)
478
#if defined(CONFIG_NETTA_6412)
480
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
484
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11))
488
#define PD_SP_DIRVAL 0
490
int board_early_init_f(void)
492
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
493
volatile iop8xx_t *ioport = &immap->im_ioport;
494
volatile cpm8xx_t *cpm = &immap->im_cpm;
495
volatile memctl8xx_t *memctl = &immap->im_memctl;
497
/* CS1: NAND chip select */
498
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
499
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
500
#if !defined(CONFIG_NETTA_6412)
502
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
503
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
506
memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
507
memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
509
/* CS4: External register chip select */
510
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
511
memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
513
/* CS5: dummy for accurate delay */
514
memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
515
memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
517
ioport->iop_padat = PA_GP_OUTVAL;
518
ioport->iop_paodr = PA_ODR_VAL;
519
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
520
ioport->iop_papar = PA_SP_MASK;
522
cpm->cp_pbdat = PB_GP_OUTVAL;
523
cpm->cp_pbodr = PB_ODR_VAL;
524
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
525
cpm->cp_pbpar = PB_SP_MASK;
527
ioport->iop_pcdat = PC_GP_OUTVAL;
528
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
529
ioport->iop_pcso = PC_SOVAL;
530
ioport->iop_pcint = PC_INTVAL;
531
ioport->iop_pcpar = PC_SP_MASK;
533
ioport->iop_pddat = PD_GP_OUTVAL;
534
ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
535
ioport->iop_pdpar = PD_SP_MASK;
537
/* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */
542
#if defined(CONFIG_CMD_PCMCIA)
544
int pcmcia_init(void)
551
#ifdef CONFIG_HW_WATCHDOG
553
void hw_watchdog_reset(void)
555
/* XXX add here the really funky stuff */