← Back to branch summary

~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

« back to all changes in this revision

Viewing changes to roms/u-boot/arch/powerpc/include/asm/fsl_law.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

Show diffs side-by-side

added added

removed removed

Lines of Context:
roms/u-boot/arch/powerpc/include/asm/fsl_law.h
 
1
/*
 
2
 * Copyright 2008-2011 Freescale Semiconductor, Inc.
 
3
 *
 
4
 * This program is free software; you can redistribute it and/or
 
5
 * modify it under the terms of the GNU General Public License
 
6
 * Version 2 as published by the Free Software Foundation.
 
7
 */
 
8
 
 
9
#ifndef _FSL_LAW_H_
 
10
#define _FSL_LAW_H_
 
11
 
 
12
#include <asm/io.h>
 
13
 
 
14
#define LAW_EN  0x80000000
 
15
 
 
16
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
 
17
        { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
 
18
 
 
19
#define SET_LAW(a, sz, trgt) \
 
20
        { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
 
21
 
 
22
enum law_size {
 
23
        LAW_SIZE_4K = 0xb,
 
24
        LAW_SIZE_8K,
 
25
        LAW_SIZE_16K,
 
26
        LAW_SIZE_32K,
 
27
        LAW_SIZE_64K,
 
28
        LAW_SIZE_128K,
 
29
        LAW_SIZE_256K,
 
30
        LAW_SIZE_512K,
 
31
        LAW_SIZE_1M,
 
32
        LAW_SIZE_2M,
 
33
        LAW_SIZE_4M,
 
34
        LAW_SIZE_8M,
 
35
        LAW_SIZE_16M,
 
36
        LAW_SIZE_32M,
 
37
        LAW_SIZE_64M,
 
38
        LAW_SIZE_128M,
 
39
        LAW_SIZE_256M,
 
40
        LAW_SIZE_512M,
 
41
        LAW_SIZE_1G,
 
42
        LAW_SIZE_2G,
 
43
        LAW_SIZE_4G,
 
44
        LAW_SIZE_8G,
 
45
        LAW_SIZE_16G,
 
46
        LAW_SIZE_32G,
 
47
};
 
48
 
 
49
#define law_size_bits(sz)       (__ilog2_u64(sz) - 1)
 
50
#define lawar_size(x)   (1ULL << ((x & 0x3f) + 1))
 
51
 
 
52
#ifdef CONFIG_FSL_CORENET
 
53
enum law_trgt_if {
 
54
        LAW_TRGT_IF_PCIE_1 = 0x00,
 
55
        LAW_TRGT_IF_PCIE_2 = 0x01,
 
56
        LAW_TRGT_IF_PCIE_3 = 0x02,
 
57
        LAW_TRGT_IF_PCIE_4 = 0x03,
 
58
        LAW_TRGT_IF_RIO_1 = 0x08,
 
59
        LAW_TRGT_IF_RIO_2 = 0x09,
 
60
 
 
61
        LAW_TRGT_IF_DDR_1 = 0x10,
 
62
        LAW_TRGT_IF_DDR_2 = 0x11,       /* 2nd controller */
 
63
        LAW_TRGT_IF_DDR_3 = 0x12,
 
64
        LAW_TRGT_IF_DDR_4 = 0x13,
 
65
        LAW_TRGT_IF_DDR_INTRLV = 0x14,
 
66
        LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
 
67
        LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
 
68
        LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
 
69
        LAW_TRGT_IF_BMAN = 0x18,
 
70
        LAW_TRGT_IF_DCSR = 0x1d,
 
71
        LAW_TRGT_IF_LBC = 0x1f,
 
72
        LAW_TRGT_IF_QMAN = 0x3c,
 
73
 
 
74
        LAW_TRGT_IF_MAPLE = 0x50,
 
75
};
 
76
#define LAW_TRGT_IF_DDR         LAW_TRGT_IF_DDR_1
 
77
#define LAW_TRGT_IF_IFC         LAW_TRGT_IF_LBC
 
78
#else
 
79
enum law_trgt_if {
 
80
        LAW_TRGT_IF_PCI = 0x00,
 
81
        LAW_TRGT_IF_PCI_2 = 0x01,
 
82
#ifndef CONFIG_MPC8641
 
83
        LAW_TRGT_IF_PCIE_1 = 0x02,
 
84
#endif
 
85
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 
86
        LAW_TRGT_IF_OCN_DSP = 0x03,
 
87
#else
 
88
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
 
89
        LAW_TRGT_IF_PCIE_3 = 0x03,
 
90
#endif
 
91
#endif
 
92
        LAW_TRGT_IF_LBC = 0x04,
 
93
        LAW_TRGT_IF_CCSR = 0x08,
 
94
        LAW_TRGT_IF_DSP_CCSR = 0x09,
 
95
        LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
 
96
        LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 
97
        LAW_TRGT_IF_RIO = 0x0c,
 
98
#if defined(CONFIG_BSC9132)
 
99
        LAW_TRGT_IF_CLASS_DSP = 0x0d,
 
100
#else
 
101
        LAW_TRGT_IF_RIO_2 = 0x0d,
 
102
#endif
 
103
        LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
 
104
        LAW_TRGT_IF_DDR = 0x0f,
 
105
        LAW_TRGT_IF_DDR_2 = 0x16,       /* 2nd controller */
 
106
        /* place holder for 3-way and 4-way interleaving */
 
107
        LAW_TRGT_IF_DDR_3,
 
108
        LAW_TRGT_IF_DDR_4,
 
109
        LAW_TRGT_IF_DDR_INTLV_34,
 
110
        LAW_TRGT_IF_DDR_INTLV_123,
 
111
        LAW_TRGT_IF_DDR_INTLV_1234,
 
112
};
 
113
#define LAW_TRGT_IF_DDR_1       LAW_TRGT_IF_DDR
 
114
#define LAW_TRGT_IF_PCI_1       LAW_TRGT_IF_PCI
 
115
#define LAW_TRGT_IF_PCIX        LAW_TRGT_IF_PCI
 
116
#define LAW_TRGT_IF_PCIE_2      LAW_TRGT_IF_PCI_2
 
117
#define LAW_TRGT_IF_RIO_1       LAW_TRGT_IF_RIO
 
118
#define LAW_TRGT_IF_IFC         LAW_TRGT_IF_LBC
 
119
 
 
120
#ifdef CONFIG_MPC8641
 
121
#define LAW_TRGT_IF_PCIE_1      LAW_TRGT_IF_PCI
 
122
#endif
 
123
 
 
124
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
 
125
#define LAW_TRGT_IF_PCIE_3      LAW_TRGT_IF_PCI
 
126
#endif
 
127
#endif /* CONFIG_FSL_CORENET */
 
128
 
 
129
struct law_entry {
 
130
        int index;
 
131
        phys_addr_t addr;
 
132
        enum law_size size;
 
133
        enum law_trgt_if trgt_id;
 
134
};
 
135
 
 
136
extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
 
137
extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
 
138
extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
 
139
extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
 
140
extern struct law_entry find_law(phys_addr_t addr);
 
141
extern void disable_law(u8 idx);
 
142
extern void init_laws(void);
 
143
extern void print_laws(void);
 
144
 
 
145
/* define in board code */
 
146
extern struct law_entry law_table[];
 
147
extern int num_law_entries;
 
148
#endif