3
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
5
* This file is based on similar values for other boards found in other
6
* U-Boot config files, and some that I found in the EP8260 manual.
8
* SPDX-License-Identifier: GPL-2.0+
12
* board/config.h - configuration options, board specific
16
* - 32M Local Bus SDRAM
17
* - 16M Flash (4 x AM29DL323DB90WDI)
18
* - 128k NVRAM with RTC
20
* "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
21
* - 300MHz/133MHz/66MHz
23
* - 32M Local Bus SDRAM
25
* - 128k NVRAM with RTC
31
/* Define this to enable support the EP8260 H2 version */
32
#define CONFIG_SYS_EP8260_H2 1
33
/* #undef CONFIG_SYS_EP8260_H2 */
35
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
37
#define CONFIG_CPM2 1 /* Has a CPM2 */
39
/* What is the oscillator's (UX2) frequency in Hz? */
40
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
42
/*-----------------------------------------------------------------------
43
* MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
44
*-----------------------------------------------------------------------
45
* What should MODCK_H be? It is dependent on the oscillator
46
* frequency, MODCK[1-3], and desired CPM and core frequencies.
47
* Here are some example values (all frequencies are in MHz):
49
* MODCK_H MODCK[1-3] Osc CPM Core
50
* ------- ---------- --- --- ----
59
* 0x5 0x7 66 133 200 *
64
#ifdef CONFIG_SYS_EP8260_H2
65
#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
67
#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
70
/* Define this if you want to boot from 0x00000100. If you don't define
71
* this, you will need to program the bootloader to 0xfff00000, and
72
* get the hardware reset config words at 0xfe000000. The simplest
73
* way to do that is to program the bootloader at both addresses.
74
* It is suggested that you just let U-Boot live at 0x00000000.
76
/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */
77
/* #undef CONFIG_SYS_SBC_BOOT_LOW */
79
/* The reset command will not work as expected if the reset address does
80
* not point to the correct address.
83
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
85
/* What should the base address of the main FLASH be and how big is
86
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
87
* The main FLASH is whichever is connected to *CS0. U-Boot expects
88
* this to be the SIMM.
90
#ifdef CONFIG_SYS_EP8260_H2
91
#define CONFIG_SYS_FLASH0_BASE 0xFE000000
92
#define CONFIG_SYS_FLASH0_SIZE 32
94
#define CONFIG_SYS_FLASH0_BASE 0xFF000000
95
#define CONFIG_SYS_FLASH0_SIZE 16
98
/* What should the base address of the secondary FLASH be and how big
99
* is it (in Mbytes)? The secondary FLASH is whichever is connected
100
* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
101
* want it enabled, don't define these constants.
103
#define CONFIG_SYS_FLASH1_BASE 0
104
#define CONFIG_SYS_FLASH1_SIZE 0
105
#undef CONFIG_SYS_FLASH1_BASE
106
#undef CONFIG_SYS_FLASH1_SIZE
108
/* What should be the base address of SDRAM DIMM (60x bus) and how big is
111
#define CONFIG_SYS_SDRAM0_BASE 0x00000000
112
#define CONFIG_SYS_SDRAM0_SIZE 64
114
/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
115
* local bus (8260 local bus is NOT cacheable!)
117
/* #define CONFIG_SYS_LSDRAM */
118
#undef CONFIG_SYS_LSDRAM
120
#ifdef CONFIG_SYS_LSDRAM
121
/* What should be the base address of SDRAM DIMM (local bus) and how big is
124
#define CONFIG_SYS_SDRAM1_BASE 0x04000000
125
#define CONFIG_SYS_SDRAM1_SIZE 32
127
#define CONFIG_SYS_SDRAM1_BASE 0
128
#define CONFIG_SYS_SDRAM1_SIZE 0
129
#undef CONFIG_SYS_SDRAM1_BASE
130
#undef CONFIG_SYS_SDRAM1_SIZE
131
#endif /* CONFIG_SYS_LSDRAM */
133
/* What should be the base address of NVRAM and how big is
136
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
137
#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
139
/* The RTC is a Dallas DS1556
141
#define CONFIG_RTC_DS1556
143
/* What should be the base address of the LEDs and switch S0?
144
* If you don't want them enabled, don't define this.
146
#define CONFIG_SYS_LED_BASE 0x00000000
147
#undef CONFIG_SYS_LED_BASE
150
* select serial console configuration
152
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
153
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
156
* if CONFIG_CONS_NONE is defined, then the serial console routines must
159
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
160
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
161
#undef CONFIG_CONS_NONE /* define if console on neither */
162
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
165
* select ethernet configuration
167
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
168
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
171
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
172
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
174
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
175
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
176
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
177
#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
179
#if ( CONFIG_ETHER_INDEX == 3 )
184
* - RAM for BD/Buffers is on the local Bus (see 28-13)
185
* - Enable Half Duplex in FSMR
187
# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
188
# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
191
* - RAM for BD/Buffers is on the local Bus (see 28-13)
193
#ifdef CONFIG_SYS_LSDRAM
194
#define CONFIG_SYS_CPMFCR_RAMTYPE 3
195
#else /* CONFIG_SYS_LSDRAM */
196
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
197
#endif /* CONFIG_SYS_LSDRAM */
199
/* - Enable Half Duplex in FSMR */
200
/* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
201
# define CONFIG_SYS_FCC_PSMR 0
203
#else /* CONFIG_ETHER_INDEX */
204
# error "on EP8260 ethernet must be FCC3"
205
#endif /* CONFIG_ETHER_INDEX */
208
* select i2c support configuration
210
* Supported configurations are {none, software, hardware} drivers.
211
* If the software driver is chosen, there are some additional
212
* configuration items that the driver uses to drive the port pins.
214
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
216
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
217
#define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */
220
* Software (bit-bang) I2C driver configuration
222
#ifdef CONFIG_SYS_I2C_SOFT
223
#define CONFIG_SYS_I2C
224
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
225
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
226
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
227
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
228
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
229
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
230
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
231
else iop->pdat &= ~0x00010000
232
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
233
else iop->pdat &= ~0x00020000
234
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
235
#endif /* CONFIG_SYS_I2C_SOFT */
237
/* #define CONFIG_RTC_DS174x */
239
/* Define this to reserve an entire FLASH sector (256 KB) for
240
* environment variables. Otherwise, the environment will be
241
* put in the same sector as U-Boot, and changing variables
242
* will erase U-Boot temporarily
244
#define CONFIG_ENV_IN_OWN_SECT
246
/* Define to allow the user to overwrite serial and ethaddr */
247
#define CONFIG_ENV_OVERWRITE
249
/* What should the console's baud rate be? */
250
#ifdef CONFIG_SYS_EP8260_H2
251
#define CONFIG_BAUDRATE 9600
253
#define CONFIG_BAUDRATE 115200
256
/* Ethernet MAC address */
257
#define CONFIG_ETHADDR 00:10:EC:00:30:8C
259
#define CONFIG_IPADDR 192.168.254.130
260
#define CONFIG_SERVERIP 192.168.254.49
262
/* Set to a positive value to delay for running BOOTCOMMAND */
263
#define CONFIG_BOOTDELAY -1
265
/* undef this to save memory */
266
#define CONFIG_SYS_LONGHELP
268
/* Monitor Command Prompt */
270
/* Define this variable to enable the "hush" shell (from
271
Busybox) as command line interpreter, thus enabling
272
powerful command line syntax like
273
if...then...else...fi conditionals or `&&' and '||'
274
constructs ("shell scripts").
275
If undefined, you get the old, much simpler behaviour
276
with a somewhat smapper memory footprint.
278
#define CONFIG_SYS_HUSH_PARSER
284
#define CONFIG_BOOTP_BOOTFILESIZE
285
#define CONFIG_BOOTP_BOOTPATH
286
#define CONFIG_BOOTP_GATEWAY
287
#define CONFIG_BOOTP_HOSTNAME
291
* Command line configuration.
293
#include <config_cmd_default.h>
295
#define CONFIG_CMD_ASKENV
296
#define CONFIG_CMD_BEDBUG
297
#define CONFIG_CMD_CACHE
298
#define CONFIG_CMD_CDP
299
#define CONFIG_CMD_DATE
300
#define CONFIG_CMD_DIAG
301
#define CONFIG_CMD_ELF
302
#define CONFIG_CMD_FAT
303
#define CONFIG_CMD_I2C
304
#define CONFIG_CMD_IMMAP
305
#define CONFIG_CMD_IRQ
306
#define CONFIG_CMD_PING
307
#define CONFIG_CMD_PORTIO
308
#define CONFIG_CMD_REGINFO
309
#define CONFIG_CMD_SAVES
310
#define CONFIG_CMD_SDRAM
311
#define CONFIG_CMD_SNTP
313
#undef CONFIG_CMD_XIMG
315
/* Where do the internal registers live? */
316
#define CONFIG_SYS_IMMR 0xF0000000
317
#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
319
/* Where do the on board registers (CS4) live? */
320
#define CONFIG_SYS_REGS_BASE 0xFA000000
322
/*****************************************************************************
324
* You should not have to modify any of the following settings
326
*****************************************************************************/
328
#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
330
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
333
* Miscellaneous configurable options
335
#if defined(CONFIG_CMD_KGDB)
336
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
338
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
341
/* Print Buffer Size */
342
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
344
#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
346
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
348
#ifdef CONFIG_SYS_LSDRAM
349
#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
350
#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
352
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
353
#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
354
#endif /* CONFIG_SYS_LSDRAM */
356
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
358
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
361
* Low Level Configuration Settings
362
* (address mappings, register initial values, etc.)
363
* You should know what you are doing if you make changes here.
366
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
367
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
369
/*-----------------------------------------------------------------------
370
* Hard Reset Configuration Words
373
#if defined(CONFIG_SYS_SBC_BOOT_LOW)
374
# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
376
# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000)
377
#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
379
#ifdef CONFIG_SYS_EP8260_H2
380
/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
381
#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
382
((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\
383
((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
385
#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\
387
CONFIG_SYS_SBC_HRCW_IMMR |\
390
CONFIG_SYS_SBC_MODCK_H |\
391
CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
393
#define CONFIG_SYS_HRCW_MASTER 0x10400245
397
#define CONFIG_SYS_HRCW_SLAVE1 0
398
#define CONFIG_SYS_HRCW_SLAVE2 0
399
#define CONFIG_SYS_HRCW_SLAVE3 0
400
#define CONFIG_SYS_HRCW_SLAVE4 0
401
#define CONFIG_SYS_HRCW_SLAVE5 0
402
#define CONFIG_SYS_HRCW_SLAVE6 0
403
#define CONFIG_SYS_HRCW_SLAVE7 0
405
/*-----------------------------------------------------------------------
406
* Definitions for initial stack pointer and data area (in DPRAM)
408
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
409
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
410
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
411
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
413
/*-----------------------------------------------------------------------
414
* Start addresses for the final memory configuration
415
* (Set up by the startup code)
416
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
417
* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
419
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
422
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
423
# define CONFIG_SYS_RAMBOOT
426
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
427
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
430
* For booting Linux, the board info and command line data
431
* have to be in the first 8 MB of memory, since this is
432
* the maximum mapped by the Linux kernel during initialization.
434
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
436
/*-----------------------------------------------------------------------
437
* FLASH and environment organization
439
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
440
#ifdef CONFIG_SYS_EP8260_H2
441
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
443
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
446
#ifdef CONFIG_SYS_EP8260_H2
447
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */
448
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
450
#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
451
#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
454
#ifndef CONFIG_SYS_RAMBOOT
455
# define CONFIG_ENV_IS_IN_FLASH 1
457
# ifdef CONFIG_ENV_IN_OWN_SECT
458
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
459
# define CONFIG_ENV_SECT_SIZE 0x40000
461
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
462
# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
463
# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
464
# endif /* CONFIG_ENV_IN_OWN_SECT */
466
# define CONFIG_ENV_IS_IN_NVRAM 1
467
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
468
# define CONFIG_ENV_SIZE 0x200
469
#endif /* CONFIG_SYS_RAMBOOT */
471
/*-----------------------------------------------------------------------
472
* Cache Configuration
474
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
476
#if defined(CONFIG_CMD_KGDB)
477
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
480
/*-----------------------------------------------------------------------
481
* HIDx - Hardware Implementation-dependent Registers 2-11
482
*-----------------------------------------------------------------------
483
* HID0 also contains cache control - initially enable both caches and
484
* invalidate contents, then the final state leaves only the instruction
485
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
486
* but Soft reset does not.
488
* HID1 has only read-only information - nothing to set.
490
#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
496
#ifdef CONFIG_SYS_LSDRAM
497
/* 8260 local bus is NOT cacheable */
498
#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
502
#else /* !CONFIG_SYS_LSDRAM */
503
#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
507
#endif /* CONFIG_SYS_LSDRAM */
509
#define CONFIG_SYS_HID2 0
511
/*-----------------------------------------------------------------------
512
* RMR - Reset Mode Register
513
*-----------------------------------------------------------------------
515
#define CONFIG_SYS_RMR 0
517
/*-----------------------------------------------------------------------
518
* BCR - Bus Configuration 4-25
519
*-----------------------------------------------------------------------
521
#define CONFIG_SYS_BCR (BCR_EBM |\
526
/*-----------------------------------------------------------------------
527
* SIUMCR - SIU Module Configuration 4-31
528
*-----------------------------------------------------------------------
530
#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
534
/*-----------------------------------------------------------------------
535
* SYPCR - System Protection Control 11-9
536
* SYPCR can only be written once after reset!
537
*-----------------------------------------------------------------------
538
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
540
#ifdef CONFIG_SYS_EP8260_H2
541
/* TBD: Find out why setting the BMT to 0xff causes the FCC to
542
* generate TX buffer underrun errors for large packets under
545
#define CONFIG_SYS_SYPCR_BMT 0x00000600
547
#define CONFIG_SYS_SYPCR_BMT SYPCR_BMT
550
#ifdef CONFIG_SYS_LSDRAM
551
#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
552
CONFIG_SYS_SYPCR_BMT |\
557
#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
558
CONFIG_SYS_SYPCR_BMT |\
563
/*-----------------------------------------------------------------------
564
* TMCNTSC - Time Counter Status and Control 4-40
565
*-----------------------------------------------------------------------
566
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
567
* and enable Time Counter
569
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
574
/*-----------------------------------------------------------------------
575
* PISCR - Periodic Interrupt Status and Control 4-42
576
*-----------------------------------------------------------------------
577
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
580
#ifdef CONFIG_SYS_EP8260_H2
581
#define CONFIG_SYS_PISCR (PISCR_PS |\
585
#define CONFIG_SYS_PISCR 0
588
/*-----------------------------------------------------------------------
589
* SCCR - System Clock Control 9-8
590
*-----------------------------------------------------------------------
592
#ifdef CONFIG_SYS_EP8260_H2
593
#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
595
#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
598
/*-----------------------------------------------------------------------
599
* RCCR - RISC Controller Configuration 13-7
600
*-----------------------------------------------------------------------
602
#define CONFIG_SYS_RCCR 0
604
/*-----------------------------------------------------------------------
605
* MPTPR - Memory Refresh Timer Prescale Register 10-32
606
*-----------------------------------------------------------------------
608
#define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK)
611
* Init Memory Controller:
613
* Bank Bus Machine PortSz Device
614
* ---- --- ------- ------ ------
615
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
616
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
617
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
619
* 4 60x GPCM 8 bit Board Regs, NVRTC
629
/*-----------------------------------------------------------------------
630
* BRx - Base Register
631
* Ref: Section 10.3.1 on page 10-14
632
* ORx - Option Register
633
* Ref: Section 10.3.2 on page 10-18
634
*-----------------------------------------------------------------------
640
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
646
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
655
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
660
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
662
ORxS_ROWST_PBI1_A6 |\
665
#ifdef CONFIG_SYS_EP8260_H2
666
#define CONFIG_SYS_PSDMR 0xC34E246E
668
#define CONFIG_SYS_PSDMR 0xC34E2462
671
#define CONFIG_SYS_PSRT 0x64
673
#ifdef CONFIG_SYS_LSDRAM
678
#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
683
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
685
ORxS_ROWST_PBI0_A9 |\
688
#define CONFIG_SYS_LSDMR 0x416A2562
689
#define CONFIG_SYS_LSRT 0x64
691
#define CONFIG_SYS_LSRT 0x0
692
#endif /* CONFIG_SYS_LSDRAM */
694
/* Bank 4 - On board registers
697
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
702
#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
708
#define CONFIG_SYS_OR4_PRELIM 0xfff00854
710
#ifdef _NOT_USED_SINCE_NOT_WORKING_
711
/* Bank 8 - On board registers
712
* PCMCIA (currently not working!)
714
#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
719
#define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\
730
/* No command line, one static partition, whole device */
731
#undef CONFIG_CMD_MTDPARTS
732
#define CONFIG_JFFS2_DEV "nor0"
733
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
734
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
736
/* mtdparts command line support */
737
/* Note: fake mtd_id used, no linux mtd map file */
739
#define CONFIG_CMD_MTDPARTS
740
#define MTDIDS_DEFAULT ""
741
#define MTDPARTS_DEFAULT ""
744
#endif /* __CONFIG_H */