2
* Copyright (c) 2011 The Chromium OS Authors.
4
* SPDX-License-Identifier: GPL-2.0+
10
#include <asm/arch-tegra/ap.h>
11
#include <asm/arch-tegra/apb_misc.h>
12
#include <asm/arch/clock.h>
13
#include <asm/arch/emc.h>
14
#include <asm/arch/tegra.h>
17
* The EMC registers have shadow registers. When the EMC clock is updated
18
* in the clock controller, the shadow registers are copied to the active
19
* registers, allowing glitchless memory bus frequency changes.
20
* This function updates the shadow registers for a new clock frequency,
21
* and relies on the clock lock on the emc clock to avoid races between
22
* multiple frequency changes
26
* This table defines the ordering of the registers provided to
28
* TODO: Convert to fdt version once available
30
static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
49
0x74, /* BURST_REFRESH_NUM */
60
0xa0, /* TCLKSTABLE */
63
0xac, /* QUSE_EXTRA */
64
0x114, /* FBIO_CFG6 */
67
0x104, /* FBIO_CFG5 */
68
0x2bc, /* CFG_DIG_DLL */
69
0x2c0, /* DLL_XFORM_DQS */
70
0x2c4, /* DLL_XFORM_QUSE */
71
0x2e0, /* ZCAL_REF_CNT */
72
0x2e4, /* ZCAL_WAIT_CNT */
73
0x2a8, /* AUTO_CAL_INTERVAL */
74
0x2d0, /* CFG_CLKTRIM_0 */
75
0x2d4, /* CFG_CLKTRIM_1 */
76
0x2d8, /* CFG_CLKTRIM_2 */
79
struct emc_ctlr *emc_get_controller(const void *blob)
84
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
86
addr = fdtdec_get_addr(blob, node, "reg");
87
if (addr != FDT_ADDR_T_NONE)
88
return (struct emc_ctlr *)addr;
93
/* Error codes we use */
95
ERR_NO_EMC_NODE = -10,
101
ERR_RAM_CODE_NOT_FOUND,
105
* Find EMC tables for the given ram code.
107
* The tegra EMC binding has two options, one using the ram code and one not.
108
* We detect which is in use by looking for the nvidia,use-ram-code property.
109
* If this is not present, then the EMC tables are directly below 'node',
110
* otherwise we select the correct emc-tables subnode based on the 'ram_code'
113
* @param blob Device tree blob
114
* @param node EMC node (nvidia,tegra20-emc compatible string)
115
* @param ram_code RAM code to select (0-3, or -1 if unknown)
116
* @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
118
static int find_emc_tables(const void *blob, int node, int ram_code)
124
/* If we are using RAM codes, scan through the tables for our code */
125
need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");
128
if (ram_code == -1) {
129
debug("%s: RAM code required but not supplied\n", __func__);
130
return ERR_NO_RAM_CODE;
137
* Sadly there is no compatible string so we cannot use
138
* fdtdec_next_compatible_subnode().
140
offset = fdt_next_node(blob, offset, &depth);
144
/* Make sure this is a direct subnode */
147
if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))
150
if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)
155
debug("%s: Could not find tables for RAM code %d\n", __func__,
157
return ERR_RAM_CODE_NOT_FOUND;
161
* Decode the EMC node of the device tree, returning a pointer to the emc
162
* controller and the table to be used for the given rate.
164
* @param blob Device tree blob
165
* @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
166
* @param emcp Returns address of EMC controller registers
167
* @param tablep Returns pointer to table to program into EMC. There are
168
* TEGRA_EMC_NUM_REGS entries, destined for offsets as per the
169
* emc_reg_addr array.
170
* @return 0 if ok, otherwise a -ve error code which will allow someone to
171
* figure out roughly what went wrong by looking at this code.
173
static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
176
struct apb_misc_pp_ctlr *pp =
177
(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
182
ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)
185
* The EMC clock rate is twice the bus rate, and the bus rate is
188
rate = rate / 2 / 1000;
190
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
192
debug("%s: No EMC node found in FDT\n", __func__);
193
return ERR_NO_EMC_NODE;
195
*emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg");
196
if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) {
197
debug("%s: No EMC node reg property\n", __func__);
198
return ERR_NO_EMC_REG;
201
/* Work out the parent node which contains our EMC tables */
202
node = find_emc_tables(blob, node, ram_code & 3);
210
node = fdtdec_next_compatible_subnode(blob, node,
211
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth);
214
node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);
215
if (node_rate == -1) {
216
debug("%s: Missing clock-frequency\n", __func__);
217
return ERR_NO_FREQ; /* we expect this property */
220
if (node_rate == rate)
224
debug("%s: No node found for clock frequency %d\n", __func__,
226
return ERR_FREQ_NOT_FOUND;
229
*tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",
232
debug("%s: node '%s' array missing / wrong size\n", __func__,
233
fdt_get_name(blob, node, NULL));
241
int tegra_set_emc(const void *blob, unsigned rate)
243
struct emc_ctlr *emc;
244
const u32 *table = NULL;
247
err = decode_emc(blob, rate, &emc, &table);
249
debug("Warning: no valid EMC (%d), memory timings unset\n",
254
debug("%s: Table found, setting EMC values as follows:\n", __func__);
255
for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
256
u32 value = fdt32_to_cpu(table[i]);
257
u32 addr = (uintptr_t)emc + emc_reg_addr[i];
259
debug(" %#x: %#x\n", addr, value);
263
/* trigger emc with new settings */
264
clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
265
clock_get_rate(CLOCK_ID_MEMORY), NULL);
266
debug("EMC clock set to %lu\n",
267
clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));