~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))

#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))

/* Static function declarations */

static int mv64460_eth_real_open (struct eth_device *eth);

static int mv64460_eth_real_stop (struct eth_device *eth);

static struct net_device_stats *mv64460_eth_get_stats (struct eth_device

*dev);

static void eth_port_init_mac_tables (ETH_PORT eth_port_num);

static void mv64460_eth_update_stat (struct eth_device *dev);

bool db64460_eth_start (struct eth_device *eth);

unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,

unsigned int mib_offset);

int mv64460_eth_receive (struct eth_device *dev);

int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);

#ifndef UPDATE_STATS_BY_SOFTWARE

static void mv64460_eth_print_stat (struct eth_device *dev);

#endif

extern unsigned int INTERNAL_REG_BASE_ADDR;

/*************************************************

*Helper functions - used inside the driver only *

*************************************************/

#ifdef DEBUG_MV_ETH

void print_globals (struct eth_device *dev)

{

printf ("Ethernet PRINT_Globals-Debug function\n");

printf ("Base Address for ETH_PORT_INFO: %08x\n",

(unsigned int) dev->priv);

printf ("Base Address for mv64460_eth_priv: %08x\n",

(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->

port_private));

printf ("GT Internal Base Address: %08x\n",

INTERNAL_REG_BASE_ADDR);

100

printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);

101

printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);

102

printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",

103

(unsigned int) ((ETH_PORT_INFO *) dev->priv)->

104

p_rx_buffer_base[0],

105

(MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);

106

printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",

107

(unsigned int) ((ETH_PORT_INFO *) dev->priv)->

108

p_tx_buffer_base[0],

109

(MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);

110

}

111

#endif

112

113

#define my_cpu_to_le32(x) my_le32_to_cpu((x))

114

115

unsigned long my_le32_to_cpu (unsigned long x)

116

{

117

return (((x & 0x000000ffU) << 24) |

118

((x & 0x0000ff00U) << 8) |

119

((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));

120

}

121

122

123

/**********************************************************************

124

* mv64460_eth_print_phy_status

125

126

* Prints gigabit ethenret phy status

127

128

* Input : pointer to ethernet interface network device structure

129

* Output : N/A

130

**********************************************************************/

131

132

static void mv64460_eth_print_phy_status (struct eth_device *dev)

133

{

134

struct mv64460_eth_priv *port_private;

135

unsigned int port_num;

136

ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;

137

unsigned int port_status, phy_reg_data;

138

139

port_private =

140

(struct mv64460_eth_priv *) ethernet_private->port_private;

141

port_num = port_private->port_num;

142

143

/* Check Link status on phy */

144

eth_port_read_smi_reg (port_num, 1, &phy_reg_data);

145

if (!(phy_reg_data & 0x20)) {

146

printf ("Ethernet port changed link status to DOWN\n");

147

} else {

148

port_status =

149

MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));

150

printf ("Ethernet status port %d: Link up", port_num);

151

printf (", %s",

152

(port_status & BIT2) ? "Full Duplex" : "Half Duplex");

153

if (port_status & BIT4)

154

printf (", Speed 1 Gbps");

155

else

156

printf (", %s",

157

(port_status & BIT5) ? "Speed 100 Mbps" :

158

"Speed 10 Mbps");

159

printf ("\n");

160

}

161

}

162

163

/**********************************************************************

164

* u-boot entry functions for mv64460_eth

165

166

**********************************************************************/

167

int db64460_eth_probe (struct eth_device *dev)

168

{

169

return ((int) db64460_eth_start (dev));

170

}

171

172

int db64460_eth_poll (struct eth_device *dev)

173

{

174

return mv64460_eth_receive (dev);

175

}

176

177

int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)

178

{

179

mv64460_eth_xmit (dev, packet, length);

180

return 0;

181

}

182

183

void db64460_eth_disable (struct eth_device *dev)

184

{

185

mv64460_eth_stop (dev);

186

}

187

188

189

void mv6446x_eth_initialize (bd_t * bis)

190

{

191

struct eth_device *dev;

192

ETH_PORT_INFO *ethernet_private;

193

struct mv64460_eth_priv *port_private;

194

int devnum, x, temp;

195

char *s, *e, buf[64];

196

197

for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {

198

dev = calloc (sizeof (*dev), 1);

199

if (!dev) {

200

printf ("%s: mv_enet%d allocation failure, %s\n",

201

__FUNCTION__, devnum, "eth_device structure");

202

return;

203

}

204

205

/* must be less than sizeof(dev->name) */

206

sprintf (dev->name, "mv_enet%d", devnum);

207

208

#ifdef DEBUG

209

printf ("Initializing %s\n", dev->name);

210

#endif

211

212

/* Extract the MAC address from the environment */

213

switch (devnum) {

214

case 0:

215

s = "ethaddr";

216

break;

217

218

case 1:

219

s = "eth1addr";

220

break;

221

222

case 2:

223

s = "eth2addr";

224

break;

225

226

default: /* this should never happen */

227

printf ("%s: Invalid device number %d\n",

228

__FUNCTION__, devnum);

229

return;

230

}

231

232

temp = getenv_f(s, buf, sizeof (buf));

233

s = (temp > 0) ? buf : NULL;

234

235

#ifdef DEBUG

236

printf ("Setting MAC %d to %s\n", devnum, s);

237

#endif

238

for (x = 0; x < 6; ++x) {

239

dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;

240

if (s)

241

s = (*e) ? e + 1 : e;

242

}

243

/* ronen - set the MAC addr in the HW */

244

eth_port_uc_addr_set (devnum, dev->enetaddr, 0);

245

246

dev->init = (void *) db64460_eth_probe;

247

dev->halt = (void *) ethernet_phy_reset;

248

dev->send = (void *) db64460_eth_transmit;

249

dev->recv = (void *) db64460_eth_poll;

250

251

ethernet_private = calloc (sizeof (*ethernet_private), 1);

252

dev->priv = (void *)ethernet_private;

253

if (!ethernet_private) {

254

printf ("%s: %s allocation failure, %s\n",

255

__FUNCTION__, dev->name,

256

"Private Device Structure");

257

free (dev);

258

return;

259

}

260

/* start with an zeroed ETH_PORT_INFO */

261

memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));

262

memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);

263

264

/* set pointer to memory for stats data structure etc... */

265

port_private = calloc (sizeof (*ethernet_private), 1);

266

ethernet_private->port_private = (void *)port_private;

267

if (!port_private) {

268

printf ("%s: %s allocation failure, %s\n",

269

__FUNCTION__, dev->name,

270

"Port Private Device Structure");

271

272

free (ethernet_private);

273

free (dev);

274

return;

275

}

276

277

port_private->stats =

278

calloc (sizeof (struct net_device_stats), 1);

279

if (!port_private->stats) {

280

printf ("%s: %s allocation failure, %s\n",

281

__FUNCTION__, dev->name,

282

"Net stat Structure");

283

284

free (port_private);

285

free (ethernet_private);

286

free (dev);

287

return;

288

}

289

memset (ethernet_private->port_private, 0,

290

sizeof (struct mv64460_eth_priv));

291

switch (devnum) {

292

case 0:

293

ethernet_private->port_num = ETH_0;

294

break;

295

case 1:

296

ethernet_private->port_num = ETH_1;

297

break;

298

case 2:

299

ethernet_private->port_num = ETH_2;

300

break;

301

default:

302

printf ("Invalid device number %d\n", devnum);

303

break;

304

};

305

306

port_private->port_num = devnum;

307

308

* Read MIB counter on the GT in order to reset them,

309

* then zero all the stats fields in memory

310

311

mv64460_eth_update_stat (dev);

312

memset (port_private->stats, 0,

313

sizeof (struct net_device_stats));

314

/* Extract the MAC address from the environment */

315

switch (devnum) {

316

case 0:

317

s = "ethaddr";

318

break;

319

320

case 1:

321

s = "eth1addr";

322

break;

323

324

case 2:

325

s = "eth2addr";

326

break;

327

328

default: /* this should never happen */

329

printf ("%s: Invalid device number %d\n",

330

__FUNCTION__, devnum);

331

return;

332

}

333

334

temp = getenv_f(s, buf, sizeof (buf));

335

s = (temp > 0) ? buf : NULL;

336

337

#ifdef DEBUG

338

printf ("Setting MAC %d to %s\n", devnum, s);

339

#endif

340

for (x = 0; x < 6; ++x) {

341

dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;

342

if (s)

343

s = (*e) ? e + 1 : e;

344

}

345

346

DP (printf ("Allocating descriptor and buffer rings\n"));

347

348

ethernet_private->p_rx_desc_area_base[0] =

349

(ETH_RX_DESC *) memalign (16,

350

RX_DESC_ALIGNED_SIZE *

351

MV64460_RX_QUEUE_SIZE + 1);

352

ethernet_private->p_tx_desc_area_base[0] =

353

(ETH_TX_DESC *) memalign (16,

354

TX_DESC_ALIGNED_SIZE *

355

MV64460_TX_QUEUE_SIZE + 1);

356

357

ethernet_private->p_rx_buffer_base[0] =

358

(char *) memalign (16,

359

MV64460_RX_QUEUE_SIZE *

360

MV64460_TX_BUFFER_SIZE + 1);

361

ethernet_private->p_tx_buffer_base[0] =

362

(char *) memalign (16,

363

MV64460_RX_QUEUE_SIZE *

364

MV64460_TX_BUFFER_SIZE + 1);

365

366

#ifdef DEBUG_MV_ETH

367

/* DEBUG OUTPUT prints adresses of globals */

368

print_globals (dev);

369

#endif

370

eth_register (dev);

371

372

}

373

DP (printf ("%s: exit\n", __FUNCTION__));

374

375

}

376

377

/**********************************************************************

378

* mv64460_eth_open

379

380

* This function is called when openning the network device. The function

381

* should initialize all the hardware, initialize cyclic Rx/Tx

382

* descriptors chain and buffers and allocate an IRQ to the network

383

* device.

384

385

* Input : a pointer to the network device structure

386

* / / ronen - changed the output to match net/eth.c needs

387

* Output : nonzero of success , zero if fails.

388

* under construction

389

**********************************************************************/

390

391

int mv64460_eth_open (struct eth_device *dev)

392

{

393

return (mv64460_eth_real_open (dev));

394

}

395

396

/* Helper function for mv64460_eth_open */

397

static int mv64460_eth_real_open (struct eth_device *dev)

398

{

399

400

unsigned int queue;

401

ETH_PORT_INFO *ethernet_private;

402

struct mv64460_eth_priv *port_private;

403

unsigned int port_num;

404

u32 phy_reg_data;

405

406

ethernet_private = (ETH_PORT_INFO *) dev->priv;

407

/* ronen - when we update the MAC env params we only update dev->enetaddr

408

see ./net/eth.c eth_set_enetaddr() */

409

memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);

410

411

port_private =

412

(struct mv64460_eth_priv *) ethernet_private->port_private;

413

port_num = port_private->port_num;

414

415

/* Stop RX Queues */

416

MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),

417

0x0000ff00);

418

419

/* Clear the ethernet port interrupts */

420

MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);

421

MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);

422

423

/* Unmask RX buffer and TX end interrupt */

424

MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),

425

INT_CAUSE_UNMASK_ALL);

426

427

/* Unmask phy and link status changes interrupts */

428

MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),

429

INT_CAUSE_UNMASK_ALL_EXT);

430

431

/* Set phy address of the port */

432

ethernet_private->port_phy_addr = 0x8 + port_num;

433

434

/* Activate the DMA channels etc */

435

eth_port_init (ethernet_private);

436

437

438

/* "Allocate" setup TX rings */

439

440

for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {

441

unsigned int size;

442

443

port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;

444

size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */

445

ethernet_private->tx_desc_area_size[queue] = size;

446

447

/* first clear desc area completely */

448

memset ((void *) ethernet_private->p_tx_desc_area_base[queue],

449

0, ethernet_private->tx_desc_area_size[queue]);

450

451

/* initialize tx desc ring with low level driver */

452

if (ether_init_tx_desc_ring

453

(ethernet_private, ETH_Q0,

454

port_private->tx_ring_size[queue],

455

MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,

456

(unsigned int) ethernet_private->

457

p_tx_desc_area_base[queue],

458

(unsigned int) ethernet_private->

459

p_tx_buffer_base[queue]) == false)

460

printf ("### Error initializing TX Ring\n");

461

}

462

463

/* "Allocate" setup RX rings */

464

for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {

465

unsigned int size;

466

467

/* Meantime RX Ring are fixed - but must be configurable by user */

468

port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;

469

size = (port_private->rx_ring_size[queue] *

470

RX_DESC_ALIGNED_SIZE);

471

ethernet_private->rx_desc_area_size[queue] = size;

472

473

/* first clear desc area completely */

474

memset ((void *) ethernet_private->p_rx_desc_area_base[queue],

475

0, ethernet_private->rx_desc_area_size[queue]);

476

if ((ether_init_rx_desc_ring

477

(ethernet_private, ETH_Q0,

478

port_private->rx_ring_size[queue],

479

MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,

480

(unsigned int) ethernet_private->

481

p_rx_desc_area_base[queue],

482

(unsigned int) ethernet_private->

483

p_rx_buffer_base[queue])) == false)

484

printf ("### Error initializing RX Ring\n");

485

}

486

487

eth_port_start (ethernet_private);

488

489

/* Set maximum receive buffer to 9700 bytes */

490

MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),

491

(0x5 << 17) |

492

(MV_REG_READ

493

(MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))

494

& 0xfff1ffff));

495

496

497

* Set ethernet MTU for leaky bucket mechanism to 0 - this will

498

* disable the leaky bucket mechanism .

499

500

501

MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);

502

MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));

503

504

/* Check Link status on phy */

505

eth_port_read_smi_reg (port_num, 1, &phy_reg_data);

506

if (!(phy_reg_data & 0x20)) {

507

/* Reset PHY */

508

if ((ethernet_phy_reset (port_num)) != true) {

509

printf ("$$ Warnning: No link on port %d \n",

510

port_num);

511

return 0;

512

} else {

513

eth_port_read_smi_reg (port_num, 1, &phy_reg_data);

514

if (!(phy_reg_data & 0x20)) {

515

printf ("### Error: Phy is not active\n");

516

return 0;

517

}

518

}

519

} else {

520

mv64460_eth_print_phy_status (dev);

521

}

522

port_private->eth_running = MAGIC_ETH_RUNNING;

523

return 1;

524

}

525

526

527

static int mv64460_eth_free_tx_rings (struct eth_device *dev)

528

{

529

unsigned int queue;

530

ETH_PORT_INFO *ethernet_private;

531

struct mv64460_eth_priv *port_private;

532

unsigned int port_num;

533

volatile ETH_TX_DESC *p_tx_curr_desc;

534

535

ethernet_private = (ETH_PORT_INFO *) dev->priv;

536

port_private =

537

(struct mv64460_eth_priv *) ethernet_private->port_private;

538

port_num = port_private->port_num;

539

540

/* Stop Tx Queues */

541

MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),

542

0x0000ff00);

543

544

/* Free TX rings */

545

DP (printf ("Clearing previously allocated TX queues... "));

546

for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {

547

/* Free on TX rings */

548

for (p_tx_curr_desc =

549

ethernet_private->p_tx_desc_area_base[queue];

550

((unsigned int) p_tx_curr_desc <= (unsigned int)

551

ethernet_private->p_tx_desc_area_base[queue] +

552

ethernet_private->tx_desc_area_size[queue]);

553

p_tx_curr_desc =

554

(ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +

555

TX_DESC_ALIGNED_SIZE)) {

556

/* this is inside for loop */

557

if (p_tx_curr_desc->return_info != 0) {

558

p_tx_curr_desc->return_info = 0;

559

DP (printf ("freed\n"));

560

}

561

}

562

DP (printf ("Done\n"));

563

}

564

return 0;

565

}

566

567

static int mv64460_eth_free_rx_rings (struct eth_device *dev)

568

{

569

unsigned int queue;

570

ETH_PORT_INFO *ethernet_private;

571

struct mv64460_eth_priv *port_private;

572

unsigned int port_num;

573

volatile ETH_RX_DESC *p_rx_curr_desc;

574

575

ethernet_private = (ETH_PORT_INFO *) dev->priv;

576

port_private =

577

(struct mv64460_eth_priv *) ethernet_private->port_private;

578

port_num = port_private->port_num;

579

580

581

/* Stop RX Queues */

582

MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),

583

0x0000ff00);

584

585

/* Free RX rings */

586

DP (printf ("Clearing previously allocated RX queues... "));

587

for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {

588

/* Free preallocated skb's on RX rings */

589

for (p_rx_curr_desc =

590

ethernet_private->p_rx_desc_area_base[queue];

591

(((unsigned int) p_rx_curr_desc <

592

((unsigned int) ethernet_private->

593

p_rx_desc_area_base[queue] +

594

ethernet_private->rx_desc_area_size[queue])));

595

p_rx_curr_desc =

596

(ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +

597

RX_DESC_ALIGNED_SIZE)) {

598

if (p_rx_curr_desc->return_info != 0) {

599

p_rx_curr_desc->return_info = 0;

600

DP (printf ("freed\n"));

601

}

602

}

603

DP (printf ("Done\n"));

604

}

605

return 0;

606

}

607

608

/**********************************************************************

609

* mv64460_eth_stop

610

611

* This function is used when closing the network device.

612

* It updates the hardware,

613

* release all memory that holds buffers and descriptors and release the IRQ.

614

* Input : a pointer to the device structure

615

* Output : zero if success , nonzero if fails

616

*********************************************************************/

617

618

int mv64460_eth_stop (struct eth_device *dev)

619

{

620

/* Disable all gigE address decoder */

621

MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);

622

DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));

623

mv64460_eth_real_stop (dev);

624

625

return 0;

626

};

627

628

/* Helper function for mv64460_eth_stop */

629

630

static int mv64460_eth_real_stop (struct eth_device *dev)

631

{

632

ETH_PORT_INFO *ethernet_private;

633

struct mv64460_eth_priv *port_private;

634

unsigned int port_num;

635

636

ethernet_private = (ETH_PORT_INFO *) dev->priv;

637

port_private =

638

(struct mv64460_eth_priv *) ethernet_private->port_private;

639

port_num = port_private->port_num;

640

641

642

mv64460_eth_free_tx_rings (dev);

643

mv64460_eth_free_rx_rings (dev);

644

645

eth_port_reset (ethernet_private->port_num);

646

/* Disable ethernet port interrupts */

647

MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);

648

MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);

649

/* Mask RX buffer and TX end interrupt */

650

MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);

651

/* Mask phy and link status changes interrupts */

652

MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);

653

MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,

654

BIT0 << port_num);

655

/* Print Network statistics */

656

#ifndef UPDATE_STATS_BY_SOFTWARE

657

658

* Print statistics (only if ethernet is running),

659

* then zero all the stats fields in memory

660

661

if (port_private->eth_running == MAGIC_ETH_RUNNING) {

662

port_private->eth_running = 0;

663

mv64460_eth_print_stat (dev);

664

}

665

memset (port_private->stats, 0, sizeof (struct net_device_stats));

666

#endif

667

DP (printf ("\nEthernet stopped ... \n"));

668

return 0;

669

}

670

671

672

/**********************************************************************

673

* mv64460_eth_start_xmit

674

675

* This function is queues a packet in the Tx descriptor for

676

* required port.

677

678

* Input : skb - a pointer to socket buffer

679

* dev - a pointer to the required port

680

681

* Output : zero upon success

682

**********************************************************************/

683

684

int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,

685

int dataSize)

686

{

687

ETH_PORT_INFO *ethernet_private;

688

struct mv64460_eth_priv *port_private;

689

PKT_INFO pkt_info;

690

ETH_FUNC_RET_STATUS status;

691

struct net_device_stats *stats;

692

ETH_FUNC_RET_STATUS release_result;

693

694

ethernet_private = (ETH_PORT_INFO *) dev->priv;

695

port_private =

696

(struct mv64460_eth_priv *) ethernet_private->port_private;

697

698

stats = port_private->stats;

699

700

/* Update packet info data structure */

701

pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */

702

pkt_info.byte_cnt = dataSize;

703

pkt_info.buf_ptr = (unsigned int) dataPtr;

704

pkt_info.return_info = 0;

705

706

status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);

707

if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {

708

printf ("Error on transmitting packet ..");

709

if (status == ETH_QUEUE_FULL)

710

printf ("ETH Queue is full. \n");

711

if (status == ETH_QUEUE_LAST_RESOURCE)

712

printf ("ETH Queue: using last available resource. \n");

713

goto error;

714

}

715

716

/* Update statistics and start of transmittion time */

717

stats->tx_bytes += dataSize;

718

stats->tx_packets++;

719

720

/* Check if packet(s) is(are) transmitted correctly (release everything) */

721

do {

722

release_result =

723

eth_tx_return_desc (ethernet_private, ETH_Q0,

724

&pkt_info);

725

switch (release_result) {

726

case ETH_OK:

727

DP (printf ("descriptor released\n"));

728

if (pkt_info.cmd_sts & BIT0) {

729

printf ("Error in TX\n");

730

stats->tx_errors++;

731

732

}

733

break;

734

case ETH_RETRY:

735

DP (printf ("transmission still in process\n"));

736

break;

737

738

case ETH_ERROR:

739

printf ("routine can not access Tx desc ring\n");

740

break;

741

742

case ETH_END_OF_JOB:

743

DP (printf ("the routine has nothing to release\n"));

744

break;

745

default: /* should not happen */

746

break;

747

}

748

} while (release_result == ETH_OK);

749

750

751

return 0; /* success */

752

error:

753

return 1; /* Failed - higher layers will free the skb */

754

}

755

756

/**********************************************************************

757

* mv64460_eth_receive

758

759

* This function is forward packets that are received from the port's

760

* queues toward kernel core or FastRoute them to another interface.

761

762

* Input : dev - a pointer to the required interface

763

* max - maximum number to receive (0 means unlimted)

764

765

* Output : number of served packets

766

**********************************************************************/

767

768

int mv64460_eth_receive (struct eth_device *dev)

769

{

770

ETH_PORT_INFO *ethernet_private;

771

struct mv64460_eth_priv *port_private;

772

PKT_INFO pkt_info;

773

struct net_device_stats *stats;

774

775

ethernet_private = (ETH_PORT_INFO *) dev->priv;

776

port_private =

777

(struct mv64460_eth_priv *) ethernet_private->port_private;

778

stats = port_private->stats;

779

780

while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==

781

ETH_OK)) {

782

783

#ifdef DEBUG_MV_ETH

784

if (pkt_info.byte_cnt != 0) {

785

printf ("%s: Received %d byte Packet @ 0x%x\n",

786

__FUNCTION__, pkt_info.byte_cnt,

787

pkt_info.buf_ptr);

788

}

789

#endif

790

/* Update statistics. Note byte count includes 4 byte CRC count */

791

stats->rx_packets++;

792

stats->rx_bytes += pkt_info.byte_cnt;

793

794

795

* In case received a packet without first / last bits on OR the error

796

* summary bit is on, the packets needs to be dropeed.

797

798

if (((pkt_info.

799

cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=

800

(ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))

801

|| (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {

802

stats->rx_dropped++;

803

804

printf ("Received packet spread on multiple descriptors\n");

805

806

/* Is this caused by an error ? */

807

if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {

808

stats->rx_errors++;

809

}

810

811

/* free these descriptors again without forwarding them to the higher layers */

812

pkt_info.buf_ptr &= ~0x7; /* realign buffer again */

813

pkt_info.byte_cnt = 0x0000; /* Reset Byte count */

814

815

if (eth_rx_return_buff

816

(ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {

817

printf ("Error while returning the RX Desc to Ring\n");

818

} else {

819

DP (printf ("RX Desc returned to Ring\n"));

820

}

821

/* /free these descriptors again */

822

} else {

823

824

/* !!! call higher layer processing */

825

#ifdef DEBUG_MV_ETH

826

printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");

827

#endif

828

/* let the upper layer handle the packet */

829

NetReceive ((uchar *) pkt_info.buf_ptr,

830

(int) pkt_info.byte_cnt);

831

832

/* **************************************************************** */

833

/* free descriptor */

834

pkt_info.buf_ptr &= ~0x7; /* realign buffer again */

835

pkt_info.byte_cnt = 0x0000; /* Reset Byte count */

836

DP (printf

837

("RX: pkt_info.buf_ptr = %x\n",

838

pkt_info.buf_ptr));

839

if (eth_rx_return_buff

840

(ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {

841

printf ("Error while returning the RX Desc to Ring\n");

842

} else {

843

DP (printf ("RX Desc returned to Ring\n"));

844

}

845

846

/* **************************************************************** */

847

848

}

849

}

850

mv64460_eth_get_stats (dev); /* update statistics */

851

return 1;

852

}

853

854

/**********************************************************************

855

* mv64460_eth_get_stats

856

857

* Returns a pointer to the interface statistics.

858

859

* Input : dev - a pointer to the required interface

860

861

* Output : a pointer to the interface's statistics

862

**********************************************************************/

863

864

static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)

865

{

866

ETH_PORT_INFO *ethernet_private;

867

struct mv64460_eth_priv *port_private;

868

869

ethernet_private = (ETH_PORT_INFO *) dev->priv;

870

port_private =

871

(struct mv64460_eth_priv *) ethernet_private->port_private;

872

873

mv64460_eth_update_stat (dev);

874

875

return port_private->stats;

876

}

877

878

879

/**********************************************************************

880

* mv64460_eth_update_stat

881

882

* Update the statistics structure in the private data structure

883

884

* Input : pointer to ethernet interface network device structure

885

* Output : N/A

886

**********************************************************************/

887

888

static void mv64460_eth_update_stat (struct eth_device *dev)

889

{

890

ETH_PORT_INFO *ethernet_private;

891

struct mv64460_eth_priv *port_private;

892

struct net_device_stats *stats;

893

894

ethernet_private = (ETH_PORT_INFO *) dev->priv;

895

port_private =

896

(struct mv64460_eth_priv *) ethernet_private->port_private;

897

stats = port_private->stats;

898

899

/* These are false updates */

900

stats->rx_packets += (unsigned long)

901

eth_read_mib_counter (ethernet_private->port_num,

902

ETH_MIB_GOOD_FRAMES_RECEIVED);

903

stats->tx_packets += (unsigned long)

904

eth_read_mib_counter (ethernet_private->port_num,

905

ETH_MIB_GOOD_FRAMES_SENT);

906

stats->rx_bytes += (unsigned long)

907

eth_read_mib_counter (ethernet_private->port_num,

908

ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);

909

910

* Ideally this should be as follows -

911

912

* stats->rx_bytes += stats->rx_bytes +

913

* ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,

914

* ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);

915

916

* But the unsigned long in PowerPC and MIPS are 32bit. So the next read

917

* is just a dummy read for proper work of the GigE port

918

919

eth_read_mib_counter (ethernet_private->port_num,

920

ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);

921

stats->tx_bytes += (unsigned long)

922

eth_read_mib_counter (ethernet_private->port_num,

923

ETH_MIB_GOOD_OCTETS_SENT_LOW);

924

eth_read_mib_counter (ethernet_private->port_num,

925

ETH_MIB_GOOD_OCTETS_SENT_HIGH);

926

stats->rx_errors += (unsigned long)

927

eth_read_mib_counter (ethernet_private->port_num,

928

ETH_MIB_MAC_RECEIVE_ERROR);

929

930

/* Rx dropped is for received packet with CRC error */

931

stats->rx_dropped +=

932

(unsigned long) eth_read_mib_counter (ethernet_private->

933

port_num,

934

ETH_MIB_BAD_CRC_EVENT);

935

stats->multicast += (unsigned long)

936

eth_read_mib_counter (ethernet_private->port_num,

937

ETH_MIB_MULTICAST_FRAMES_RECEIVED);

938

stats->collisions +=

939

(unsigned long) eth_read_mib_counter (ethernet_private->

940

port_num,

941

ETH_MIB_COLLISION) +

942

(unsigned long) eth_read_mib_counter (ethernet_private->

943

port_num,

944

ETH_MIB_LATE_COLLISION);

945

/* detailed rx errors */

946

stats->rx_length_errors +=

947

(unsigned long) eth_read_mib_counter (ethernet_private->

948

port_num,

949

ETH_MIB_UNDERSIZE_RECEIVED)

950

951

(unsigned long) eth_read_mib_counter (ethernet_private->

952

port_num,

953

ETH_MIB_OVERSIZE_RECEIVED);

954

/* detailed tx errors */

955

}

956

957

#ifndef UPDATE_STATS_BY_SOFTWARE

958

/**********************************************************************

959

* mv64460_eth_print_stat

960

961

* Update the statistics structure in the private data structure

962

963

* Input : pointer to ethernet interface network device structure

964

* Output : N/A

965

**********************************************************************/

966

967

static void mv64460_eth_print_stat (struct eth_device *dev)

968

{

969

ETH_PORT_INFO *ethernet_private;

970

struct mv64460_eth_priv *port_private;

971

struct net_device_stats *stats;

972

973

ethernet_private = (ETH_PORT_INFO *) dev->priv;

974

port_private =

975

(struct mv64460_eth_priv *) ethernet_private->port_private;

976

stats = port_private->stats;

977

978

/* These are false updates */

979

printf ("\n### Network statistics: ###\n");

980

printf ("--------------------------\n");

981

printf (" Packets received: %ld\n", stats->rx_packets);

982

printf (" Packets send: %ld\n", stats->tx_packets);

983

printf (" Received bytes: %ld\n", stats->rx_bytes);

984

printf (" Send bytes: %ld\n", stats->tx_bytes);

985

if (stats->rx_errors != 0)

986

printf (" Rx Errors: %ld\n",

987

stats->rx_errors);

988

if (stats->rx_dropped != 0)

989

printf (" Rx dropped (CRC Errors): %ld\n",

990

stats->rx_dropped);

991

if (stats->multicast != 0)

992

printf (" Rx mulicast frames: %ld\n",

993

stats->multicast);

994

if (stats->collisions != 0)

995

printf (" No. of collisions: %ld\n",

996

stats->collisions);

997

if (stats->rx_length_errors != 0)

998

printf (" Rx length errors: %ld\n",

999

stats->rx_length_errors);

1000

}

1001

#endif

1002

1003

/**************************************************************************

1004

*network_start - Network Kick Off Routine UBoot

1005

*Inputs :

1006

*Outputs :

1007

**************************************************************************/

1008

1009

bool db64460_eth_start (struct eth_device *dev)

1010

{

1011

return (mv64460_eth_open (dev)); /* calls real open */

1012

}

1013

1014

/*************************************************************************

1015

**************************************************************************

1016

**************************************************************************

1017

* The second part is the low level driver of the gigE ethernet ports. *

1018

**************************************************************************

1019

**************************************************************************

1020

*************************************************************************/

1021

1022

* based on Linux code

1023

* arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports

1024

1025

* SPDX-License-Identifier: GPL-2.0+

1026

1027

1028

/********************************************************************************

1029

* Marvell's Gigabit Ethernet controller low level driver

1030

1031

* DESCRIPTION:

1032

* This file introduce low level API to Marvell's Gigabit Ethernet

1033

* controller. This Gigabit Ethernet Controller driver API controls

1034

* 1) Operations (i.e. port init, start, reset etc').

1035

* 2) Data flow (i.e. port send, receive etc').

1036

* Each Gigabit Ethernet port is controlled via ETH_PORT_INFO

1037

* struct.

1038

* This struct includes user configuration information as well as

1039

* driver internal data needed for its operations.

1040

1041

* Supported Features:

1042

* - This low level driver is OS independent. Allocating memory for

1043

* the descriptor rings and buffers are not within the scope of

1044

* this driver.

1045

* - The user is free from Rx/Tx queue managing.

1046

* - This low level driver introduce functionality API that enable

1047

* the to operate Marvell's Gigabit Ethernet Controller in a

1048

* convenient way.

1049

* - Simple Gigabit Ethernet port operation API.

1050

* - Simple Gigabit Ethernet port data flow API.

1051

* - Data flow and operation API support per queue functionality.

1052

* - Support cached descriptors for better performance.

1053

* - Enable access to all four DRAM banks and internal SRAM memory

1054

* spaces.

1055

* - PHY access and control API.

1056

* - Port control register configuration API.

1057

* - Full control over Unicast and Multicast MAC configurations.

1058

1059

* Operation flow:

1060

1061

* Initialization phase

1062

* This phase complete the initialization of the ETH_PORT_INFO

1063

* struct.

1064

* User information regarding port configuration has to be set

1065

* prior to calling the port initialization routine. For example,

1066

* the user has to assign the port_phy_addr field which is board

1067

* depended parameter.

1068

* In this phase any port Tx/Rx activity is halted, MIB counters

1069

* are cleared, PHY address is set according to user parameter and

1070

* access to DRAM and internal SRAM memory spaces.

1071

1072

* Driver ring initialization

1073

* Allocating memory for the descriptor rings and buffers is not

1074

* within the scope of this driver. Thus, the user is required to

1075

* allocate memory for the descriptors ring and buffers. Those

1076

* memory parameters are used by the Rx and Tx ring initialization

1077

* routines in order to curve the descriptor linked list in a form

1078

* of a ring.

1079

* Note: Pay special attention to alignment issues when using

1080

* cached descriptors/buffers. In this phase the driver store

1081

* information in the ETH_PORT_INFO struct regarding each queue

1082

* ring.

1083

1084

* Driver start

1085

* This phase prepares the Ethernet port for Rx and Tx activity.

1086

* It uses the information stored in the ETH_PORT_INFO struct to

1087

* initialize the various port registers.

1088

1089

* Data flow:

1090

* All packet references to/from the driver are done using PKT_INFO

1091

* struct.

1092

* This struct is a unified struct used with Rx and Tx operations.

1093

* This way the user is not required to be familiar with neither

1094

* Tx nor Rx descriptors structures.

1095

* The driver's descriptors rings are management by indexes.

1096

* Those indexes controls the ring resources and used to indicate

1097

* a SW resource error:

1098

* 'current'

1099

* This index points to the current available resource for use. For

1100

* example in Rx process this index will point to the descriptor

1101

* that will be passed to the user upon calling the receive routine.

1102

* In Tx process, this index will point to the descriptor

1103

* that will be assigned with the user packet info and transmitted.

1104

* 'used'

1105

* This index points to the descriptor that need to restore its

1106

* resources. For example in Rx process, using the Rx buffer return

1107

* API will attach the buffer returned in packet info to the

1108

* descriptor pointed by 'used'. In Tx process, using the Tx

1109

* descriptor return will merely return the user packet info with

1110

* the command status of the transmitted buffer pointed by the

1111

* 'used' index. Nevertheless, it is essential to use this routine

1112

* to update the 'used' index.

1113

* 'first'

1114

* This index supports Tx Scatter-Gather. It points to the first

1115

* descriptor of a packet assembled of multiple buffers. For example

1116

* when in middle of Such packet we have a Tx resource error the

1117

* 'curr' index get the value of 'first' to indicate that the ring

1118

* returned to its state before trying to transmit this packet.

1119

1120

* Receive operation:

1121

* The eth_port_receive API set the packet information struct,

1122

* passed by the caller, with received information from the

1123

* 'current' SDMA descriptor.

1124

* It is the user responsibility to return this resource back

1125

* to the Rx descriptor ring to enable the reuse of this source.

1126

* Return Rx resource is done using the eth_rx_return_buff API.

1127

1128

* Transmit operation:

1129

* The eth_port_send API supports Scatter-Gather which enables to

1130

* send a packet spanned over multiple buffers. This means that

1131

* for each packet info structure given by the user and put into

1132

* the Tx descriptors ring, will be transmitted only if the 'LAST'

1133

* bit will be set in the packet info command status field. This

1134

* API also consider restriction regarding buffer alignments and

1135

* sizes.

1136

* The user must return a Tx resource after ensuring the buffer

1137

* has been transmitted to enable the Tx ring indexes to update.

1138

1139

* BOARD LAYOUT

1140

* This device is on-board. No jumper diagram is necessary.

1141

1142

* EXTERNAL INTERFACE

1143

1144

* Prior to calling the initialization routine eth_port_init() the user

1145

* must set the following fields under ETH_PORT_INFO struct:

1146

* port_num User Ethernet port number.

1147

* port_phy_addr User PHY address of Ethernet port.

1148

* port_mac_addr[6] User defined port MAC address.

1149

* port_config User port configuration value.

1150

* port_config_extend User port config extend value.

1151

* port_sdma_config User port SDMA config value.

1152

* port_serial_control User port serial control value.

1153

* *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.

1154

* *port_private User scratch pad for user specific data structures.

1155

1156

* This driver introduce a set of default values:

1157

* PORT_CONFIG_VALUE Default port configuration value

1158

* PORT_CONFIG_EXTEND_VALUE Default port extend configuration value

1159

* PORT_SDMA_CONFIG_VALUE Default sdma control value

1160

* PORT_SERIAL_CONTROL_VALUE Default port serial control value

1161

1162

* This driver data flow is done using the PKT_INFO struct which is

1163

* a unified struct for Rx and Tx operations:

1164

* byte_cnt Tx/Rx descriptor buffer byte count.

1165

* l4i_chk CPU provided TCP Checksum. For Tx operation only.

1166

* cmd_sts Tx/Rx descriptor command status.

1167

* buf_ptr Tx/Rx descriptor buffer pointer.

1168

* return_info Tx/Rx user resource return information.

1169

1170

1171

* EXTERNAL SUPPORT REQUIREMENTS

1172

1173

* This driver requires the following external support:

1174

1175

* D_CACHE_FLUSH_LINE (address, address offset)

1176

1177

* This macro applies assembly code to flush and invalidate cache

1178

* line.

1179

* address - address base.

1180

* address offset - address offset

1181

1182

1183

* CPU_PIPE_FLUSH

1184

1185

* This macro applies assembly code to flush the CPU pipeline.

1186

1187

*******************************************************************************/

1188

/* includes */

1189

1190

/* defines */

1191

/* SDMA command macros */

1192

#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \

1193

MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))

1194

1195

#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \

1196

MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\

1197

(1 << (8 + tx_queue)))

1198

1199

#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \

1200

MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))

1201

1202

#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \

1203

MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))

1204

1205

#define CURR_RFD_GET(p_curr_desc, queue) \

1206

((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])

1207

1208

#define CURR_RFD_SET(p_curr_desc, queue) \

1209

(p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))

1210

1211

#define USED_RFD_GET(p_used_desc, queue) \

1212

((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])

1213

1214

#define USED_RFD_SET(p_used_desc, queue)\

1215

(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))

1216

1217

1218

#define CURR_TFD_GET(p_curr_desc, queue) \

1219

((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])

1220

1221

#define CURR_TFD_SET(p_curr_desc, queue) \

1222

(p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))

1223

1224

#define USED_TFD_GET(p_used_desc, queue) \

1225

((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])

1226

1227

#define USED_TFD_SET(p_used_desc, queue) \

1228

(p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))

1229

1230

#define FIRST_TFD_GET(p_first_desc, queue) \

1231

((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])

1232

1233

#define FIRST_TFD_SET(p_first_desc, queue) \

1234

(p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))

1235

1236

1237

/* Macros that save access to desc in order to find next desc pointer */

1238

#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])

1239

1240

#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])

1241

1242

#define LINK_UP_TIMEOUT 100000

1243

#define PHY_BUSY_TIMEOUT 10000000

1244

1245

/* locals */

1246

1247

/* PHY routines */

1248

static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);

1249

static int ethernet_phy_get (ETH_PORT eth_port_num);

1250

1251

/* Ethernet Port routines */

1252

static void eth_set_access_control (ETH_PORT eth_port_num,

1253

ETH_WIN_PARAM * param);

1254

static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,

1255

ETH_QUEUE queue, int option);

1256

#if 0 /* FIXME */

1257

static bool eth_port_smc_addr (ETH_PORT eth_port_num,

1258

unsigned char mc_byte,

1259

ETH_QUEUE queue, int option);

1260

static bool eth_port_omc_addr (ETH_PORT eth_port_num,

1261

unsigned char crc8,

1262

ETH_QUEUE queue, int option);

1263

#endif

1264

1265

static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,

1266

int byte_count);

1267

1268

void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);

1269

1270

1271

typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;

1272

u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)

1273

{

1274

u32 result = 0;

1275

u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);

1276

1277

if (enable & (1 << bank))

1278

return 0;

1279

if (bank == BANK0)

1280

result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);

1281

if (bank == BANK1)

1282

result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);

1283

if (bank == BANK2)

1284

result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);

1285

if (bank == BANK3)

1286

result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);

1287

result &= 0x0000ffff;

1288

result = result << 16;

1289

return result;

1290

}

1291

1292

u32 mv_get_dram_bank_size (MEMORY_BANK bank)

1293

{

1294

u32 result = 0;

1295

u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);

1296

1297

if (enable & (1 << bank))

1298

return 0;

1299

if (bank == BANK0)

1300

result = MV_REG_READ (MV64460_CS_0_SIZE);

1301

if (bank == BANK1)

1302

result = MV_REG_READ (MV64460_CS_1_SIZE);

1303

if (bank == BANK2)

1304

result = MV_REG_READ (MV64460_CS_2_SIZE);

1305

if (bank == BANK3)

1306

result = MV_REG_READ (MV64460_CS_3_SIZE);

1307

result += 1;

1308

result &= 0x0000ffff;

1309

result = result << 16;

1310

return result;

1311

}

1312

1313

u32 mv_get_internal_sram_base (void)

1314

{

1315

u32 result;

1316

1317

result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);

1318

result &= 0x0000ffff;

1319

result = result << 16;

1320

return result;

1321

}

1322

1323

/*******************************************************************************

1324

* eth_port_init - Initialize the Ethernet port driver

1325

1326

* DESCRIPTION:

1327

* This function prepares the ethernet port to start its activity:

1328

* 1) Completes the ethernet port driver struct initialization toward port

1329

* start routine.

1330

* 2) Resets the device to a quiescent state in case of warm reboot.

1331

* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.

1332

* 4) Clean MAC tables. The reset status of those tables is unknown.

1333

* 5) Set PHY address.

1334

* Note: Call this routine prior to eth_port_start routine and after setting

1335

* user values in the user fields of Ethernet port control struct (i.e.

1336

* port_phy_addr).

1337

1338

* INPUT:

1339

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct

1340

1341

* OUTPUT:

1342

* See description.

1343

1344

* RETURN:

1345

* None.

1346

1347

*******************************************************************************/

1348

static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)

1349

{

1350

int queue;

1351

ETH_WIN_PARAM win_param;

1352

1353

p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;

1354

p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;

1355

p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;

1356

p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;

1357

1358

p_eth_port_ctrl->port_rx_queue_command = 0;

1359

p_eth_port_ctrl->port_tx_queue_command = 0;

1360

1361

/* Zero out SW structs */

1362

for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {

1363

CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);

1364

USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);

1365

p_eth_port_ctrl->rx_resource_err[queue] = false;

1366

}

1367

1368

for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {

1369

CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);

1370

USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);

1371

FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);

1372

p_eth_port_ctrl->tx_resource_err[queue] = false;

1373

}

1374

1375

eth_port_reset (p_eth_port_ctrl->port_num);

1376

1377

/* Set access parameters for DRAM bank 0 */

1378

win_param.win = ETH_WIN0; /* Use Ethernet window 0 */

1379

win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */

1380

win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */

1381

#ifndef CONFIG_NOT_COHERENT_CACHE

1382

win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;

1383

#endif

1384

win_param.high_addr = 0;

1385

/* Get bank base */

1386

win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);

1387

win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */

1388

if (win_param.size == 0)

1389

win_param.enable = 0;

1390

else

1391

win_param.enable = 1; /* Enable the access */

1392

win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */

1393

1394

/* Set the access control for address window (EPAPR) READ & WRITE */

1395

eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);

1396

1397

/* Set access parameters for DRAM bank 1 */

1398

win_param.win = ETH_WIN1; /* Use Ethernet window 1 */

1399

win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */

1400

win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */

1401

#ifndef CONFIG_NOT_COHERENT_CACHE

1402

win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;

1403

#endif

1404

win_param.high_addr = 0;

1405

/* Get bank base */

1406

win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);

1407

win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */

1408

if (win_param.size == 0)

1409

win_param.enable = 0;

1410

else

1411

win_param.enable = 1; /* Enable the access */

1412

win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */

1413

1414

/* Set the access control for address window (EPAPR) READ & WRITE */

1415

eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);

1416

1417

/* Set access parameters for DRAM bank 2 */

1418

win_param.win = ETH_WIN2; /* Use Ethernet window 2 */

1419

win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */

1420

win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */

1421

#ifndef CONFIG_NOT_COHERENT_CACHE

1422

win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;

1423

#endif

1424

win_param.high_addr = 0;

1425

/* Get bank base */

1426

win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);

1427

win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */

1428

if (win_param.size == 0)

1429

win_param.enable = 0;

1430

else

1431

win_param.enable = 1; /* Enable the access */

1432

win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */

1433

1434

/* Set the access control for address window (EPAPR) READ & WRITE */

1435

eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);

1436

1437

/* Set access parameters for DRAM bank 3 */

1438

win_param.win = ETH_WIN3; /* Use Ethernet window 3 */

1439

win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */

1440

win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */

1441

#ifndef CONFIG_NOT_COHERENT_CACHE

1442

win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;

1443

#endif

1444

win_param.high_addr = 0;

1445

/* Get bank base */

1446

win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);

1447

win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */

1448

if (win_param.size == 0)

1449

win_param.enable = 0;

1450

else

1451

win_param.enable = 1; /* Enable the access */

1452

win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */

1453

1454

/* Set the access control for address window (EPAPR) READ & WRITE */

1455

eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);

1456

1457

/* Set access parameters for Internal SRAM */

1458

win_param.win = ETH_WIN4; /* Use Ethernet window 0 */

1459

win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */

1460

win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;

1461

win_param.high_addr = 0;

1462

win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */

1463

win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */

1464

win_param.enable = 1; /* Enable the access */

1465

win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */

1466

1467

/* Set the access control for address window (EPAPR) READ & WRITE */

1468

eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);

1469

1470

eth_port_init_mac_tables (p_eth_port_ctrl->port_num);

1471

1472

ethernet_phy_set (p_eth_port_ctrl->port_num,

1473

p_eth_port_ctrl->port_phy_addr);

1474

1475

return;

1476

1477

}

1478

1479

/*******************************************************************************

1480

* eth_port_start - Start the Ethernet port activity.

1481

1482

* DESCRIPTION:

1483

* This routine prepares the Ethernet port for Rx and Tx activity:

1484

* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that

1485

* has been initialized a descriptor's ring (using ether_init_tx_desc_ring

1486

* for Tx and ether_init_rx_desc_ring for Rx)

1487

* 2. Initialize and enable the Ethernet configuration port by writing to

1488

* the port's configuration and command registers.

1489

* 3. Initialize and enable the SDMA by writing to the SDMA's

1490

* configuration and command registers.

1491

* After completing these steps, the ethernet port SDMA can starts to

1492

* perform Rx and Tx activities.

1493

1494

* Note: Each Rx and Tx queue descriptor's list must be initialized prior

1495

* to calling this function (use ether_init_tx_desc_ring for Tx queues and

1496

* ether_init_rx_desc_ring for Rx queues).

1497

1498

* INPUT:

1499

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct

1500

1501

* OUTPUT:

1502

* Ethernet port is ready to receive and transmit.

1503

1504

* RETURN:

1505

* false if the port PHY is not up.

1506

* true otherwise.

1507

1508

*******************************************************************************/

1509

static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)

1510

{

1511

int queue;

1512

volatile ETH_TX_DESC *p_tx_curr_desc;

1513

volatile ETH_RX_DESC *p_rx_curr_desc;

1514

unsigned int phy_reg_data;

1515

ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;

1516

1517

1518

/* Assignment of Tx CTRP of given queue */

1519

for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {

1520

CURR_TFD_GET (p_tx_curr_desc, queue);

1521

MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0

1522

(eth_port_num)

1523

+ (4 * queue)),

1524

((unsigned int) p_tx_curr_desc));

1525

1526

}

1527

1528

/* Assignment of Rx CRDP of given queue */

1529

for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {

1530

CURR_RFD_GET (p_rx_curr_desc, queue);

1531

MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0

1532

(eth_port_num)

1533

+ (4 * queue)),

1534

((unsigned int) p_rx_curr_desc));

1535

1536

if (p_rx_curr_desc != NULL)

1537

/* Add the assigned Ethernet address to the port's address table */

1538

eth_port_uc_addr_set (p_eth_port_ctrl->port_num,

1539

p_eth_port_ctrl->port_mac_addr,

1540

queue);

1541

}

1542

1543

/* Assign port configuration and command. */

1544

MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),

1545

p_eth_port_ctrl->port_config);

1546

1547

MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),

1548

p_eth_port_ctrl->port_config_extend);

1549

1550

MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),

1551

p_eth_port_ctrl->port_serial_control);

1552

1553

MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),

1554

ETH_SERIAL_PORT_ENABLE);

1555

1556

/* Assign port SDMA configuration */

1557

MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),

1558

p_eth_port_ctrl->port_sdma_config);

1559

1560

MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT

1561

(eth_port_num), 0x3fffffff);

1562

MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG

1563

(eth_port_num), 0x03fffcff);

1564

/* Turn off the port/queue bandwidth limitation */

1565

MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);

1566

1567

/* Enable port Rx. */

1568

MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),

1569

p_eth_port_ctrl->port_rx_queue_command);

1570

1571

/* Check if link is up */

1572

eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);

1573

1574

if (!(phy_reg_data & 0x20))

1575

return false;

1576

1577

return true;

1578

}

1579

1580

/*******************************************************************************

1581

* eth_port_uc_addr_set - This function Set the port Unicast address.

1582

1583

* DESCRIPTION:

1584

* This function Set the port Ethernet MAC address.

1585

1586

* INPUT:

1587

* ETH_PORT eth_port_num Port number.

1588

* char * p_addr Address to be set

1589

* ETH_QUEUE queue Rx queue number for this MAC address.

1590

1591

* OUTPUT:

1592

* Set MAC address low and high registers. also calls eth_port_uc_addr()

1593

* To set the unicast table with the proper information.

1594

1595

* RETURN:

1596

* N/A.

1597

1598

*******************************************************************************/

1599

static void eth_port_uc_addr_set (ETH_PORT eth_port_num,

1600

unsigned char *p_addr, ETH_QUEUE queue)

1601

{

1602

unsigned int mac_h;

1603

unsigned int mac_l;

1604

1605

mac_l = (p_addr[4] << 8) | (p_addr[5]);

1606

mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |

1607

(p_addr[2] << 8) | (p_addr[3] << 0);

1608

1609

MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);

1610

MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);

1611

1612

/* Accept frames of this address */

1613

eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);

1614

1615

return;

1616

}

1617

1618

/*******************************************************************************

1619

* eth_port_uc_addr - This function Set the port unicast address table

1620

1621

* DESCRIPTION:

1622

* This function locates the proper entry in the Unicast table for the

1623

* specified MAC nibble and sets its properties according to function

1624

* parameters.

1625

1626

* INPUT:

1627

* ETH_PORT eth_port_num Port number.

1628

* unsigned char uc_nibble Unicast MAC Address last nibble.

1629

* ETH_QUEUE queue Rx queue number for this MAC address.

1630

* int option 0 = Add, 1 = remove address.

1631

1632

* OUTPUT:

1633

* This function add/removes MAC addresses from the port unicast address

1634

* table.

1635

1636

* RETURN:

1637

* true is output succeeded.

1638

* false if option parameter is invalid.

1639

1640

*******************************************************************************/

1641

static bool eth_port_uc_addr (ETH_PORT eth_port_num,

1642

unsigned char uc_nibble,

1643

ETH_QUEUE queue, int option)

1644

{

1645

unsigned int unicast_reg;

1646

unsigned int tbl_offset;

1647

unsigned int reg_offset;

1648

1649

/* Locate the Unicast table entry */

1650

uc_nibble = (0xf & uc_nibble);

1651

tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */

1652

reg_offset = uc_nibble % 4; /* Entry offset within the above register */

1653

1654

switch (option) {

1655

case REJECT_MAC_ADDR:

1656

/* Clear accepts frame bit at specified unicast DA table entry */

1657

unicast_reg =

1658

MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE

1659

(eth_port_num)

1660

+ tbl_offset));

1661

1662

unicast_reg &= (0x0E << (8 * reg_offset));

1663

1664

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE

1665

(eth_port_num)

1666

+ tbl_offset), unicast_reg);

1667

break;

1668

1669

case ACCEPT_MAC_ADDR:

1670

/* Set accepts frame bit at unicast DA filter table entry */

1671

unicast_reg =

1672

MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE

1673

(eth_port_num)

1674

+ tbl_offset));

1675

1676

unicast_reg |= ((0x01 | queue) << (8 * reg_offset));

1677

1678

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE

1679

(eth_port_num)

1680

+ tbl_offset), unicast_reg);

1681

1682

break;

1683

1684

default:

1685

return false;

1686

}

1687

return true;

1688

}

1689

1690

#if 0 /* FIXME */

1691

/*******************************************************************************

1692

* eth_port_mc_addr - Multicast address settings.

1693

1694

* DESCRIPTION:

1695

* This API controls the MV device MAC multicast support.

1696

* The MV device supports multicast using two tables:

1697

* 1) Special Multicast Table for MAC addresses of the form

1698

* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).

1699

* The MAC DA[7:0] bits are used as a pointer to the Special Multicast

1700

* Table entries in the DA-Filter table.

1701

* In this case, the function calls eth_port_smc_addr() routine to set the

1702

* Special Multicast Table.

1703

* 2) Other Multicast Table for multicast of another type. A CRC-8bit

1704

* is used as an index to the Other Multicast Table entries in the

1705

* DA-Filter table.

1706

* In this case, the function calculates the CRC-8bit value and calls

1707

* eth_port_omc_addr() routine to set the Other Multicast Table.

1708

* INPUT:

1709

* ETH_PORT eth_port_num Port number.

1710

* unsigned char *p_addr Unicast MAC Address.

1711

* ETH_QUEUE queue Rx queue number for this MAC address.

1712

* int option 0 = Add, 1 = remove address.

1713

1714

* OUTPUT:

1715

* See description.

1716

1717

* RETURN:

1718

* true is output succeeded.

1719

* false if add_address_table_entry( ) failed.

1720

1721

*******************************************************************************/

1722

static void eth_port_mc_addr (ETH_PORT eth_port_num,

1723

unsigned char *p_addr,

1724

ETH_QUEUE queue, int option)

1725

{

1726

unsigned int mac_h;

1727

unsigned int mac_l;

1728

unsigned char crc_result = 0;

1729

int mac_array[48];

1730

int crc[8];

1731

int i;

1732

1733

1734

if ((p_addr[0] == 0x01) &&

1735

(p_addr[1] == 0x00) &&

1736

(p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))

1737

1738

eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);

1739

else {

1740

/* Calculate CRC-8 out of the given address */

1741

mac_h = (p_addr[0] << 8) | (p_addr[1]);

1742

mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |

1743

(p_addr[4] << 8) | (p_addr[5] << 0);

1744

1745

for (i = 0; i < 32; i++)

1746

mac_array[i] = (mac_l >> i) & 0x1;

1747

for (i = 32; i < 48; i++)

1748

mac_array[i] = (mac_h >> (i - 32)) & 0x1;

1749

1750

1751

crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^

1752

mac_array[39] ^ mac_array[35] ^ mac_array[34] ^

1753

mac_array[31] ^ mac_array[30] ^ mac_array[28] ^

1754

mac_array[23] ^ mac_array[21] ^ mac_array[19] ^

1755

mac_array[18] ^ mac_array[16] ^ mac_array[14] ^

1756

mac_array[12] ^ mac_array[8] ^ mac_array[7] ^

1757

mac_array[6] ^ mac_array[0];

1758

1759

crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^

1760

mac_array[43] ^ mac_array[41] ^ mac_array[39] ^

1761

mac_array[36] ^ mac_array[34] ^ mac_array[32] ^

1762

mac_array[30] ^ mac_array[29] ^ mac_array[28] ^

1763

mac_array[24] ^ mac_array[23] ^ mac_array[22] ^

1764

mac_array[21] ^ mac_array[20] ^ mac_array[18] ^

1765

mac_array[17] ^ mac_array[16] ^ mac_array[15] ^

1766

mac_array[14] ^ mac_array[13] ^ mac_array[12] ^

1767

mac_array[9] ^ mac_array[6] ^ mac_array[1] ^

1768

mac_array[0];

1769

1770

crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^

1771

mac_array[43] ^ mac_array[42] ^ mac_array[39] ^

1772

mac_array[37] ^ mac_array[34] ^ mac_array[33] ^

1773

mac_array[29] ^ mac_array[28] ^ mac_array[25] ^

1774

mac_array[24] ^ mac_array[22] ^ mac_array[17] ^

1775

mac_array[15] ^ mac_array[13] ^ mac_array[12] ^

1776

mac_array[10] ^ mac_array[8] ^ mac_array[6] ^

1777

mac_array[2] ^ mac_array[1] ^ mac_array[0];

1778

1779

crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^

1780

mac_array[43] ^ mac_array[40] ^ mac_array[38] ^

1781

mac_array[35] ^ mac_array[34] ^ mac_array[30] ^

1782

mac_array[29] ^ mac_array[26] ^ mac_array[25] ^

1783

mac_array[23] ^ mac_array[18] ^ mac_array[16] ^

1784

mac_array[14] ^ mac_array[13] ^ mac_array[11] ^

1785

mac_array[9] ^ mac_array[7] ^ mac_array[3] ^

1786

mac_array[2] ^ mac_array[1];

1787

1788

crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^

1789

mac_array[41] ^ mac_array[39] ^ mac_array[36] ^

1790

mac_array[35] ^ mac_array[31] ^ mac_array[30] ^

1791

mac_array[27] ^ mac_array[26] ^ mac_array[24] ^

1792

mac_array[19] ^ mac_array[17] ^ mac_array[15] ^

1793

mac_array[14] ^ mac_array[12] ^ mac_array[10] ^

1794

mac_array[8] ^ mac_array[4] ^ mac_array[3] ^

1795

mac_array[2];

1796

1797

crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^

1798

mac_array[42] ^ mac_array[40] ^ mac_array[37] ^

1799

mac_array[36] ^ mac_array[32] ^ mac_array[31] ^

1800

mac_array[28] ^ mac_array[27] ^ mac_array[25] ^

1801

mac_array[20] ^ mac_array[18] ^ mac_array[16] ^

1802

mac_array[15] ^ mac_array[13] ^ mac_array[11] ^

1803

mac_array[9] ^ mac_array[5] ^ mac_array[4] ^

1804

mac_array[3];

1805

1806

crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^

1807

mac_array[41] ^ mac_array[38] ^ mac_array[37] ^

1808

mac_array[33] ^ mac_array[32] ^ mac_array[29] ^

1809

mac_array[28] ^ mac_array[26] ^ mac_array[21] ^

1810

mac_array[19] ^ mac_array[17] ^ mac_array[16] ^

1811

mac_array[14] ^ mac_array[12] ^ mac_array[10] ^

1812

mac_array[6] ^ mac_array[5] ^ mac_array[4];

1813

1814

crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^

1815

mac_array[39] ^ mac_array[38] ^ mac_array[34] ^

1816

mac_array[33] ^ mac_array[30] ^ mac_array[29] ^

1817

mac_array[27] ^ mac_array[22] ^ mac_array[20] ^

1818

mac_array[18] ^ mac_array[17] ^ mac_array[15] ^

1819

mac_array[13] ^ mac_array[11] ^ mac_array[7] ^

1820

mac_array[6] ^ mac_array[5];

1821

1822

for (i = 0; i < 8; i++)

1823

crc_result = crc_result | (crc[i] << i);

1824

1825

eth_port_omc_addr (eth_port_num, crc_result, queue, option);

1826

}

1827

return;

1828

}

1829

1830

/*******************************************************************************

1831

* eth_port_smc_addr - Special Multicast address settings.

1832

1833

* DESCRIPTION:

1834

* This routine controls the MV device special MAC multicast support.

1835

* The Special Multicast Table for MAC addresses supports MAC of the form

1836

* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).

1837

* The MAC DA[7:0] bits are used as a pointer to the Special Multicast

1838

* Table entries in the DA-Filter table.

1839

* This function set the Special Multicast Table appropriate entry

1840

* according to the argument given.

1841

1842

* INPUT:

1843

* ETH_PORT eth_port_num Port number.

1844

* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).

1845

* ETH_QUEUE queue Rx queue number for this MAC address.

1846

* int option 0 = Add, 1 = remove address.

1847

1848

* OUTPUT:

1849

* See description.

1850

1851

* RETURN:

1852

* true is output succeeded.

1853

* false if option parameter is invalid.

1854

1855

*******************************************************************************/

1856

static bool eth_port_smc_addr (ETH_PORT eth_port_num,

1857

unsigned char mc_byte,

1858

ETH_QUEUE queue, int option)

1859

{

1860

unsigned int smc_table_reg;

1861

unsigned int tbl_offset;

1862

unsigned int reg_offset;

1863

1864

/* Locate the SMC table entry */

1865

tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */

1866

reg_offset = mc_byte % 4; /* Entry offset within the above register */

1867

queue &= 0x7;

1868

1869

switch (option) {

1870

case REJECT_MAC_ADDR:

1871

/* Clear accepts frame bit at specified Special DA table entry */

1872

smc_table_reg =

1873

MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));

1874

smc_table_reg &= (0x0E << (8 * reg_offset));

1875

1876

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);

1877

break;

1878

1879

case ACCEPT_MAC_ADDR:

1880

/* Set accepts frame bit at specified Special DA table entry */

1881

smc_table_reg =

1882

MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));

1883

smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));

1884

1885

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);

1886

break;

1887

1888

default:

1889

return false;

1890

}

1891

return true;

1892

}

1893

1894

/*******************************************************************************

1895

* eth_port_omc_addr - Multicast address settings.

1896

1897

* DESCRIPTION:

1898

* This routine controls the MV device Other MAC multicast support.

1899

* The Other Multicast Table is used for multicast of another type.

1900

* A CRC-8bit is used as an index to the Other Multicast Table entries

1901

* in the DA-Filter table.

1902

* The function gets the CRC-8bit value from the calling routine and

1903

* set the Other Multicast Table appropriate entry according to the

1904

* CRC-8 argument given.

1905

1906

* INPUT:

1907

* ETH_PORT eth_port_num Port number.

1908

* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).

1909

* ETH_QUEUE queue Rx queue number for this MAC address.

1910

* int option 0 = Add, 1 = remove address.

1911

1912

* OUTPUT:

1913

* See description.

1914

1915

* RETURN:

1916

* true is output succeeded.

1917

* false if option parameter is invalid.

1918

1919

*******************************************************************************/

1920

static bool eth_port_omc_addr (ETH_PORT eth_port_num,

1921

unsigned char crc8,

1922

ETH_QUEUE queue, int option)

1923

{

1924

unsigned int omc_table_reg;

1925

unsigned int tbl_offset;

1926

unsigned int reg_offset;

1927

1928

/* Locate the OMC table entry */

1929

tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */

1930

reg_offset = crc8 % 4; /* Entry offset within the above register */

1931

queue &= 0x7;

1932

1933

switch (option) {

1934

case REJECT_MAC_ADDR:

1935

/* Clear accepts frame bit at specified Other DA table entry */

1936

omc_table_reg =

1937

MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));

1938

omc_table_reg &= (0x0E << (8 * reg_offset));

1939

1940

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);

1941

break;

1942

1943

case ACCEPT_MAC_ADDR:

1944

/* Set accepts frame bit at specified Other DA table entry */

1945

omc_table_reg =

1946

MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));

1947

omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));

1948

1949

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);

1950

break;

1951

1952

default:

1953

return false;

1954

}

1955

return true;

1956

}

1957

#endif

1958

1959

/*******************************************************************************

1960

* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables

1961

1962

* DESCRIPTION:

1963

* Go through all the DA filter tables (Unicast, Special Multicast & Other

1964

* Multicast) and set each entry to 0.

1965

1966

* INPUT:

1967

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

1968

1969

* OUTPUT:

1970

* Multicast and Unicast packets are rejected.

1971

1972

* RETURN:

1973

* None.

1974

1975

*******************************************************************************/

1976

static void eth_port_init_mac_tables (ETH_PORT eth_port_num)

1977

{

1978

int table_index;

1979

1980

/* Clear DA filter unicast table (Ex_dFUT) */

1981

for (table_index = 0; table_index <= 0xC; table_index += 4)

1982

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE

1983

(eth_port_num) + table_index), 0);

1984

1985

for (table_index = 0; table_index <= 0xFC; table_index += 4) {

1986

/* Clear DA filter special multicast table (Ex_dFSMT) */

1987

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);

1988

/* Clear DA filter other multicast table (Ex_dFOMT) */

1989

MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);

1990

}

1991

}

1992

1993

/*******************************************************************************

1994

* eth_clear_mib_counters - Clear all MIB counters

1995

1996

* DESCRIPTION:

1997

* This function clears all MIB counters of a specific ethernet port.

1998

* A read from the MIB counter will reset the counter.

1999

2000

* INPUT:

2001

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2002

2003

* OUTPUT:

2004

* After reading all MIB counters, the counters resets.

2005

2006

* RETURN:

2007

* MIB counter value.

2008

2009

*******************************************************************************/

2010

static void eth_clear_mib_counters (ETH_PORT eth_port_num)

2011

{

2012

int i;

2013

2014

/* Perform dummy reads from MIB counters */

2015

for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;

2016

i += 4)

2017

MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));

2018

2019

return;

2020

}

2021

2022

/*******************************************************************************

2023

* eth_read_mib_counter - Read a MIB counter

2024

2025

* DESCRIPTION:

2026

* This function reads a MIB counter of a specific ethernet port.

2027

* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the

2028

* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH

2029

* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and

2030

* ETH_MIB_GOOD_OCTETS_SENT_HIGH

2031

2032

* INPUT:

2033

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2034

* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).

2035

2036

* OUTPUT:

2037

* After reading the MIB counter, the counter resets.

2038

2039

* RETURN:

2040

* MIB counter value.

2041

2042

*******************************************************************************/

2043

unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,

2044

unsigned int mib_offset)

2045

{

2046

return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)

2047

+ mib_offset));

2048

}

2049

2050

/*******************************************************************************

2051

* ethernet_phy_set - Set the ethernet port PHY address.

2052

2053

* DESCRIPTION:

2054

* This routine set the ethernet port PHY address according to given

2055

* parameter.

2056

2057

* INPUT:

2058

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2059

2060

* OUTPUT:

2061

* Set PHY Address Register with given PHY address parameter.

2062

2063

* RETURN:

2064

* None.

2065

2066

*******************************************************************************/

2067

static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)

2068

{

2069

unsigned int reg_data;

2070

2071

reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);

2072

2073

reg_data &= ~(0x1F << (5 * eth_port_num));

2074

reg_data |= (phy_addr << (5 * eth_port_num));

2075

2076

MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);

2077

2078

return;

2079

}

2080

2081

/*******************************************************************************

2082

* ethernet_phy_get - Get the ethernet port PHY address.

2083

2084

* DESCRIPTION:

2085

* This routine returns the given ethernet port PHY address.

2086

2087

* INPUT:

2088

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2089

2090

* OUTPUT:

2091

* None.

2092

2093

* RETURN:

2094

* PHY address.

2095

2096

*******************************************************************************/

2097

static int ethernet_phy_get (ETH_PORT eth_port_num)

2098

{

2099

unsigned int reg_data;

2100

2101

reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);

2102

2103

return ((reg_data >> (5 * eth_port_num)) & 0x1f);

2104

}

2105

2106

/*******************************************************************************

2107

* ethernet_phy_reset - Reset Ethernet port PHY.

2108

2109

* DESCRIPTION:

2110

* This routine utilize the SMI interface to reset the ethernet port PHY.

2111

* The routine waits until the link is up again or link up is timeout.

2112

2113

* INPUT:

2114

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2115

2116

* OUTPUT:

2117

* The ethernet port PHY renew its link.

2118

2119

* RETURN:

2120

* None.

2121

2122

*******************************************************************************/

2123

static bool ethernet_phy_reset (ETH_PORT eth_port_num)

2124

{

2125

unsigned int time_out = 50;

2126

unsigned int phy_reg_data;

2127

2128

/* Reset the PHY */

2129

eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);

2130

phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */

2131

eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);

2132

2133

/* Poll on the PHY LINK */

2134

do {

2135

eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);

2136

2137

if (time_out-- == 0)

2138

return false;

2139

}

2140

while (!(phy_reg_data & 0x20));

2141

2142

return true;

2143

}

2144

2145

/*******************************************************************************

2146

* eth_port_reset - Reset Ethernet port

2147

2148

* DESCRIPTION:

2149

* This routine resets the chip by aborting any SDMA engine activity and

2150

* clearing the MIB counters. The Receiver and the Transmit unit are in

2151

* idle state after this command is performed and the port is disabled.

2152

2153

* INPUT:

2154

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2155

2156

* OUTPUT:

2157

* Channel activity is halted.

2158

2159

* RETURN:

2160

* None.

2161

2162

*******************************************************************************/

2163

static void eth_port_reset (ETH_PORT eth_port_num)

2164

{

2165

unsigned int reg_data;

2166

2167

/* Stop Tx port activity. Check port Tx activity. */

2168

reg_data =

2169

MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG

2170

(eth_port_num));

2171

2172

if (reg_data & 0xFF) {

2173

/* Issue stop command for active channels only */

2174

MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG

2175

(eth_port_num), (reg_data << 8));

2176

2177

/* Wait for all Tx activity to terminate. */

2178

do {

2179

/* Check port cause register that all Tx queues are stopped */

2180

reg_data =

2181

MV_REG_READ

2182

(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG

2183

(eth_port_num));

2184

}

2185

while (reg_data & 0xFF);

2186

}

2187

2188

/* Stop Rx port activity. Check port Rx activity. */

2189

reg_data =

2190

MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG

2191

(eth_port_num));

2192

2193

if (reg_data & 0xFF) {

2194

/* Issue stop command for active channels only */

2195

MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG

2196

(eth_port_num), (reg_data << 8));

2197

2198

/* Wait for all Rx activity to terminate. */

2199

do {

2200

/* Check port cause register that all Rx queues are stopped */

2201

reg_data =

2202

MV_REG_READ

2203

(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG

2204

(eth_port_num));

2205

}

2206

while (reg_data & 0xFF);

2207

}

2208

2209

2210

/* Clear all MIB counters */

2211

eth_clear_mib_counters (eth_port_num);

2212

2213

/* Reset the Enable bit in the Configuration Register */

2214

reg_data =

2215

MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG

2216

(eth_port_num));

2217

reg_data &= ~ETH_SERIAL_PORT_ENABLE;

2218

MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),

2219

reg_data);

2220

2221

return;

2222

}

2223

2224

#if 0 /* Not needed here */

2225

/*******************************************************************************

2226

* ethernet_set_config_reg - Set specified bits in configuration register.

2227

2228

* DESCRIPTION:

2229

* This function sets specified bits in the given ethernet

2230

* configuration register.

2231

2232

* INPUT:

2233

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2234

* unsigned int value 32 bit value.

2235

2236

* OUTPUT:

2237

* The set bits in the value parameter are set in the configuration

2238

* register.

2239

2240

* RETURN:

2241

* None.

2242

2243

*******************************************************************************/

2244

static void ethernet_set_config_reg (ETH_PORT eth_port_num,

2245

unsigned int value)

2246

{

2247

unsigned int eth_config_reg;

2248

2249

eth_config_reg =

2250

MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));

2251

eth_config_reg |= value;

2252

MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),

2253

eth_config_reg);

2254

2255

return;

2256

}

2257

#endif

2258

2259

#if 0 /* FIXME */

2260

/*******************************************************************************

2261

* ethernet_reset_config_reg - Reset specified bits in configuration register.

2262

2263

* DESCRIPTION:

2264

* This function resets specified bits in the given Ethernet

2265

* configuration register.

2266

2267

* INPUT:

2268

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2269

* unsigned int value 32 bit value.

2270

2271

* OUTPUT:

2272

* The set bits in the value parameter are reset in the configuration

2273

* register.

2274

2275

* RETURN:

2276

* None.

2277

2278

*******************************************************************************/

2279

static void ethernet_reset_config_reg (ETH_PORT eth_port_num,

2280

unsigned int value)

2281

{

2282

unsigned int eth_config_reg;

2283

2284

eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG

2285

(eth_port_num));

2286

eth_config_reg &= ~value;

2287

MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),

2288

eth_config_reg);

2289

2290

return;

2291

}

2292

#endif

2293

2294

#if 0 /* Not needed here */

2295

/*******************************************************************************

2296

* ethernet_get_config_reg - Get the port configuration register

2297

2298

* DESCRIPTION:

2299

* This function returns the configuration register value of the given

2300

* ethernet port.

2301

2302

* INPUT:

2303

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2304

2305

* OUTPUT:

2306

* None.

2307

2308

* RETURN:

2309

* Port configuration register value.

2310

2311

*******************************************************************************/

2312

static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)

2313

{

2314

unsigned int eth_config_reg;

2315

2316

eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG

2317

(eth_port_num));

2318

return eth_config_reg;

2319

}

2320

2321

#endif

2322

2323

/*******************************************************************************

2324

* eth_port_read_smi_reg - Read PHY registers

2325

2326

* DESCRIPTION:

2327

* This routine utilize the SMI interface to interact with the PHY in

2328

* order to perform PHY register read.

2329

2330

* INPUT:

2331

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2332

* unsigned int phy_reg PHY register address offset.

2333

* unsigned int *value Register value buffer.

2334

2335

* OUTPUT:

2336

* Write the value of a specified PHY register into given buffer.

2337

2338

* RETURN:

2339

* false if the PHY is busy or read data is not in valid state.

2340

* true otherwise.

2341

2342

*******************************************************************************/

2343

static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,

2344

unsigned int phy_reg, unsigned int *value)

2345

{

2346

unsigned int reg_value;

2347

unsigned int time_out = PHY_BUSY_TIMEOUT;

2348

int phy_addr;

2349

2350

phy_addr = ethernet_phy_get (eth_port_num);

2351

/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/

2352

2353

/* first check that it is not busy */

2354

do {

2355

reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);

2356

if (time_out-- == 0) {

2357

return false;

2358

}

2359

}

2360

while (reg_value & ETH_SMI_BUSY);

2361

2362

/* not busy */

2363

2364

MV_REG_WRITE (MV64460_ETH_SMI_REG,

2365

(phy_addr << 16) | (phy_reg << 21) |

2366

ETH_SMI_OPCODE_READ);

2367

2368

time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */

2369

2370

do {

2371

reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);

2372

if (time_out-- == 0) {

2373

return false;

2374

}

2375

}

2376

while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */

2377

2378

/* Wait for the data to update in the SMI register */

2379

#define PHY_UPDATE_TIMEOUT 10000

2380

for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);

2381

2382

reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);

2383

2384

*value = reg_value & 0xffff;

2385

2386

return true;

2387

}

2388

2389

/*******************************************************************************

2390

* eth_port_write_smi_reg - Write to PHY registers

2391

2392

* DESCRIPTION:

2393

* This routine utilize the SMI interface to interact with the PHY in

2394

* order to perform writes to PHY registers.

2395

2396

* INPUT:

2397

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2398

* unsigned int phy_reg PHY register address offset.

2399

* unsigned int value Register value.

2400

2401

* OUTPUT:

2402

* Write the given value to the specified PHY register.

2403

2404

* RETURN:

2405

* false if the PHY is busy.

2406

* true otherwise.

2407

2408

*******************************************************************************/

2409

static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,

2410

unsigned int phy_reg, unsigned int value)

2411

{

2412

unsigned int reg_value;

2413

unsigned int time_out = PHY_BUSY_TIMEOUT;

2414

int phy_addr;

2415

2416

phy_addr = ethernet_phy_get (eth_port_num);

2417

2418

/* first check that it is not busy */

2419

do {

2420

reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);

2421

if (time_out-- == 0) {

2422

return false;

2423

}

2424

}

2425

while (reg_value & ETH_SMI_BUSY);

2426

2427

/* not busy */

2428

MV_REG_WRITE (MV64460_ETH_SMI_REG,

2429

(phy_addr << 16) | (phy_reg << 21) |

2430

ETH_SMI_OPCODE_WRITE | (value & 0xffff));

2431

return true;

2432

}

2433

2434

/*******************************************************************************

2435

* eth_set_access_control - Config address decode parameters for Ethernet unit

2436

2437

* DESCRIPTION:

2438

* This function configures the address decode parameters for the Gigabit

2439

* Ethernet Controller according the given parameters struct.

2440

2441

* INPUT:

2442

* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.

2443

* ETH_WIN_PARAM *param Address decode parameter struct.

2444

2445

* OUTPUT:

2446

* An access window is opened using the given access parameters.

2447

2448

* RETURN:

2449

* None.

2450

2451

*******************************************************************************/

2452

static void eth_set_access_control (ETH_PORT eth_port_num,

2453

ETH_WIN_PARAM * param)

2454

{

2455

unsigned int access_prot_reg;

2456

2457

/* Set access control register */

2458

access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG

2459

(eth_port_num));

2460

access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */

2461

access_prot_reg |= (param->access_ctrl << (param->win * 2));

2462

MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),

2463

access_prot_reg);

2464

2465

/* Set window Size reg (SR) */

2466

MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +

2467

(ETH_SIZE_REG_GAP * param->win)),

2468

(((param->size / 0x10000) - 1) << 16));

2469

2470

/* Set window Base address reg (BA) */

2471

MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),

2472

(param->target | param->attributes | param->base_addr));

2473

/* High address remap reg (HARR) */

2474

if (param->win < 4)

2475

MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +

2476

(ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),

2477

param->high_addr);

2478

2479

/* Base address enable reg (BARER) */

2480

if (param->enable == 1)

2481

MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,

2482

(1 << param->win));

2483

else

2484

MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,

2485

(1 << param->win));

2486

}

2487

2488

/*******************************************************************************

2489

* ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.

2490

2491

* DESCRIPTION:

2492

* This function prepares a Rx chained list of descriptors and packet

2493

* buffers in a form of a ring. The routine must be called after port

2494

* initialization routine and before port start routine.

2495

* The Ethernet SDMA engine uses CPU bus addresses to access the various

2496

* devices in the system (i.e. DRAM). This function uses the ethernet

2497

* struct 'virtual to physical' routine (set by the user) to set the ring

2498

* with physical addresses.

2499

2500

* INPUT:

2501

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.

2502

* ETH_QUEUE rx_queue Number of Rx queue.

2503

* int rx_desc_num Number of Rx descriptors

2504

* int rx_buff_size Size of Rx buffer

2505

* unsigned int rx_desc_base_addr Rx descriptors memory area base addr.

2506

* unsigned int rx_buff_base_addr Rx buffer memory area base addr.

2507

2508

* OUTPUT:

2509

* The routine updates the Ethernet port control struct with information

2510

* regarding the Rx descriptors and buffers.

2511

2512

* RETURN:

2513

* false if the given descriptors memory area is not aligned according to

2514

* Ethernet SDMA specifications.

2515

* true otherwise.

2516

2517

*******************************************************************************/

2518

static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,

2519

ETH_QUEUE rx_queue,

2520

int rx_desc_num,

2521

int rx_buff_size,

2522

unsigned int rx_desc_base_addr,

2523

unsigned int rx_buff_base_addr)

2524

{

2525

ETH_RX_DESC *p_rx_desc;

2526

ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */

2527

unsigned int buffer_addr;

2528

int ix; /* a counter */

2529

2530

2531

p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;

2532

p_rx_prev_desc = p_rx_desc;

2533

buffer_addr = rx_buff_base_addr;

2534

2535

/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */

2536

if (rx_buff_base_addr & 0xF)

2537

return false;

2538

2539

/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */

2540

if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))

2541

return false;

2542

2543

/* Rx buffers must be 64-bit aligned. */

2544

if ((rx_buff_base_addr + rx_buff_size) & 0x7)

2545

return false;

2546

2547

/* initialize the Rx descriptors ring */

2548

for (ix = 0; ix < rx_desc_num; ix++) {

2549

p_rx_desc->buf_size = rx_buff_size;

2550

p_rx_desc->byte_cnt = 0x0000;

2551

p_rx_desc->cmd_sts =

2552

ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;

2553

p_rx_desc->next_desc_ptr =

2554

((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;

2555

p_rx_desc->buf_ptr = buffer_addr;

2556

p_rx_desc->return_info = 0x00000000;

2557

D_CACHE_FLUSH_LINE (p_rx_desc, 0);

2558

buffer_addr += rx_buff_size;

2559

p_rx_prev_desc = p_rx_desc;

2560

p_rx_desc = (ETH_RX_DESC *)

2561

((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);

2562

}

2563

2564

/* Closing Rx descriptors ring */

2565

p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);

2566

D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);

2567

2568

/* Save Rx desc pointer to driver struct. */

2569

CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);

2570

USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);

2571

2572

p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =

2573

(ETH_RX_DESC *) rx_desc_base_addr;

2574

p_eth_port_ctrl->rx_desc_area_size[rx_queue] =

2575

rx_desc_num * RX_DESC_ALIGNED_SIZE;

2576

2577

p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);

2578

2579

return true;

2580

}

2581

2582

/*******************************************************************************

2583

* ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.

2584

2585

* DESCRIPTION:

2586

* This function prepares a Tx chained list of descriptors and packet

2587

* buffers in a form of a ring. The routine must be called after port

2588

* initialization routine and before port start routine.

2589

* The Ethernet SDMA engine uses CPU bus addresses to access the various

2590

* devices in the system (i.e. DRAM). This function uses the ethernet

2591

* struct 'virtual to physical' routine (set by the user) to set the ring

2592

* with physical addresses.

2593

2594

* INPUT:

2595

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.

2596

* ETH_QUEUE tx_queue Number of Tx queue.

2597

* int tx_desc_num Number of Tx descriptors

2598

* int tx_buff_size Size of Tx buffer

2599

* unsigned int tx_desc_base_addr Tx descriptors memory area base addr.

2600

* unsigned int tx_buff_base_addr Tx buffer memory area base addr.

2601

2602

* OUTPUT:

2603

* The routine updates the Ethernet port control struct with information

2604

* regarding the Tx descriptors and buffers.

2605

2606

* RETURN:

2607

* false if the given descriptors memory area is not aligned according to

2608

* Ethernet SDMA specifications.

2609

* true otherwise.

2610

2611

*******************************************************************************/

2612

static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,

2613

ETH_QUEUE tx_queue,

2614

int tx_desc_num,

2615

int tx_buff_size,

2616

unsigned int tx_desc_base_addr,

2617

unsigned int tx_buff_base_addr)

2618

{

2619

2620

ETH_TX_DESC *p_tx_desc;

2621

ETH_TX_DESC *p_tx_prev_desc;

2622

unsigned int buffer_addr;

2623

int ix; /* a counter */

2624

2625

2626

/* save the first desc pointer to link with the last descriptor */

2627

p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;

2628

p_tx_prev_desc = p_tx_desc;

2629

buffer_addr = tx_buff_base_addr;

2630

2631

/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */

2632

if (tx_buff_base_addr & 0xF)

2633

return false;

2634

2635

/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */

2636

if ((tx_buff_size > TX_BUFFER_MAX_SIZE)

2637

|| (tx_buff_size < TX_BUFFER_MIN_SIZE))

2638

return false;

2639

2640

/* Initialize the Tx descriptors ring */

2641

for (ix = 0; ix < tx_desc_num; ix++) {

2642

p_tx_desc->byte_cnt = 0x0000;

2643

p_tx_desc->l4i_chk = 0x0000;

2644

p_tx_desc->cmd_sts = 0x00000000;

2645

p_tx_desc->next_desc_ptr =

2646

((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;

2647

2648

p_tx_desc->buf_ptr = buffer_addr;

2649

p_tx_desc->return_info = 0x00000000;

2650

D_CACHE_FLUSH_LINE (p_tx_desc, 0);

2651

buffer_addr += tx_buff_size;

2652

p_tx_prev_desc = p_tx_desc;

2653

p_tx_desc = (ETH_TX_DESC *)

2654

((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);

2655

2656

}

2657

/* Closing Tx descriptors ring */

2658

p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;

2659

D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);

2660

/* Set Tx desc pointer in driver struct. */

2661

CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);

2662

USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);

2663

2664

/* Init Tx ring base and size parameters */

2665

p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =

2666

(ETH_TX_DESC *) tx_desc_base_addr;

2667

p_eth_port_ctrl->tx_desc_area_size[tx_queue] =

2668

(tx_desc_num * TX_DESC_ALIGNED_SIZE);

2669

2670

/* Add the queue to the list of Tx queues of this port */

2671

p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);

2672

2673

return true;

2674

}

2675

2676

/*******************************************************************************

2677

* eth_port_send - Send an Ethernet packet

2678

2679

* DESCRIPTION:

2680

* This routine send a given packet described by p_pktinfo parameter. It

2681

* supports transmitting of a packet spaned over multiple buffers. The

2682

* routine updates 'curr' and 'first' indexes according to the packet

2683

* segment passed to the routine. In case the packet segment is first,

2684

* the 'first' index is update. In any case, the 'curr' index is updated.

2685

* If the routine get into Tx resource error it assigns 'curr' index as

2686

* 'first'. This way the function can abort Tx process of multiple

2687

* descriptors per packet.

2688

2689

* INPUT:

2690

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.

2691

* ETH_QUEUE tx_queue Number of Tx queue.

2692

* PKT_INFO *p_pkt_info User packet buffer.

2693

2694

* OUTPUT:

2695

* Tx ring 'curr' and 'first' indexes are updated.

2696

2697

* RETURN:

2698

* ETH_QUEUE_FULL in case of Tx resource error.

2699

* ETH_ERROR in case the routine can not access Tx desc ring.

2700

* ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.

2701

* ETH_OK otherwise.

2702

2703

*******************************************************************************/

2704

static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,

2705

ETH_QUEUE tx_queue,

2706

PKT_INFO * p_pkt_info)

2707

{

2708

volatile ETH_TX_DESC *p_tx_desc_first;

2709

volatile ETH_TX_DESC *p_tx_desc_curr;

2710

volatile ETH_TX_DESC *p_tx_next_desc_curr;

2711

volatile ETH_TX_DESC *p_tx_desc_used;

2712

unsigned int command_status;

2713

2714

/* Do not process Tx ring in case of Tx ring resource error */

2715

if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)

2716

return ETH_QUEUE_FULL;

2717

2718

/* Get the Tx Desc ring indexes */

2719

CURR_TFD_GET (p_tx_desc_curr, tx_queue);

2720

USED_TFD_GET (p_tx_desc_used, tx_queue);

2721

2722

if (p_tx_desc_curr == NULL)

2723

return ETH_ERROR;

2724

2725

/* The following parameters are used to save readings from memory */

2726

p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);

2727

command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;

2728

2729

if (command_status & (ETH_TX_FIRST_DESC)) {

2730

/* Update first desc */

2731

FIRST_TFD_SET (p_tx_desc_curr, tx_queue);

2732

p_tx_desc_first = p_tx_desc_curr;

2733

} else {

2734

FIRST_TFD_GET (p_tx_desc_first, tx_queue);

2735

command_status |= ETH_BUFFER_OWNED_BY_DMA;

2736

}

2737

2738

/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */

2739

/* boundary. We use the memory allocated for Tx descriptor. This memory */

2740

/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */

2741

if (p_pkt_info->byte_cnt <= 8) {

2742

printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */

2743

return ETH_ERROR;

2744

2745

p_tx_desc_curr->buf_ptr =

2746

(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;

2747

eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,

2748

p_pkt_info->byte_cnt);

2749

} else

2750

p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;

2751

2752

p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;

2753

p_tx_desc_curr->return_info = p_pkt_info->return_info;

2754

2755

if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {

2756

/* Set last desc with DMA ownership and interrupt enable. */

2757

p_tx_desc_curr->cmd_sts = command_status |

2758

ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;

2759

2760

if (p_tx_desc_curr != p_tx_desc_first)

2761

p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;

2762

2763

/* Flush CPU pipe */

2764

2765

D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);

2766

D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);

2767

CPU_PIPE_FLUSH;

2768

2769

/* Apply send command */

2770

ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);

2771

2772

/* Finish Tx packet. Update first desc in case of Tx resource error */

2773

p_tx_desc_first = p_tx_next_desc_curr;

2774

FIRST_TFD_SET (p_tx_desc_first, tx_queue);

2775

2776

} else {

2777

p_tx_desc_curr->cmd_sts = command_status;

2778

D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);

2779

}

2780

2781

/* Check for ring index overlap in the Tx desc ring */

2782

if (p_tx_next_desc_curr == p_tx_desc_used) {

2783

/* Update the current descriptor */

2784

CURR_TFD_SET (p_tx_desc_first, tx_queue);

2785

2786

p_eth_port_ctrl->tx_resource_err[tx_queue] = true;

2787

return ETH_QUEUE_LAST_RESOURCE;

2788

} else {

2789

/* Update the current descriptor */

2790

CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);

2791

return ETH_OK;

2792

}

2793

}

2794

2795

/*******************************************************************************

2796

* eth_tx_return_desc - Free all used Tx descriptors

2797

2798

* DESCRIPTION:

2799

* This routine returns the transmitted packet information to the caller.

2800

* It uses the 'first' index to support Tx desc return in case a transmit

2801

* of a packet spanned over multiple buffer still in process.

2802

* In case the Tx queue was in "resource error" condition, where there are

2803

* no available Tx resources, the function resets the resource error flag.

2804

2805

* INPUT:

2806

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.

2807

* ETH_QUEUE tx_queue Number of Tx queue.

2808

* PKT_INFO *p_pkt_info User packet buffer.

2809

2810

* OUTPUT:

2811

* Tx ring 'first' and 'used' indexes are updated.

2812

2813

* RETURN:

2814

* ETH_ERROR in case the routine can not access Tx desc ring.

2815

* ETH_RETRY in case there is transmission in process.

2816

* ETH_END_OF_JOB if the routine has nothing to release.

2817

* ETH_OK otherwise.

2818

2819

*******************************************************************************/

2820

static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *

2821

p_eth_port_ctrl,

2822

ETH_QUEUE tx_queue,

2823

PKT_INFO * p_pkt_info)

2824

{

2825

volatile ETH_TX_DESC *p_tx_desc_used = NULL;

2826

volatile ETH_TX_DESC *p_tx_desc_first = NULL;

2827

unsigned int command_status;

2828

2829

2830

/* Get the Tx Desc ring indexes */

2831

USED_TFD_GET (p_tx_desc_used, tx_queue);

2832

FIRST_TFD_GET (p_tx_desc_first, tx_queue);

2833

2834

2835

/* Sanity check */

2836

if (p_tx_desc_used == NULL)

2837

return ETH_ERROR;

2838

2839

command_status = p_tx_desc_used->cmd_sts;

2840

2841

/* Still transmitting... */

2842

if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {

2843

D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);

2844

return ETH_RETRY;

2845

}

2846

2847

/* Stop release. About to overlap the current available Tx descriptor */

2848

if ((p_tx_desc_used == p_tx_desc_first) &&

2849

(p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {

2850

D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);

2851

return ETH_END_OF_JOB;

2852

}

2853

2854

/* Pass the packet information to the caller */

2855

p_pkt_info->cmd_sts = command_status;

2856

p_pkt_info->return_info = p_tx_desc_used->return_info;

2857

p_tx_desc_used->return_info = 0;

2858

2859

/* Update the next descriptor to release. */

2860

USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);

2861

2862

/* Any Tx return cancels the Tx resource error status */

2863

if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)

2864

p_eth_port_ctrl->tx_resource_err[tx_queue] = false;

2865

2866

D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);

2867

2868

return ETH_OK;

2869

2870

}

2871

2872

/*******************************************************************************

2873

* eth_port_receive - Get received information from Rx ring.

2874

2875

* DESCRIPTION:

2876

* This routine returns the received data to the caller. There is no

2877

* data copying during routine operation. All information is returned

2878

* using pointer to packet information struct passed from the caller.

2879

* If the routine exhausts Rx ring resources then the resource error flag

2880

* is set.

2881

2882

* INPUT:

2883

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.

2884

* ETH_QUEUE rx_queue Number of Rx queue.

2885

* PKT_INFO *p_pkt_info User packet buffer.

2886

2887

* OUTPUT:

2888

* Rx ring current and used indexes are updated.

2889

2890

* RETURN:

2891

* ETH_ERROR in case the routine can not access Rx desc ring.

2892

* ETH_QUEUE_FULL if Rx ring resources are exhausted.

2893

* ETH_END_OF_JOB if there is no received data.

2894

* ETH_OK otherwise.

2895

2896

*******************************************************************************/

2897

static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,

2898

ETH_QUEUE rx_queue,

2899

PKT_INFO * p_pkt_info)

2900

{

2901

volatile ETH_RX_DESC *p_rx_curr_desc;

2902

volatile ETH_RX_DESC *p_rx_next_curr_desc;

2903

volatile ETH_RX_DESC *p_rx_used_desc;

2904

unsigned int command_status;

2905

2906

/* Do not process Rx ring in case of Rx ring resource error */

2907

if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {

2908

printf ("\nRx Queue is full ...\n");

2909

return ETH_QUEUE_FULL;

2910

}

2911

2912

/* Get the Rx Desc ring 'curr and 'used' indexes */

2913

CURR_RFD_GET (p_rx_curr_desc, rx_queue);

2914

USED_RFD_GET (p_rx_used_desc, rx_queue);

2915

2916

/* Sanity check */

2917

if (p_rx_curr_desc == NULL)

2918

return ETH_ERROR;

2919

2920

/* The following parameters are used to save readings from memory */

2921

p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);

2922

command_status = p_rx_curr_desc->cmd_sts;

2923

2924

/* Nothing to receive... */

2925

if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {

2926

/* DP(printf("Rx: command_status: %08x\n", command_status)); */

2927

D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);

2928

/* DP(printf("\nETH_END_OF_JOB ...\n"));*/

2929

return ETH_END_OF_JOB;

2930

}

2931

2932

p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;

2933

p_pkt_info->cmd_sts = command_status;

2934

p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;

2935

p_pkt_info->return_info = p_rx_curr_desc->return_info;

2936

p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */

2937

2938

/* Clean the return info field to indicate that the packet has been */

2939

/* moved to the upper layers */

2940

p_rx_curr_desc->return_info = 0;

2941

2942

/* Update 'curr' in data structure */

2943

CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);

2944

2945

/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */

2946

if (p_rx_next_curr_desc == p_rx_used_desc)

2947

p_eth_port_ctrl->rx_resource_err[rx_queue] = true;

2948

2949

D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);

2950

CPU_PIPE_FLUSH;

2951

return ETH_OK;

2952

}

2953

2954

/*******************************************************************************

2955

* eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.

2956

2957

* DESCRIPTION:

2958

* This routine returns a Rx buffer back to the Rx ring. It retrieves the

2959

* next 'used' descriptor and attached the returned buffer to it.

2960

* In case the Rx ring was in "resource error" condition, where there are

2961

* no available Rx resources, the function resets the resource error flag.

2962

2963

* INPUT:

2964

* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.

2965

* ETH_QUEUE rx_queue Number of Rx queue.

2966

* PKT_INFO *p_pkt_info Information on the returned buffer.

2967

2968

* OUTPUT:

2969

* New available Rx resource in Rx descriptor ring.

2970

2971

* RETURN:

2972

* ETH_ERROR in case the routine can not access Rx desc ring.

2973

* ETH_OK otherwise.

2974

2975

*******************************************************************************/

2976

static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *

2977

p_eth_port_ctrl,

2978

ETH_QUEUE rx_queue,

2979

PKT_INFO * p_pkt_info)

2980

{

2981

volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */

2982

2983

/* Get 'used' Rx descriptor */

2984

USED_RFD_GET (p_used_rx_desc, rx_queue);

2985

2986

/* Sanity check */

2987

if (p_used_rx_desc == NULL)

2988

return ETH_ERROR;

2989

2990

p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;

2991

p_used_rx_desc->return_info = p_pkt_info->return_info;

2992

p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;

2993

p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */

2994

2995

/* Flush the write pipe */

2996

CPU_PIPE_FLUSH;

2997

2998

/* Return the descriptor to DMA ownership */

2999

p_used_rx_desc->cmd_sts =

3000

ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;

3001

3002

/* Flush descriptor and CPU pipe */

3003

D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);

3004

CPU_PIPE_FLUSH;

3005

3006

/* Move the used descriptor pointer to the next descriptor */

3007

USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);

3008

3009

/* Any Rx return cancels the Rx resource error status */

3010

if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)

3011

p_eth_port_ctrl->rx_resource_err[rx_queue] = false;

3012

3013

return ETH_OK;

3014

}

3015

3016

/*******************************************************************************

3017

* eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path

3018

3019

* DESCRIPTION:

3020

* This routine sets the RX coalescing interrupt mechanism parameter.

3021

* This parameter is a timeout counter, that counts in 64 t_clk

3022

* chunks ; that when timeout event occurs a maskable interrupt

3023

* occurs.

3024

* The parameter is calculated using the tClk of the MV-643xx chip

3025

* , and the required delay of the interrupt in usec.

3026

3027

* INPUT:

3028

* ETH_PORT eth_port_num Ethernet port number

3029

* unsigned int t_clk t_clk of the MV-643xx chip in HZ units

3030

* unsigned int delay Delay in usec

3031

3032

* OUTPUT:

3033

* Interrupt coalescing mechanism value is set in MV-643xx chip.

3034

3035

* RETURN:

3036

* The interrupt coalescing value set in the gigE port.

3037

3038

*******************************************************************************/

3039

#if 0 /* FIXME */

3040

static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,

3041

unsigned int t_clk,

3042

unsigned int delay)

3043

{

3044

unsigned int coal;

3045

3046

coal = ((t_clk / 1000000) * delay) / 64;

3047

/* Set RX Coalescing mechanism */

3048

MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),

3049

((coal & 0x3fff) << 8) |

3050

(MV_REG_READ

3051

(MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))

3052

& 0xffc000ff));

3053

return coal;

3054

}

3055

3056

#endif

3057

/*******************************************************************************

3058

* eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path

3059

3060

* DESCRIPTION:

3061

* This routine sets the TX coalescing interrupt mechanism parameter.

3062

* This parameter is a timeout counter, that counts in 64 t_clk

3063

* chunks ; that when timeout event occurs a maskable interrupt

3064

* occurs.

3065

* The parameter is calculated using the t_cLK frequency of the

3066

* MV-643xx chip and the required delay in the interrupt in uSec

3067

3068

* INPUT:

3069

* ETH_PORT eth_port_num Ethernet port number

3070

* unsigned int t_clk t_clk of the MV-643xx chip in HZ units

3071

* unsigned int delay Delay in uSeconds

3072

3073

* OUTPUT:

3074

* Interrupt coalescing mechanism value is set in MV-643xx chip.

3075

3076

* RETURN:

3077

* The interrupt coalescing value set in the gigE port.

3078

3079

*******************************************************************************/

3080

#if 0 /* FIXME */

3081

static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,

3082

unsigned int t_clk,

3083

unsigned int delay)

3084

{

3085

unsigned int coal;

3086

3087

coal = ((t_clk / 1000000) * delay) / 64;

3088

/* Set TX Coalescing mechanism */

3089

MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),

3090

coal << 4);

3091

return coal;

3092

}

3093

#endif

3094

3095

/*******************************************************************************

3096

* eth_b_copy - Copy bytes from source to destination

3097

3098

* DESCRIPTION:

3099

* This function supports the eight bytes limitation on Tx buffer size.

3100

* The routine will zero eight bytes starting from the destination address

3101

* followed by copying bytes from the source address to the destination.

3102

3103

* INPUT:

3104

* unsigned int src_addr 32 bit source address.

3105

* unsigned int dst_addr 32 bit destination address.

3106

* int byte_count Number of bytes to copy.

3107

3108

* OUTPUT:

3109

* See description.

3110

3111

* RETURN:

3112

* None.

3113

3114

*******************************************************************************/

3115

static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,

3116

int byte_count)

3117

{

3118

/* Zero the dst_addr area */

3119

*(unsigned int *) dst_addr = 0x0;

3120

3121

while (byte_count != 0) {

3122

*(char *) dst_addr = *(char *) src_addr;

3123

dst_addr++;

3124

src_addr++;

3125

byte_count--;

3126

}

3127

}

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