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* Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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FILE_LICENCE ( GPL2_OR_LATER );
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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* Set the number of Tx and Rx buffers, using Log_2(# buffers).
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* Set default values to 16 Tx buffers and 32 Rx buffers.
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#define PCNET32_LOG_TX_BUFFERS 4
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#define PCNET32_LOG_RX_BUFFERS 5
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/* Maximum number of descriptor rings is 512 */
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#define PCNET32_LOG_MAX_TX_BUFFERS 9
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#define PCNET32_LOG_MAX_RX_BUFFERS 9
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#define TX_RING_SIZE ( 1 << ( PCNET32_LOG_TX_BUFFERS ) )
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#define TX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_TX_BUFFERS ) )
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#define RX_RING_SIZE ( 1 << ( PCNET32_LOG_RX_BUFFERS ) )
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#define RX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_RX_BUFFERS ) )
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#define RX_RING_BYTES ( RX_RING_SIZE * sizeof(struct pcnet32_rx_desc ) )
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#define TX_RING_BYTES ( TX_RING_SIZE * sizeof(struct pcnet32_tx_desc ) )
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#define PKT_BUF_SIZE 1536
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#define RX_RING_ALIGN 16
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#define TX_RING_ALIGN 16
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#define INIT_BLOCK_ALIGN 32
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#define PCNET32_WIO_RDP 0x10
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#define PCNET32_WIO_RAP 0x12
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#define PCNET32_WIO_RESET 0x14
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#define PCNET32_WIO_BDP 0x16
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#define PCNET32_DWIO_RDP 0x10
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#define PCNET32_DWIO_RAP 0x14
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#define PCNET32_DWIO_RESET 0x18
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#define PCNET32_DWIO_BDP 0x1C
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#define PCNET32_PORT_AUI 0x00
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#define PCNET32_PORT_10BT 0x01
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#define PCNET32_PORT_GPSI 0x02
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#define PCNET32_PORT_MII 0x03
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#define PCNET32_PORT_PORTSEL 0x03
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#define PCNET32_PORT_ASEL 0x04
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#define PCNET32_PORT_100 0x40
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#define PCNET32_PORT_FD 0x80
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#define PCNET32_SWSTYLE_LANCE 0x00
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#define PCNET32_SWSTYLE_ILACC 0x01
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#define PCNET32_SWSTYLE_PCNET32 0x02
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#define PCNET32_MAX_PHYS 32
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#ifndef PCI_VENDOR_ID_AT
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#define PCI_VENDOR_ID_AT 0x1259
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#ifndef PCI_SUBDEVICE_ID_AT_2700FX
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#define PCI_SUBDEVICE_ID_AT_2700FX 0x2701
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#ifndef PCI_SUBDEVICE_ID_AT_2701FX
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#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703
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struct pcnet32_rx_desc {
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struct pcnet32_tx_desc {
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struct pcnet32_init_block {
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struct pcnet32_access {
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u16 ( *read_csr ) ( unsigned long, int );
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void ( *write_csr ) ( unsigned long, int, u16 );
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u16 ( *read_bcr ) ( unsigned long, int );
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void ( *write_bcr ) ( unsigned long, int, u16 );
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u16 ( *read_rap ) ( unsigned long );
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void ( *write_rap ) ( unsigned long, u16 );
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void ( *reset ) ( unsigned long );
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struct pcnet32_private {
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struct pcnet32_init_block init_block __attribute__((aligned(32)));
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struct pci_device *pci_dev;
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struct net_device *netdev;
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struct io_buffer *rx_iobuf[RX_RING_SIZE];
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struct io_buffer *tx_iobuf[TX_RING_SIZE];
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struct pcnet32_rx_desc *rx_base;
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struct pcnet32_tx_desc *tx_base;
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uint32_t tx_fill_ctr;
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struct pcnet32_access *a;
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unsigned short chip_version;
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enum pcnet32_desc_status_bit {
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StartOfPacket = (1 << 9),
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EndOfPacket = (1 << 8)
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enum pcnet32_register_content {
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/* CSR0 bits - Controller status register */
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IntEnable = (1 << 6),
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/* CSR3 bits - Controller status register */
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BablMask = (1 << 14),
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MissFrameMask = (1 << 12),
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MemErrMask = (1 << 11),
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RxIntMask = (1 << 10),
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TxIntMask = (1 << 9),
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InitDoneMask = (1 << 8)
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#endif /* _PCNET32_H_ */