← Back to branch summary

~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

« back to all changes in this revision

Viewing changes to roms/skiboot/core/pci-opal.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

Show diffs side-by-side

added added

removed removed

Lines of Context:
roms/skiboot/core/pci-opal.c
 
1
/* Copyright 2013-2014 IBM Corp.
 
2
 *
 
3
 * Licensed under the Apache License, Version 2.0 (the "License");
 
4
 * you may not use this file except in compliance with the License.
 
5
 * You may obtain a copy of the License at
 
6
 *
 
7
 *      http://www.apache.org/licenses/LICENSE-2.0
 
8
 *
 
9
 * Unless required by applicable law or agreed to in writing, software
 
10
 * distributed under the License is distributed on an "AS IS" BASIS,
 
11
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
 
12
 * implied.
 
13
 * See the License for the specific language governing permissions and
 
14
 * limitations under the License.
 
15
 */
 
16
 
 
17
#include <skiboot.h>
 
18
#include <opal-api.h>
 
19
#include <pci.h>
 
20
#include <pci-cfg.h>
 
21
#include <pci-slot.h>
 
22
#include <opal-msg.h>
 
23
#include <timebase.h>
 
24
#include <timer.h>
 
25
 
 
26
#define OPAL_PCICFG_ACCESS(op, cb, type)        \
 
27
static int64_t opal_pci_config_##op(uint64_t phb_id,                    \
 
28
                                    uint64_t bus_dev_func,              \
 
29
                                    uint64_t offset, type data)         \
 
30
{                                                                       \
 
31
        struct phb *phb = pci_get_phb(phb_id);                          \
 
32
        int64_t rc;                                                     \
 
33
                                                                        \
 
34
        if (!phb)                                                       \
 
35
                return OPAL_PARAMETER;                                  \
 
36
        phb_lock(phb);                                          \
 
37
        rc = phb->ops->cfg_##cb(phb, bus_dev_func, offset, data);       \
 
38
        phb_unlock(phb);                                                \
 
39
                                                                        \
 
40
        return rc;                                                      \
 
41
}
 
42
 
 
43
OPAL_PCICFG_ACCESS(read_byte,           read8, uint8_t *)
 
44
OPAL_PCICFG_ACCESS(read_half_word,      read16, uint16_t *)
 
45
OPAL_PCICFG_ACCESS(read_word,           read32, uint32_t *)
 
46
OPAL_PCICFG_ACCESS(write_byte,          write8, uint8_t)
 
47
OPAL_PCICFG_ACCESS(write_half_word,     write16, uint16_t)
 
48
OPAL_PCICFG_ACCESS(write_word,          write32, uint32_t)
 
49
 
 
50
opal_call(OPAL_PCI_CONFIG_READ_BYTE, opal_pci_config_read_byte, 4);
 
51
opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, opal_pci_config_read_half_word, 4);
 
52
opal_call(OPAL_PCI_CONFIG_READ_WORD, opal_pci_config_read_word, 4);
 
53
opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, opal_pci_config_write_byte, 4);
 
54
opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, opal_pci_config_write_half_word, 4);
 
55
opal_call(OPAL_PCI_CONFIG_WRITE_WORD, opal_pci_config_write_word, 4);
 
56
 
 
57
static struct lock opal_eeh_evt_lock = LOCK_UNLOCKED;
 
58
static uint64_t opal_eeh_evt = 0;
 
59
 
 
60
void opal_pci_eeh_set_evt(uint64_t phb_id)
 
61
{
 
62
        lock(&opal_eeh_evt_lock);
 
63
        opal_eeh_evt |= 1ULL << phb_id;
 
64
        opal_update_pending_evt(OPAL_EVENT_PCI_ERROR, OPAL_EVENT_PCI_ERROR);
 
65
        unlock(&opal_eeh_evt_lock);
 
66
}
 
67
 
 
68
void opal_pci_eeh_clear_evt(uint64_t phb_id)
 
69
{
 
70
        lock(&opal_eeh_evt_lock);
 
71
        opal_eeh_evt &= ~(1ULL << phb_id);
 
72
        if (!opal_eeh_evt)
 
73
                opal_update_pending_evt(OPAL_EVENT_PCI_ERROR, 0);
 
74
        unlock(&opal_eeh_evt_lock);
 
75
}
 
76
 
 
77
static int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 
78
                                          uint8_t *freeze_state,
 
79
                                          uint16_t *pci_error_type,
 
80
                                          uint64_t *phb_status)
 
81
{
 
82
        struct phb *phb = pci_get_phb(phb_id);
 
83
        int64_t rc;
 
84
 
 
85
        if (!phb)
 
86
                return OPAL_PARAMETER;
 
87
        if (!phb->ops->eeh_freeze_status)
 
88
                return OPAL_UNSUPPORTED;
 
89
        phb_lock(phb);
 
90
        rc = phb->ops->eeh_freeze_status(phb, pe_number, freeze_state,
 
91
                                         pci_error_type, NULL, phb_status);
 
92
        phb_unlock(phb);
 
93
 
 
94
        return rc;
 
95
}
 
96
opal_call(OPAL_PCI_EEH_FREEZE_STATUS, opal_pci_eeh_freeze_status, 5);
 
97
 
 
98
static int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 
99
                                         uint64_t eeh_action_token)
 
100
{
 
101
        struct phb *phb = pci_get_phb(phb_id);
 
102
        int64_t rc;
 
103
 
 
104
        if (!phb)
 
105
                return OPAL_PARAMETER;
 
106
        if (!phb->ops->eeh_freeze_clear)
 
107
                return OPAL_UNSUPPORTED;
 
108
        phb_lock(phb);
 
109
        rc = phb->ops->eeh_freeze_clear(phb, pe_number, eeh_action_token);
 
110
        phb_unlock(phb);
 
111
 
 
112
        return rc;
 
113
}
 
114
opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, opal_pci_eeh_freeze_clear, 3);
 
115
 
 
116
static int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
 
117
                                       uint64_t eeh_action_token)
 
118
{
 
119
        struct phb *phb = pci_get_phb(phb_id);
 
120
        int64_t rc;
 
121
 
 
122
        if (!phb)
 
123
                return OPAL_PARAMETER;
 
124
        if (!phb->ops->eeh_freeze_set)
 
125
                return OPAL_UNSUPPORTED;
 
126
        phb_lock(phb);
 
127
        rc = phb->ops->eeh_freeze_set(phb, pe_number, eeh_action_token);
 
128
        phb_unlock(phb);
 
129
 
 
130
        return rc;
 
131
}
 
132
opal_call(OPAL_PCI_EEH_FREEZE_SET, opal_pci_eeh_freeze_set, 3);
 
133
 
 
134
static int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no,
 
135
                                   uint32_t type, uint32_t func,
 
136
                                   uint64_t addr, uint64_t mask)
 
137
{
 
138
        struct phb *phb = pci_get_phb(phb_id);
 
139
        int64_t rc;
 
140
 
 
141
        if (!phb)
 
142
                return OPAL_PARAMETER;
 
143
        if (!phb->ops || !phb->ops->err_inject)
 
144
                return OPAL_UNSUPPORTED;
 
145
 
 
146
        if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
 
147
            type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64)
 
148
                return OPAL_PARAMETER;
 
149
 
 
150
        phb_lock(phb);
 
151
        rc = phb->ops->err_inject(phb, pe_no, type, func, addr, mask);
 
152
        phb_unlock(phb);
 
153
 
 
154
        return rc;
 
155
}
 
156
opal_call(OPAL_PCI_ERR_INJECT, opal_pci_err_inject, 6);
 
157
 
 
158
static int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 
159
                                        uint16_t window_num, uint16_t enable)
 
160
{
 
161
        struct phb *phb = pci_get_phb(phb_id);
 
162
        int64_t rc;
 
163
 
 
164
        if (!phb)
 
165
                return OPAL_PARAMETER;
 
166
        if (!phb->ops->phb_mmio_enable)
 
167
                return OPAL_UNSUPPORTED;
 
168
        phb_lock(phb);
 
169
        rc = phb->ops->phb_mmio_enable(phb, window_type, window_num, enable);
 
170
        phb_unlock(phb);
 
171
 
 
172
        return rc;
 
173
}
 
174
opal_call(OPAL_PCI_PHB_MMIO_ENABLE, opal_pci_phb_mmio_enable, 4);
 
175
 
 
176
static int64_t opal_pci_set_phb_mem_window(uint64_t phb_id,
 
177
                                           uint16_t window_type,
 
178
                                           uint16_t window_num,
 
179
                                           uint64_t addr,
 
180
                                           uint64_t pci_addr,
 
181
                                           uint64_t size)
 
182
{
 
183
        struct phb *phb = pci_get_phb(phb_id);
 
184
        int64_t rc;
 
185
 
 
186
        if (!phb)
 
187
                return OPAL_PARAMETER;
 
188
        if (!phb->ops->set_phb_mem_window)
 
189
                return OPAL_UNSUPPORTED;
 
190
        phb_lock(phb);
 
191
        rc = phb->ops->set_phb_mem_window(phb, window_type, window_num,
 
192
                                          addr, pci_addr, size);
 
193
        phb_unlock(phb);
 
194
 
 
195
        return rc;
 
196
}
 
197
opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, opal_pci_set_phb_mem_window, 6);
 
198
 
 
199
static int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 
200
                                           uint16_t window_type,
 
201
                                           uint16_t window_num,
 
202
                                           uint16_t segment_num)
 
203
{
 
204
        struct phb *phb = pci_get_phb(phb_id);
 
205
        int64_t rc;
 
206
 
 
207
        if (!phb)
 
208
                return OPAL_PARAMETER;
 
209
        if (!phb->ops->map_pe_mmio_window)
 
210
                return OPAL_UNSUPPORTED;
 
211
        phb_lock(phb);
 
212
        rc = phb->ops->map_pe_mmio_window(phb, pe_number, window_type,
 
213
                                          window_num, segment_num);
 
214
        phb_unlock(phb);
 
215
 
 
216
        return rc;
 
217
}
 
218
opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, opal_pci_map_pe_mmio_window, 5);
 
219
 
 
220
static int64_t opal_pci_set_phb_table_memory(uint64_t phb_id __unused,
 
221
                                             uint64_t rtt_addr __unused,
 
222
                                             uint64_t ivt_addr __unused,
 
223
                                             uint64_t ivt_len __unused,
 
224
                                             uint64_t rej_array_addr __unused,
 
225
                                             uint64_t peltv_addr __unused)
 
226
{
 
227
        /* IODA2 (P8) stuff, TODO */
 
228
        return OPAL_UNSUPPORTED;
 
229
}
 
230
opal_call(OPAL_PCI_SET_PHB_TABLE_MEMORY, opal_pci_set_phb_table_memory, 6);
 
231
 
 
232
static int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number,
 
233
                               uint64_t bus_dev_func, uint8_t bus_compare,
 
234
                               uint8_t dev_compare, uint8_t func_compare,
 
235
                               uint8_t pe_action)
 
236
{
 
237
        struct phb *phb = pci_get_phb(phb_id);
 
238
        int64_t rc;
 
239
 
 
240
        if (!phb)
 
241
                return OPAL_PARAMETER;
 
242
        if (!phb->ops->set_pe)
 
243
                return OPAL_UNSUPPORTED;
 
244
        phb_lock(phb);
 
245
        rc = phb->ops->set_pe(phb, pe_number, bus_dev_func, bus_compare,
 
246
                              dev_compare, func_compare, pe_action);
 
247
        phb_unlock(phb);
 
248
 
 
249
        return rc;
 
250
}
 
251
opal_call(OPAL_PCI_SET_PE, opal_pci_set_pe, 7);
 
252
 
 
253
static int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe,
 
254
                                  uint32_t child_pe, uint8_t state)
 
255
{
 
256
        struct phb *phb = pci_get_phb(phb_id);
 
257
        int64_t rc;
 
258
 
 
259
        if (!phb)
 
260
                return OPAL_PARAMETER;
 
261
        if (!phb->ops->set_peltv)
 
262
                return OPAL_UNSUPPORTED;
 
263
        phb_lock(phb);
 
264
        rc = phb->ops->set_peltv(phb, parent_pe, child_pe, state);
 
265
        phb_unlock(phb);
 
266
 
 
267
        return rc;
 
268
}
 
269
opal_call(OPAL_PCI_SET_PELTV, opal_pci_set_peltv, 4);
 
270
 
 
271
static int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number,
 
272
                                uint32_t pe_number)
 
273
{
 
274
        struct phb *phb = pci_get_phb(phb_id);
 
275
        int64_t rc;
 
276
 
 
277
        if (!phb)
 
278
                return OPAL_PARAMETER;
 
279
        if (!phb->ops->set_mve)
 
280
                return OPAL_UNSUPPORTED;
 
281
        phb_lock(phb);
 
282
        rc = phb->ops->set_mve(phb, mve_number, pe_number);
 
283
        phb_unlock(phb);
 
284
 
 
285
        return rc;
 
286
}
 
287
opal_call(OPAL_PCI_SET_MVE, opal_pci_set_mve, 3);
 
288
 
 
289
static int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 
290
                                       uint32_t state)
 
291
{
 
292
        struct phb *phb = pci_get_phb(phb_id);
 
293
        int64_t rc;
 
294
 
 
295
        if (!phb)
 
296
                return OPAL_PARAMETER;
 
297
        if (!phb->ops->set_mve_enable)
 
298
                return OPAL_UNSUPPORTED;
 
299
        phb_lock(phb);
 
300
        rc = phb->ops->set_mve_enable(phb, mve_number, state);
 
301
        phb_unlock(phb);
 
302
 
 
303
        return rc;
 
304
}
 
305
opal_call(OPAL_PCI_SET_MVE_ENABLE, opal_pci_set_mve_enable, 3);
 
306
 
 
307
static int64_t opal_pci_get_xive_reissue(uint64_t phb_id __unused,
 
308
                                         uint32_t xive_number __unused,
 
309
                                         uint8_t *p_bit __unused,
 
310
                                         uint8_t *q_bit __unused)
 
311
{
 
312
        /* IODA2 (P8) stuff, TODO */
 
313
        return OPAL_UNSUPPORTED;
 
314
}
 
315
opal_call(OPAL_PCI_GET_XIVE_REISSUE, opal_pci_get_xive_reissue, 4);
 
316
 
 
317
static int64_t opal_pci_set_xive_reissue(uint64_t phb_id __unused,
 
318
                                         uint32_t xive_number __unused,
 
319
                                         uint8_t p_bit __unused,
 
320
                                         uint8_t q_bit __unused)
 
321
{
 
322
        /* IODA2 (P8) stuff, TODO */
 
323
        return OPAL_UNSUPPORTED;
 
324
}
 
325
opal_call(OPAL_PCI_SET_XIVE_REISSUE, opal_pci_set_xive_reissue, 4);
 
326
 
 
327
static int64_t opal_pci_msi_eoi(uint64_t phb_id,
 
328
                                uint32_t hwirq)
 
329
{
 
330
        struct phb *phb = pci_get_phb(phb_id);
 
331
        int64_t rc;
 
332
 
 
333
        if (!phb)
 
334
                return OPAL_PARAMETER;
 
335
        if (!phb->ops->pci_msi_eoi)
 
336
                return OPAL_UNSUPPORTED;
 
337
        phb_lock(phb);
 
338
        rc = phb->ops->pci_msi_eoi(phb, hwirq);
 
339
        phb_unlock(phb);
 
340
 
 
341
        return rc;
 
342
}
 
343
opal_call(OPAL_PCI_MSI_EOI, opal_pci_msi_eoi, 2);
 
344
 
 
345
static int64_t opal_pci_tce_kill(uint64_t phb_id,
 
346
                                 uint32_t kill_type,
 
347
                                 uint32_t pe_num, uint32_t tce_size,
 
348
                                 uint64_t dma_addr, uint32_t npages)
 
349
{
 
350
        struct phb *phb = pci_get_phb(phb_id);
 
351
        int64_t rc;
 
352
 
 
353
        if (!phb)
 
354
                return OPAL_PARAMETER;
 
355
        if (!phb->ops->tce_kill)
 
356
                return OPAL_UNSUPPORTED;
 
357
        phb_lock(phb);
 
358
        rc = phb->ops->tce_kill(phb, kill_type, pe_num, tce_size,
 
359
                                dma_addr, npages);
 
360
        phb_unlock(phb);
 
361
 
 
362
        return rc;
 
363
}
 
364
opal_call(OPAL_PCI_TCE_KILL, opal_pci_tce_kill, 6);
 
365
 
 
366
static int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 
367
                                    uint32_t xive_num)
 
368
{
 
369
        struct phb *phb = pci_get_phb(phb_id);
 
370
        int64_t rc;
 
371
 
 
372
        if (!phb)
 
373
                return OPAL_PARAMETER;
 
374
        if (!phb->ops->set_xive_pe)
 
375
                return OPAL_UNSUPPORTED;
 
376
        phb_lock(phb);
 
377
        rc = phb->ops->set_xive_pe(phb, pe_number, xive_num);
 
378
        phb_unlock(phb);
 
379
 
 
380
        return rc;
 
381
}
 
382
opal_call(OPAL_PCI_SET_XIVE_PE, opal_pci_set_xive_pe, 3);
 
383
 
 
384
static int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 
385
                                    int32_t *interrupt_source_number)
 
386
{
 
387
        struct phb *phb = pci_get_phb(phb_id);
 
388
        int64_t rc;
 
389
 
 
390
        if (!phb)
 
391
                return OPAL_PARAMETER;
 
392
        if (!phb->ops->get_xive_source)
 
393
                return OPAL_UNSUPPORTED;
 
394
        phb_lock(phb);
 
395
        rc = phb->ops->get_xive_source(phb, xive_num, interrupt_source_number);
 
396
        phb_unlock(phb);
 
397
 
 
398
        return rc;
 
399
}
 
400
opal_call(OPAL_GET_XIVE_SOURCE, opal_get_xive_source, 3);
 
401
 
 
402
static int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number,
 
403
                               uint32_t xive_num, uint8_t msi_range,
 
404
                               uint32_t *msi_address, uint32_t *message_data)
 
405
{
 
406
        struct phb *phb = pci_get_phb(phb_id);
 
407
        int64_t rc;
 
408
 
 
409
        if (!phb)
 
410
                return OPAL_PARAMETER;
 
411
        if (!phb->ops->get_msi_32)
 
412
                return OPAL_UNSUPPORTED;
 
413
        phb_lock(phb);
 
414
        rc = phb->ops->get_msi_32(phb, mve_number, xive_num, msi_range,
 
415
                                  msi_address, message_data);
 
416
        phb_unlock(phb);
 
417
 
 
418
        return rc;
 
419
}
 
420
opal_call(OPAL_GET_MSI_32, opal_get_msi_32, 6);
 
421
 
 
422
static int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 
423
                               uint32_t xive_num, uint8_t msi_range,
 
424
                               uint64_t *msi_address, uint32_t *message_data)
 
425
{
 
426
        struct phb *phb = pci_get_phb(phb_id);
 
427
        int64_t rc;
 
428
 
 
429
        if (!phb)
 
430
                return OPAL_PARAMETER;
 
431
        if (!phb->ops->get_msi_64)
 
432
                return OPAL_UNSUPPORTED;
 
433
        phb_lock(phb);
 
434
        rc = phb->ops->get_msi_64(phb, mve_number, xive_num, msi_range,
 
435
                                  msi_address, message_data);
 
436
        phb_unlock(phb);
 
437
 
 
438
        return rc;
 
439
}
 
440
opal_call(OPAL_GET_MSI_64, opal_get_msi_64, 6);
 
441
 
 
442
static int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number,
 
443
                                          uint16_t window_id,
 
444
                                          uint16_t tce_levels,
 
445
                                          uint64_t tce_table_addr,
 
446
                                          uint64_t tce_table_size,
 
447
                                          uint64_t tce_page_size)
 
448
{
 
449
        struct phb *phb = pci_get_phb(phb_id);
 
450
        int64_t rc;
 
451
 
 
452
        if (!phb)
 
453
                return OPAL_PARAMETER;
 
454
        if (!phb->ops->map_pe_dma_window)
 
455
                return OPAL_UNSUPPORTED;
 
456
        phb_lock(phb);
 
457
        rc = phb->ops->map_pe_dma_window(phb, pe_number, window_id,
 
458
                                         tce_levels, tce_table_addr,
 
459
                                         tce_table_size, tce_page_size);
 
460
        phb_unlock(phb);
 
461
 
 
462
        return rc;
 
463
}
 
464
opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, opal_pci_map_pe_dma_window, 7);
 
465
 
 
466
static int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id,
 
467
                                               uint16_t pe_number,
 
468
                                               uint16_t window_id,
 
469
                                               uint64_t pci_start_addr,
 
470
                                               uint64_t pci_mem_size)
 
471
{
 
472
        struct phb *phb = pci_get_phb(phb_id);
 
473
        int64_t rc;
 
474
 
 
475
        if (!phb)
 
476
                return OPAL_PARAMETER;
 
477
        if (!phb->ops->map_pe_dma_window_real)
 
478
                return OPAL_UNSUPPORTED;
 
479
        phb_lock(phb);
 
480
        rc = phb->ops->map_pe_dma_window_real(phb, pe_number, window_id,
 
481
                                              pci_start_addr, pci_mem_size);
 
482
        phb_unlock(phb);
 
483
 
 
484
        return rc;
 
485
}
 
486
opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, opal_pci_map_pe_dma_window_real, 5);
 
487
 
 
488
static int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope,
 
489
                              uint8_t assert_state)
 
490
{
 
491
        struct pci_slot *slot = pci_slot_find(id);
 
492
        struct phb *phb = slot ? slot->phb : NULL;
 
493
        int64_t rc = OPAL_SUCCESS;
 
494
 
 
495
        if (!slot || !phb)
 
496
                return OPAL_PARAMETER;
 
497
        if (assert_state != OPAL_ASSERT_RESET &&
 
498
            assert_state != OPAL_DEASSERT_RESET)
 
499
                return OPAL_PARAMETER;
 
500
 
 
501
        phb_lock(phb);
 
502
 
 
503
        switch(reset_scope) {
 
504
        case OPAL_RESET_PHB_COMPLETE:
 
505
                /* Complete reset is applicable to PHB slot only */
 
506
                if (!slot->ops.creset || slot->pd) {
 
507
                        rc = OPAL_UNSUPPORTED;
 
508
                        break;
 
509
                }
 
510
 
 
511
                if (assert_state != OPAL_ASSERT_RESET)
 
512
                        break;
 
513
 
 
514
                rc = slot->ops.creset(slot);
 
515
                if (rc < 0)
 
516
                        prlog(PR_ERR, "SLOT-%016llx: Error %lld on complete reset\n",
 
517
                              slot->id, rc);
 
518
                break;
 
519
        case OPAL_RESET_PCI_FUNDAMENTAL:
 
520
                if (!slot->ops.freset) {
 
521
                        rc = OPAL_UNSUPPORTED;
 
522
                        break;
 
523
                }
 
524
 
 
525
                /* We need do nothing on deassert time */
 
526
                if (assert_state != OPAL_ASSERT_RESET)
 
527
                        break;
 
528
 
 
529
                rc = slot->ops.freset(slot);
 
530
                if (rc < 0)
 
531
                        prlog(PR_ERR, "SLOT-%016llx: Error %lld on fundamental reset\n",
 
532
                              slot->id, rc);
 
533
                break;
 
534
        case OPAL_RESET_PCI_HOT:
 
535
                if (!slot->ops.hreset) {
 
536
                        rc = OPAL_UNSUPPORTED;
 
537
                        break;
 
538
                }
 
539
 
 
540
                /* We need do nothing on deassert time */
 
541
                if (assert_state != OPAL_ASSERT_RESET)
 
542
                        break;
 
543
 
 
544
                rc = slot->ops.hreset(slot);
 
545
                if (rc < 0)
 
546
                        prlog(PR_ERR, "SLOT-%016llx: Error %lld on hot reset\n",
 
547
                              slot->id, rc);
 
548
                break;
 
549
        case OPAL_RESET_PCI_IODA_TABLE:
 
550
                /* It's allowed on PHB slot only */
 
551
                if (slot->pd || !phb->ops || !phb->ops->ioda_reset) {
 
552
                        rc = OPAL_UNSUPPORTED;
 
553
                        break;
 
554
                }
 
555
 
 
556
                if (assert_state != OPAL_ASSERT_RESET)
 
557
                        break;
 
558
 
 
559
                rc = phb->ops->ioda_reset(phb, true);
 
560
                break;
 
561
        case OPAL_RESET_PHB_ERROR:
 
562
                /* It's allowed on PHB slot only */
 
563
                if (slot->pd || !phb->ops || !phb->ops->papr_errinjct_reset) {
 
564
                        rc = OPAL_UNSUPPORTED;
 
565
                        break;
 
566
                }
 
567
 
 
568
                if (assert_state != OPAL_ASSERT_RESET)
 
569
                        break;
 
570
 
 
571
                rc = phb->ops->papr_errinjct_reset(phb);
 
572
                break;
 
573
        default:
 
574
                rc = OPAL_UNSUPPORTED;
 
575
        }
 
576
        phb_unlock(phb);
 
577
 
 
578
        return (rc > 0) ? tb_to_msecs(rc) : rc;
 
579
}
 
580
opal_call(OPAL_PCI_RESET, opal_pci_reset, 3);
 
581
 
 
582
static int64_t opal_pci_reinit(uint64_t phb_id,
 
583
                               uint64_t reinit_scope,
 
584
                               uint64_t data)
 
585
{
 
586
        struct phb *phb = pci_get_phb(phb_id);
 
587
        int64_t rc;
 
588
 
 
589
        if (!phb)
 
590
                return OPAL_PARAMETER;
 
591
        if (!phb->ops || !phb->ops->pci_reinit)
 
592
                return OPAL_UNSUPPORTED;
 
593
 
 
594
        phb_lock(phb);
 
595
        rc = phb->ops->pci_reinit(phb, reinit_scope, data);
 
596
        phb_unlock(phb);
 
597
 
 
598
        return rc;
 
599
}
 
600
opal_call(OPAL_PCI_REINIT, opal_pci_reinit, 3);
 
601
 
 
602
static int64_t opal_pci_poll(uint64_t id)
 
603
{
 
604
        struct pci_slot *slot = pci_slot_find(id);
 
605
        struct phb *phb = slot ? slot->phb : NULL;
 
606
        int64_t rc;
 
607
 
 
608
        if (!slot || !phb)
 
609
                return OPAL_PARAMETER;
 
610
        if (!slot->ops.poll)
 
611
                return OPAL_UNSUPPORTED;
 
612
 
 
613
        phb_lock(phb);
 
614
        rc = slot->ops.poll(slot);
 
615
        phb_unlock(phb);
 
616
 
 
617
        /* Return milliseconds for caller to sleep: round up */
 
618
        if (rc > 0) {
 
619
                rc = tb_to_msecs(rc);
 
620
                if (rc == 0)
 
621
                        rc = 1;
 
622
        }
 
623
 
 
624
        return rc;
 
625
}
 
626
opal_call(OPAL_PCI_POLL, opal_pci_poll, 1);
 
627
 
 
628
static int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data)
 
629
{
 
630
        struct pci_slot *slot = pci_slot_find(id);
 
631
        struct phb *phb = slot ? slot->phb : NULL;
 
632
        uint8_t *presence = (uint8_t *)data;
 
633
        int64_t rc;
 
634
 
 
635
        if (!slot || !phb)
 
636
                return OPAL_PARAMETER;
 
637
        if (!slot->ops.get_presence_state)
 
638
                return OPAL_UNSUPPORTED;
 
639
 
 
640
        phb_lock(phb);
 
641
        rc = slot->ops.get_presence_state(slot, presence);
 
642
        phb_unlock(phb);
 
643
 
 
644
        return rc;
 
645
}
 
646
opal_call(OPAL_PCI_GET_PRESENCE_STATE, opal_pci_get_presence_state, 2);
 
647
 
 
648
static int64_t opal_pci_get_power_state(uint64_t id, uint64_t data)
 
649
{
 
650
        struct pci_slot *slot = pci_slot_find(id);
 
651
        struct phb *phb = slot ? slot->phb : NULL;
 
652
        uint8_t *power_state = (uint8_t *)data;
 
653
        int64_t rc;
 
654
 
 
655
        if (!slot || !phb)
 
656
                return OPAL_PARAMETER;
 
657
        if (!slot->ops.get_power_state)
 
658
                return OPAL_UNSUPPORTED;
 
659
 
 
660
        phb_lock(phb);
 
661
        rc = slot->ops.get_power_state(slot, power_state);
 
662
        phb_unlock(phb);
 
663
 
 
664
        return rc;
 
665
}
 
666
opal_call(OPAL_PCI_GET_POWER_STATE, opal_pci_get_power_state, 2);
 
667
 
 
668
static void set_power_timer(struct timer *t __unused, void *data,
 
669
                            uint64_t now __unused)
 
670
{
 
671
        struct pci_slot *slot = data;
 
672
        struct phb *phb = slot->phb;
 
673
        struct pci_device *pd = slot->pd;
 
674
        struct dt_node *dn = pd->dn;
 
675
        uint8_t link;
 
676
 
 
677
        switch (slot->state) {
 
678
        case PCI_SLOT_STATE_SPOWER_START:
 
679
                if (slot->retries-- == 0) {
 
680
                        pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
 
681
                        opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL,
 
682
                                       slot->async_token, dn->phandle,
 
683
                                       slot->power_state, OPAL_BUSY);
 
684
                } else {
 
685
                        schedule_timer(&slot->timer, msecs_to_tb(10));
 
686
                }
 
687
 
 
688
                break;
 
689
        case PCI_SLOT_STATE_SPOWER_DONE:
 
690
                if (slot->power_state == OPAL_PCI_SLOT_POWER_OFF) {
 
691
                        pci_remove_bus(phb, &pd->children);
 
692
                        pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
 
693
                        opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL,
 
694
                                       slot->async_token, dn->phandle,
 
695
                                       OPAL_PCI_SLOT_POWER_OFF, OPAL_SUCCESS);
 
696
                        break;
 
697
                }
 
698
 
 
699
                /* Power on */
 
700
                if (slot->ops.get_link_state(slot, &link) != OPAL_SUCCESS)
 
701
                        link = 0;
 
702
                if (link) {
 
703
                        slot->ops.prepare_link_change(slot, true);
 
704
                        pci_scan_bus(phb, pd->secondary_bus,
 
705
                                     pd->subordinate_bus,
 
706
                                     &pd->children, pd, true);
 
707
                        pci_add_device_nodes(phb, &pd->children, dn,
 
708
                                             &phb->lstate, 0);
 
709
                        pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
 
710
                        opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL,
 
711
                                       slot->async_token, dn->phandle,
 
712
                                       OPAL_PCI_SLOT_POWER_ON, OPAL_SUCCESS);
 
713
                } else if (slot->retries-- == 0) {
 
714
                        pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
 
715
                        opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL,
 
716
                                       slot->async_token, dn->phandle,
 
717
                                       OPAL_PCI_SLOT_POWER_ON, OPAL_BUSY);
 
718
                } else {
 
719
                        schedule_timer(&slot->timer, msecs_to_tb(10));
 
720
                }
 
721
 
 
722
                break;
 
723
        default:
 
724
                prlog(PR_ERR, "PCI SLOT %016llx: Unexpected state 0x%08x\n",
 
725
                      slot->id, slot->state);
 
726
        }
 
727
}
 
728
 
 
729
static int64_t opal_pci_set_power_state(uint64_t async_token,
 
730
                                        uint64_t id,
 
731
                                        uint64_t data)
 
732
{
 
733
        struct pci_slot *slot = pci_slot_find(id);
 
734
        struct phb *phb = slot ? slot->phb : NULL;
 
735
        struct pci_device *pd = slot ? slot->pd : NULL;
 
736
        uint8_t *state = (uint8_t *)data;
 
737
        int64_t rc;
 
738
 
 
739
        if (!slot || !phb)
 
740
                return OPAL_PARAMETER;
 
741
 
 
742
        phb_lock(phb);
 
743
        switch (*state) {
 
744
        case OPAL_PCI_SLOT_POWER_OFF:
 
745
                if (!slot->ops.prepare_link_change ||
 
746
                    !slot->ops.set_power_state)
 
747
                        return OPAL_UNSUPPORTED;
 
748
 
 
749
                slot->async_token = async_token;
 
750
                slot->ops.prepare_link_change(slot, false);
 
751
                rc = slot->ops.set_power_state(slot, PCI_SLOT_POWER_OFF);
 
752
                break;
 
753
        case OPAL_PCI_SLOT_POWER_ON:
 
754
                if (!slot->ops.set_power_state ||
 
755
                    !slot->ops.get_link_state)
 
756
                        return OPAL_UNSUPPORTED;
 
757
 
 
758
                slot->async_token = async_token;
 
759
                rc = slot->ops.set_power_state(slot, PCI_SLOT_POWER_ON);
 
760
                break;
 
761
        case OPAL_PCI_SLOT_OFFLINE:
 
762
                if (!pd)
 
763
                        return OPAL_PARAMETER;
 
764
 
 
765
                pci_remove_bus(phb, &pd->children);
 
766
                rc = OPAL_SUCCESS;
 
767
                break;
 
768
        case OPAL_PCI_SLOT_ONLINE:
 
769
                if (!pd)
 
770
                        return OPAL_PARAMETER;
 
771
                pci_scan_bus(phb, pd->secondary_bus, pd->subordinate_bus,
 
772
                             &pd->children, pd, true);
 
773
                pci_add_device_nodes(phb, &pd->children, pd->dn,
 
774
                                     &phb->lstate, 0);
 
775
                rc = OPAL_SUCCESS;
 
776
                break;
 
777
        default:
 
778
                rc = OPAL_PARAMETER;
 
779
        }
 
780
 
 
781
        phb_unlock(phb);
 
782
        if (rc == OPAL_ASYNC_COMPLETION) {
 
783
                slot->retries = 500;
 
784
                init_timer(&slot->timer, set_power_timer, slot);
 
785
                schedule_timer(&slot->timer, msecs_to_tb(10));
 
786
        }
 
787
 
 
788
        return rc;
 
789
}
 
790
opal_call(OPAL_PCI_SET_POWER_STATE, opal_pci_set_power_state, 3);
 
791
 
 
792
static int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id,
 
793
                                           uint64_t tce_mem_addr,
 
794
                                           uint64_t tce_mem_size)
 
795
{
 
796
        struct phb *phb = pci_get_phb(phb_id);
 
797
        int64_t rc;
 
798
 
 
799
        if (!phb)
 
800
                return OPAL_PARAMETER;
 
801
        if (!phb->ops->set_phb_tce_memory)
 
802
                return OPAL_UNSUPPORTED;
 
803
        phb_lock(phb);
 
804
        rc = phb->ops->set_phb_tce_memory(phb, tce_mem_addr, tce_mem_size);
 
805
        phb_unlock(phb);
 
806
 
 
807
        return rc;
 
808
}
 
809
opal_call(OPAL_PCI_SET_PHB_TCE_MEMORY, opal_pci_set_phb_tce_memory, 3);
 
810
 
 
811
static int64_t opal_pci_get_phb_diag_data(uint64_t phb_id,
 
812
                                          void *diag_buffer,
 
813
                                          uint64_t diag_buffer_len)
 
814
{
 
815
        struct phb *phb = pci_get_phb(phb_id);
 
816
        int64_t rc;
 
817
 
 
818
        if (!phb)
 
819
                return OPAL_PARAMETER;
 
820
        if (!phb->ops->get_diag_data)
 
821
                return OPAL_UNSUPPORTED;
 
822
        phb_lock(phb);
 
823
        rc = phb->ops->get_diag_data(phb, diag_buffer, diag_buffer_len);
 
824
        phb_unlock(phb);
 
825
 
 
826
        return rc;
 
827
}
 
828
opal_call(OPAL_PCI_GET_PHB_DIAG_DATA, opal_pci_get_phb_diag_data, 3);
 
829
 
 
830
static int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id,
 
831
                                           void *diag_buffer,
 
832
                                           uint64_t diag_buffer_len)
 
833
{
 
834
        struct phb *phb = pci_get_phb(phb_id);
 
835
        int64_t rc;
 
836
 
 
837
        if (!phb)
 
838
                return OPAL_PARAMETER;
 
839
        if (!phb->ops->get_diag_data2)
 
840
                return OPAL_UNSUPPORTED;
 
841
        phb_lock(phb);
 
842
        rc = phb->ops->get_diag_data2(phb, diag_buffer, diag_buffer_len);
 
843
        phb_unlock(phb);
 
844
 
 
845
        return rc;
 
846
}
 
847
opal_call(OPAL_PCI_GET_PHB_DIAG_DATA2, opal_pci_get_phb_diag_data2, 3);
 
848
 
 
849
static int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
 
850
                                   uint16_t *pci_error_type, uint16_t *severity)
 
851
{
 
852
        struct phb *phb = pci_get_phb(phb_id);
 
853
        int64_t rc;
 
854
 
 
855
        if (!phb)
 
856
                return OPAL_PARAMETER;
 
857
        if (!phb->ops->next_error)
 
858
                return OPAL_UNSUPPORTED;
 
859
        phb_lock(phb);
 
860
 
 
861
        opal_pci_eeh_clear_evt(phb_id);
 
862
        rc = phb->ops->next_error(phb, first_frozen_pe, pci_error_type,
 
863
                                  severity);
 
864
        phb_unlock(phb);
 
865
 
 
866
        return rc;
 
867
}
 
868
opal_call(OPAL_PCI_NEXT_ERROR, opal_pci_next_error, 4);
 
869
 
 
870
static int64_t opal_pci_eeh_freeze_status2(uint64_t phb_id, uint64_t pe_number,
 
871
                                           uint8_t *freeze_state,
 
872
                                           uint16_t *pci_error_type,
 
873
                                           uint16_t *severity,
 
874
                                           uint64_t *phb_status)
 
875
{
 
876
        struct phb *phb = pci_get_phb(phb_id);
 
877
        int64_t rc;
 
878
 
 
879
        if (!phb)
 
880
                return OPAL_PARAMETER;
 
881
        if (!phb->ops->eeh_freeze_status)
 
882
                return OPAL_UNSUPPORTED;
 
883
        phb_lock(phb);
 
884
        rc = phb->ops->eeh_freeze_status(phb, pe_number, freeze_state,
 
885
                                         pci_error_type, severity, phb_status);
 
886
        phb_unlock(phb);
 
887
 
 
888
        return rc;
 
889
}
 
890
opal_call(OPAL_PCI_EEH_FREEZE_STATUS2, opal_pci_eeh_freeze_status2, 6);
 
891
 
 
892
static int64_t opal_pci_set_phb_capi_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number)
 
893
{
 
894
        struct phb *phb = pci_get_phb(phb_id);
 
895
        int64_t rc;
 
896
 
 
897
        if (!phb)
 
898
                return OPAL_PARAMETER;
 
899
        if (!phb->ops->set_capi_mode)
 
900
                return OPAL_UNSUPPORTED;
 
901
 
 
902
        phb_lock(phb);
 
903
        rc = phb->ops->set_capi_mode(phb, mode, pe_number);
 
904
        phb_unlock(phb);
 
905
        return rc;
 
906
}
 
907
opal_call(OPAL_PCI_SET_PHB_CAPI_MODE, opal_pci_set_phb_capi_mode, 3);