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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/micronas/vct/dcgu.c
 
1
/*
 
2
 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
 
3
 *
 
4
 * Original Author Guenter Gebhardt
 
5
 * Copyright (C) 2006 Micronas GmbH
 
6
 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
9
 
 
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#include <common.h>
 
11
#include <asm/errno.h>
 
12
 
 
13
#include "vct.h"
 
14
 
 
15
int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
 
16
{
 
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        u32 enable;
 
18
        union dcgu_clk_en1 en1;
 
19
        union dcgu_clk_en2 en2;
 
20
 
 
21
        switch (setup) {
 
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        case DCGU_SWITCH_ON:
 
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                enable = 1;
 
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                break;
 
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        case DCGU_SWITCH_OFF:
 
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                enable = 0;
 
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                break;
 
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        default:
 
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                printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
 
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                       setup);
 
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                return -EINVAL;
 
32
        }
 
33
 
 
34
        if (module == DCGU_HW_MODULE_CPU)
 
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                en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
 
36
        else
 
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                en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
 
38
 
 
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        switch (module) {
 
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        case DCGU_HW_MODULE_MSMC:
 
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                en1.bits.en_clkmsmc = enable;
 
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                break;
 
43
        case DCGU_HW_MODULE_SSI_S:
 
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                en1.bits.en_clkssi_s = enable;
 
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                break;
 
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        case DCGU_HW_MODULE_SSI_M:
 
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                en1.bits.en_clkssi_m = enable;
 
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                break;
 
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        case DCGU_HW_MODULE_SMC:
 
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                en1.bits.en_clksmc = enable;
 
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                break;
 
52
        case DCGU_HW_MODULE_EBI:
 
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                en1.bits.en_clkebi = enable;
 
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                break;
 
55
        case DCGU_HW_MODULE_USB_PLL:
 
56
                en1.bits.en_usbpll = enable;
 
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                break;
 
58
        case DCGU_HW_MODULE_USB_60:
 
59
                en1.bits.en_clkusb60 = enable;
 
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                break;
 
61
        case DCGU_HW_MODULE_USB_24:
 
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                en1.bits.en_clkusb24 = enable;
 
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                break;
 
64
        case DCGU_HW_MODULE_UART_2:
 
65
                en1.bits.en_clkuart2 = enable;
 
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                break;
 
67
        case DCGU_HW_MODULE_UART_1:
 
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                en1.bits.en_clkuart1 = enable;
 
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                break;
 
70
        case DCGU_HW_MODULE_PERI:
 
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                en1.bits.en_clkperi20 = enable;
 
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                break;
 
73
        case DCGU_HW_MODULE_CPU:
 
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                en2.bits.en_clkcpu = enable;
 
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                break;
 
76
        case DCGU_HW_MODULE_I2S:
 
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                en1.bits.en_clk_i2s_dly = enable;
 
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                break;
 
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        case DCGU_HW_MODULE_ABP_SCC:
 
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                en1.bits.en_clk_scc_abp = enable;
 
81
                break;
 
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        case DCGU_HW_MODULE_SPDIF:
 
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                en1.bits.en_clk_dtv_spdo = enable;
 
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                break;
 
85
        case DCGU_HW_MODULE_AD:
 
86
                en1.bits.en_clkad = enable;
 
87
                break;
 
88
        case DCGU_HW_MODULE_MVD:
 
89
                en1.bits.en_clkmvd = enable;
 
90
                break;
 
91
        case DCGU_HW_MODULE_TSD:
 
92
                en1.bits.en_clktsd = enable;
 
93
                break;
 
94
        case DCGU_HW_MODULE_GA:
 
95
                en1.bits.en_clkga = enable;
 
96
                break;
 
97
        case DCGU_HW_MODULE_DVP:
 
98
                en1.bits.en_clkdvp = enable;
 
99
                break;
 
100
        case DCGU_HW_MODULE_MR2:
 
101
                en1.bits.en_clkmr2 = enable;
 
102
                break;
 
103
        case DCGU_HW_MODULE_MR1:
 
104
                en1.bits.en_clkmr1 = enable;
 
105
                break;
 
106
        default:
 
107
                printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
 
108
                       __LINE__, module);
 
109
                return -EINVAL;
 
110
        }
 
111
 
 
112
        /*
 
113
         * The reg_read() following the reg_write() below forces the write to
 
114
         * be really done on the bus.
 
115
         * Otherwise the clock may not be switched on when this API function
 
116
         * returns, which may cause an bus error if a registers of the hardware
 
117
         * module connected to the clock is accessed.
 
118
         */
 
119
        if (module == DCGU_HW_MODULE_CPU) {
 
120
                reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
 
121
                en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
 
122
        } else {
 
123
                reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
 
124
                en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
 
125
        }
 
126
 
 
127
        return 0;
 
128
}
 
129
 
 
130
int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
 
131
{
 
132
        union dcgu_reset_unit1 val;
 
133
        u32 enable;
 
134
 
 
135
        switch (setup) {
 
136
        case DCGU_SWITCH_ON:
 
137
                enable = 1;
 
138
                break;
 
139
        case DCGU_SWITCH_OFF:
 
140
                enable = 0;
 
141
                break;
 
142
        default:
 
143
                printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
 
144
                       setup);
 
145
                return -EINVAL;
 
146
        }
 
147
 
 
148
        val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
 
149
        switch (module) {
 
150
        case DCGU_HW_MODULE_MSMC:
 
151
                val.bits.swreset_clkmsmc = enable;
 
152
                break;
 
153
        case DCGU_HW_MODULE_SSI_S:
 
154
                val.bits.swreset_clkssi_s = enable;
 
155
                break;
 
156
        case DCGU_HW_MODULE_SSI_M:
 
157
                val.bits.swreset_clkssi_m = enable;
 
158
                break;
 
159
        case DCGU_HW_MODULE_SMC:
 
160
                val.bits.swreset_clksmc = enable;
 
161
                break;
 
162
        case DCGU_HW_MODULE_EBI:
 
163
                val.bits.swreset_clkebi = enable;
 
164
                break;
 
165
        case DCGU_HW_MODULE_USB_60:
 
166
                val.bits.swreset_clkusb60 = enable;
 
167
                break;
 
168
        case DCGU_HW_MODULE_USB_24:
 
169
                val.bits.swreset_clkusb24 = enable;
 
170
                break;
 
171
        case DCGU_HW_MODULE_UART_2:
 
172
                val.bits.swreset_clkuart2 = enable;
 
173
                break;
 
174
        case DCGU_HW_MODULE_UART_1:
 
175
                val.bits.swreset_clkuart1 = enable;
 
176
                break;
 
177
        case DCGU_HW_MODULE_PWM:
 
178
                val.bits.swreset_pwm = enable;
 
179
                break;
 
180
        case DCGU_HW_MODULE_GPT:
 
181
                val.bits.swreset_gpt = enable;
 
182
                break;
 
183
        case DCGU_HW_MODULE_I2C2:
 
184
                val.bits.swreset_i2c2 = enable;
 
185
                break;
 
186
        case DCGU_HW_MODULE_I2C1:
 
187
                val.bits.swreset_i2c1 = enable;
 
188
                break;
 
189
        case DCGU_HW_MODULE_GPIO2:
 
190
                val.bits.swreset_gpio2 = enable;
 
191
                break;
 
192
        case DCGU_HW_MODULE_GPIO1:
 
193
                val.bits.swreset_gpio1 = enable;
 
194
                break;
 
195
        case DCGU_HW_MODULE_CPU:
 
196
                val.bits.swreset_clkcpu = enable;
 
197
                break;
 
198
        case DCGU_HW_MODULE_I2S:
 
199
                val.bits.swreset_clk_i2s_dly = enable;
 
200
                break;
 
201
        case DCGU_HW_MODULE_ABP_SCC:
 
202
                val.bits.swreset_clk_scc_abp = enable;
 
203
                break;
 
204
        case DCGU_HW_MODULE_SPDIF:
 
205
                val.bits.swreset_clk_dtv_spdo = enable;
 
206
                break;
 
207
        case DCGU_HW_MODULE_AD:
 
208
                val.bits.swreset_clkad = enable;
 
209
                break;
 
210
        case DCGU_HW_MODULE_MVD:
 
211
                val.bits.swreset_clkmvd = enable;
 
212
                break;
 
213
        case DCGU_HW_MODULE_TSD:
 
214
                val.bits.swreset_clktsd = enable;
 
215
                break;
 
216
        case DCGU_HW_MODULE_TSIO:
 
217
                val.bits.swreset_clktsio = enable;
 
218
                break;
 
219
        case DCGU_HW_MODULE_GA:
 
220
                val.bits.swreset_clkga = enable;
 
221
                break;
 
222
        case DCGU_HW_MODULE_MPC:
 
223
                val.bits.swreset_clkmpc = enable;
 
224
                break;
 
225
        case DCGU_HW_MODULE_CVE:
 
226
                val.bits.swreset_clkcve = enable;
 
227
                break;
 
228
        case DCGU_HW_MODULE_DVP:
 
229
                val.bits.swreset_clkdvp = enable;
 
230
                break;
 
231
        case DCGU_HW_MODULE_MR2:
 
232
                val.bits.swreset_clkmr2 = enable;
 
233
                break;
 
234
        case DCGU_HW_MODULE_MR1:
 
235
                val.bits.swreset_clkmr1 = enable;
 
236
                break;
 
237
        default:
 
238
                printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
 
239
                       __LINE__, module);
 
240
                return -EINVAL;
 
241
        }
 
242
        reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
 
243
 
 
244
        return 0;
 
245
}